CN115295409A - Wafer scribing method - Google Patents

Abstract

The embodiment of the disclosure provides a wafer scribing method, which comprises the following steps: providing a wafer, wherein the surface of the wafer is provided with a plurality of chip areas and scribing channels positioned between the chip areas; etching the wafer along the thickness direction of the wafer in the scribing channel to form a groove; and scribing the wafer along the groove to obtain a plurality of separated chips.

Description

Wafer Scribing Method

technical field

The present disclosure relates to the field of semiconductor manufacturing, in particular to a wafer scribing method.

Background technique

Wafers are the basic raw materials for manufacturing semiconductor devices and are widely used in various electronic devices. A wafer usually contains multiple chips, and in order to obtain a single chip, the entire wafer needs to be diced. The process of cutting the entire wafer into single chips according to the chip size is called wafer dicing.

Traditional wafer scribing uses a blade or laser cutting method to cut through the entire wafer from top to bottom in the dicing lane of the wafer to obtain a single chip. During the dicing process, it is easy to cause stress damage to the wafer, which may cause chipping or flying, which will damage the chip and reduce the yield of the chip. Although the damage to the chip during the cutting process can be reduced by increasing the width of the scribing lane, it will inevitably occupy the area of the chip area. Moreover, the traditional wafer scribing method has strict requirements on the performance of the blade or laser, and the cost is high.

Contents of the invention

In view of this, an embodiment of the present disclosure provides a wafer dicing method, including:

providing a wafer, the surface of the wafer has a plurality of chip areas and scribe lanes between each of the chip areas;

Etching the wafer along the thickness direction of the wafer in the scribing lane to form grooves;

Scribing the wafer along the grooves to obtain a plurality of separate chips.

In some embodiments, the etching of the wafer along the thickness direction of the wafer in the scribing lane to form grooves includes:

The wafer is etched in the scribing lane along the thickness direction of the wafer by using a through silicon via process to form grooves.

In some embodiments, the through-silicon via process is used to etch the wafer along the thickness direction of the wafer in the scribing lane to form grooves, including:

performing photolithographic treatment on the surface of the wafer to form a patterned photoresist layer;

Based on the pattern corresponding to the photoresist layer, the wafer is etched to form the trench; wherein, the pattern corresponding to the photoresist layer is located in the scribing lane.

In some embodiments, the etching the wafer includes:

The wafer is etched using dry etching and/or wet etching.

In some embodiments, the wafer dicing method also includes:

After the wafer is etched, the photoresist layer is removed.

In some embodiments, before scribing the wafer along the groove, the method further includes:

thinning the back side of the wafer, the back side of the wafer being the other side on which the grooves are formed.

In some embodiments, the trench has a depth less than or equal to 75% of the wafer thickness.

In some embodiments, the width of the groove is less than or equal to the width of the scribe lane.

In some embodiments, the wafer includes:

A substrate and a device formation layer on the substrate; the depth of the trench is greater than or equal to the thickness of the device formation layer.

In some embodiments, the device formation layer located in the chip region is used to form a chip.

The wafer scribing method provided by the embodiments of the present disclosure includes: providing a wafer, the surface of the wafer has a plurality of chip areas and dicing lanes between each of the chip areas; Etching the wafer in the thickness direction of the wafer to form grooves; dicing the wafer along the grooves to obtain a plurality of separate chips. In this way, by etching the wafer, forming a groove at the position of the scribing lane, and then cutting in the groove with the traditional method, the damage to the chip during cutting can be reduced, and the yield rate of the chip can be improved; at the same time, it can also ensure Does not occupy the area of the wafer chip area.

Description of drawings

FIG. 1 is a schematic flow diagram of a wafer dicing method provided by an embodiment of the present disclosure;

FIG. 2 is a partial top view of a wafer with a chip area and a scribe lane provided by an embodiment of the present disclosure;

FIG. 3 is a partial top view of a wafer with a chip area and a scribe lane provided by an embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional structure diagram of a groove provided by an embodiment of the present disclosure;

5 is a schematic cross-sectional structure diagram of a wafer with a device formation layer provided by an embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional structure diagram of a groove provided by an embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional structure diagram of a wafer coated with photoresist provided by an embodiment of the present disclosure.

Detailed ways

In order to facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to related drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments may not be described here, and well-known functions and structures may not be described in detail.

In general, a term can be understood at least in part from its usage in context. For example, the term "one or more" as used herein may be used in the singular to describe any feature, structure, or characteristic or may be used in the plural to describe a combination of features, structures, or characteristics, depending at least in part on the context. . Similarly, terms such as "a" or "the" may equally be read to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, pertaining to "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on context.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be provided in the following description, so as to explain the technical solution of the present disclosure. Preferred embodiments of the present disclosure are described in detail as follows, however, the present disclosure may have other embodiments besides these detailed descriptions.

As shown in FIG. 1, an embodiment of the present disclosure provides a wafer dicing method, including:

Step S101, providing a wafer, the surface of the wafer has a plurality of chip areas and dicing lanes between each of the chip areas;

Step S102, etching the wafer along the thickness direction of the wafer in the scribing lane to form grooves;

Step S103 , dicing the wafer along the grooves to obtain a plurality of separate chips.

The aforementioned wafer may be a wafer formed with a plurality of chips arranged in an array, or may be a bare wafer or a wafer grown with an epitaxial layer.

The substrate of the wafer may include semiconductor material, insulating material, conductive material or any combination thereof, and may be a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator may also be included. The epitaxial layer of the wafer may include silicon oxide, silicon nitride, etc., which are not specifically limited herein.

The chip area here is used to form various chips, for example, memory chips, processor chips, and the like. In the process involved in the embodiments of the present disclosure, the chips in the above-mentioned chip area are bare chips that have not been packaged. After performing the dicing operation in the embodiment of the present disclosure, the above-mentioned chip regions are separated, so that the chips on the same wafer are separated into independent dies. Then package and process chip products such as memory chips and processor chips.

In the embodiment of the present disclosure, there are scribing lanes between the chip regions of the wafer, and the scribing lanes may be positions to be diced that are determined during the process of making chips. During the chip manufacturing process, the chip area can be processed, and finally a chip can be formed in the chip area. Of course, during the chip manufacturing process, some structures or film layers can also be formed simultaneously on the scribing lane. However, these structures or film layers on the scribing lane do not affect devices in the chip area, so dicing can be performed on the scribing lane during the final scribing process.

In some embodiments, as shown in FIG. 2 , a scribe lane 102 may be included between two adjacent chip areas 101, and the width of the scribe lane 102 is W1, and the scribe lane 102 is the division of the two chip areas 101. The chip area 101 on both sides of the scribe lane 102 is separated by dicing process. In some other embodiments, as shown in FIG. 3 , there may also be two parallel scribing lanes 103 between two chip areas 101 , and there may be a certain scribing area between the two scribing lanes 103 . After dicing, not only the two chip regions 101 are separated, but also an independent dicing region is separated. The scribe area can be used to form some test structures during the manufacturing process and to perform tests during the manufacturing process. After dicing, these test structures are no longer needed, so they can be removed along with the dicing operation.

In the embodiment of the present disclosure, prior to dicing the above-mentioned wafer, grooves are formed on the dicing lane 102 by an etching process. The etching process may include dry etching or wet etching and the like.

The etching process can accurately locate the position of the lane 102 to be scribed on the wafer, and the width and depth of the groove formed by etching are easy to control. For example, it is known that the width of the scribing lane 102 is W1, and the thickness of the wafer is H1. In some embodiments, etching can be performed at the position where the scribe lane 102 is located by controlling the etching process parameters to form a trench 104 with a width W2 and a depth H2, as shown in FIG. 4 . Here, the width W2 of the groove 104 may be smaller than or equal to the width W1 of the scribe lane 102; the depth H2 of the groove 104 may be smaller than the thickness H1 of the wafer.

In some embodiments, as shown in FIG. 5 , the wafer includes: the wafer includes a substrate 100 and a device formation layer 110 on the substrate 100; the depth of the trench 104 is greater than or equal to the The thickness of the device forming layer 110 .

In some embodiments, the device formation layer 110 located in the chip region 101 is used to form a chip.

The device formation layer 110 may include various devices used to form the above-mentioned chip region 101 , and may also include various film layers, for example, a protective layer used to protect the chip structure. Certainly, the scribing area on the scribing lane 102 or between two scribing lanes 103 may also be covered by the device formation layer 110 and contain some devices or film layers. The device formation layer 110 mentioned here only generally describes the structure of a certain thickness in the wafer and may contain various device structures for forming chips, and is not limited to the actual specific structure of the chips contained in the wafer.

In an embodiment of the present disclosure, the depth of the trench formed by the above-mentioned etching method may be greater than the thickness of the above-mentioned device formation layer 110 . As shown in Figure 6, the wafer includes a substrate 100 and a device formation layer 110 located on the substrate 100, the thickness of the device formation layer 110 is H3, and the depth H2 of the trench 104 is greater than H3 but less than the thickness H1 of the wafer , that is, etch through the device formation layer 110 . In this way, when the wafer is diced, the wafer has a good mechanical stress situation, thereby reducing the situation of chipping and flying in the process of cutting the wafer, and at the same time avoiding the damage caused by cutting. Chip device layers cause damage that degrades chip performance.

In some embodiments, the depth H2 of the trench 104 is less than or equal to 75% of the thickness H1 of the wafer, and may be greater than the thickness H3 of the above-mentioned device formation layer 110 . That is, H3≦H2≦75%×H1. In this way, on the one hand, the force on the wafer during the subsequent dicing can be made uniform, and the situation of chipping and flying is not easy to occur, and the possibility of chip damage is reduced. On the other hand, it can reduce the occurrence of wafer breakage or other damage during the etching process.

In some embodiments, the width W2 of the trench 104 is less than or equal to the width W1 of the scribe lane 102 , ie W2≦W1. In this way, the damage to the chip caused by the deviation of the scribing position can be reduced, and due to the high precision of the etching process, there is no need for an overly wide scribing lane, which can improve the utilization rate of the wafer area, reduce costs, and improve product yield. .

In some embodiments, a TSV etching method may be used to etch the position where the scribe lane 102 is located to form the trench 104 with a controllable width and depth. The etching process may include dry etching or wet etching and the like.

Through-silicon via technology is a technology that realizes the interconnection between chips by making vertical conduction between chips and between wafers, and its core is to process through holes on the wafer. Using the TSV technology to etch on the scribe lane 102 can more precisely control the width and depth of the trench 104 formed by etching.

In some embodiments, the wafer is etched along the thickness direction of the wafer in the scribe lane 102 by using a through-silicon via process to form a trench 104, including:

performing photolithographic treatment on the surface of the wafer to form a patterned photoresist layer;

Based on the pattern corresponding to the photoresist layer, the wafer is etched to form the groove 104 ; wherein the pattern corresponding to the photoresist layer is located in the scribe lane 102 .

The photolithography treatment may be coating a photoresist layer on the surface of the wafer, and then forming a patterned photoresist layer through steps such as exposure and development. In the embodiment of the present disclosure, as shown in FIG. 7 , the pattern corresponding to the photoresist layer 120 is located at the position of the scribe line 102 of the wafer, and the position of the scribe line 102 is etched using the photoresist pattern as a mask, and The positions including the chip region 101 outside the scribing lane 102 are not etched. By controlling the etching process parameters, a trench 104 with a width of W2 and a depth of H2 is formed.

In some embodiments, the above TSV etching process may be a deep silicon etching process using plasma dry etching. First, the wafer surface is subjected to photolithography treatment, as shown in Figure 7, a patterned photoresist layer 120 is formed, and the pattern corresponding to the photoresist layer 120 is located at the position of the scribe lane 102 of the wafer; As a mask, a deep silicon etching machine is used to etch the position of the scribe line 102, and by controlling the etching process parameters, a trench 104 with a width of W2 and a depth of H2 is formed. Compared with the general etching process, the main difference of the above-mentioned deep silicon etching process is that the etching depth is much greater than that of the general silicon etching process. The etching depth of a general silicon etching process is usually less than 1 μm, while the etching depth of a through-silicon via etching process is tens of microns or even hundreds of microns, with a large aspect ratio. Therefore, by using the etching method of the above-mentioned deep silicon etching process, the trench 104 with a larger aspect ratio can be formed, that is, the depth H2 of the trench 104 can be made greater than several tens of times W2, thereby obtaining a better trench 104 morphology.

In some embodiments, the above TSV etching process may be a wet etching method. The wet etching process uses an etchant to etch the etchant, and the etchant has a corrosive effect on the etchant. First, the wafer surface is subjected to photolithography treatment to form a patterned photoresist layer 120, and the pattern corresponding to the photoresist layer 120 is located at the position of the scribing lane 102 of the wafer; then, sulfuric acid, nitric acid, and hydrofluoric acid can be selected , Potassium hydroxide and other solutions that can corrode the wafer are used as etching solution. Based on the corresponding pattern of the photoresist layer 120, wet etching equipment is used in the wet etching tank to use the etching solution on the scribe line 102. Etching is performed at the position, or it can be etched by spraying. By controlling the etching process parameters, a trench 104 with a width of W2 and a depth of H2 is formed. Compared with the dry etching process, the wet etching process has lower damage to the surface, and has good repeatability, simple operation, and fast etching rate.

In some embodiments, the wafer dicing method further includes: removing the photoresist layer 120 after etching the wafer.

As a mask material, photoresist plays the role of pattern replication and transmission in the etching process, and once the etching process is completed, the mission of photoresist is completed, and it needs to be completely removed.

During the etching process, the surface of the wafer is subjected to photolithography treatment to form a patterned photoresist layer 120 which covers the chip area 101 on the surface of the wafer. After the etching is completed, the photoresist layer 120 on the surface of the wafer can be exposed to a plasma atmosphere, such as oxygen plasma, through the reaction of active ions in the plasma atmosphere with the photoresist, and the bombardment of the plasma. The photoresist is removed to obtain a clean wafer.

In some embodiments, before scribing the wafer along the groove 104, the method further includes: thinning the back side of the wafer, the back side of the wafer is formed by forming The other side of the groove 104.

Wafer backside thinning is to perform grinding, grinding, chemical mechanical polishing, and plasma etching on the backside substrate material of the wafer that has completed the function, and remove a certain thickness of material on the backside of the wafer to make it reach the required thickness. The thinned chip has at least the following advantages: (1) improve thermal diffusion efficiency, and thin chips are more conducive to heat dissipation; (2) reduce the volume of chip packaging, and microelectronic products are increasingly developing in the direction of thinner and smaller, reducing chip packaging Volume is the only way to adapt to this development trend; (3) To improve the mechanical properties, the mechanical properties of the chip after thinning are significantly improved. The thinner the silicon wafer, the better its flexibility and the smaller the stress caused by external impact; (4) ) Reduce the amount of dicing processing, and then cut after thinning, which can reduce the processing amount during scribing and reduce the incidence of chip chipping.

After removing the photoresist on the surface of the wafer, the clean wafer is bonded to the thin film, and then the thin film and the wafer are sucked onto the porous ceramic carrier by vacuum, and the wafer is ground by a grinder Processing to obtain a wafer of desired thickness; then dicing the thinned wafer to obtain multiple separate chips. Thinning the back of the wafer is beneficial to make the chip obtained after dicing meet the requirements of the subsequent packaging process, as well as the physical strength, heat dissipation and size of the chip.

It should be noted that the features disclosed in several method or device embodiments provided by the embodiments of the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only the specific implementation of the embodiments of the present disclosure, but the scope of protection of the embodiments of the present disclosure is not limited thereto. Anyone familiar with the technical field can easily Any changes or substitutions that come to mind should fall within the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the protection scope of the claims.

Claims (10)

1. A wafer dicing method, characterized in that the method comprises: providing a wafer, the surface of the wafer has a plurality of chip areas and scribe lanes between each of the chip areas; Etching the wafer along the thickness direction of the wafer in the scribing lane to form grooves; Scribing the wafer along the grooves to obtain a plurality of separate chips. 2. The method according to claim 1, wherein said etching said wafer along said wafer thickness direction in said dicing lane to form a groove comprises: The wafer is etched in the scribing lane along the thickness direction of the wafer by using a through silicon via process to form grooves. 3. The method according to claim 2, characterized in that, said through silicon via process is used to etch the wafer along the thickness direction of the wafer in the scribing lane to form trenches, comprising : performing photolithographic treatment on the surface of the wafer to form a patterned photoresist layer; Based on the pattern corresponding to the photoresist layer, the wafer is etched to form the trench; wherein, the pattern corresponding to the photoresist layer is located in the scribing lane. 4. The method according to claim 3, wherein said etching said wafer comprises: The wafer is etched using dry etching and/or wet etching. 5. The method of claim 3, further comprising: After the wafer is etched, the photoresist layer is removed. 6. The method according to claim 1, wherein before the wafer is diced along the groove, the method further comprises: thinning the back side of the wafer, the back side of the wafer being the other side on which the grooves are formed. 7. The method of claim 1, wherein the depth of the trench is less than or equal to 75% of the thickness of the wafer. 8. The method of claim 1, wherein a width of the groove is smaller than or equal to a width of the scribe lane. 9. The method of claim 1, wherein the wafer comprises: A substrate and a device formation layer on the substrate; the depth of the trench is greater than or equal to the thickness of the device formation layer. 10. The method according to claim 9, wherein the device formation layer located in the chip area is used to form a chip.

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