CN115293092A - Design method of PCell layout - Google Patents

Abstract

The invention provides a design method of a PCell layout, which comprises the steps of firstly obtaining the PCell layout of a target device, wherein the PCell layout is provided with a plurality of process layers, each process layer is provided with a plurality of graphs, and then transforming at least one process layer and/or at least one graph so as to distort the PCell layout. The distorted PCell layout is provided for a customer, the customer can use the PCell layout corresponding to the default CDF parameter or modify the CDF parameter to update the PCell layout, and meanwhile, the structure leakage of the autonomously designed semiconductor device can be avoided.

Description

Design method of PCell layout

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a design method of a PCell layout.

Background

The PDK (Process Design Kit) is a communication bridge between the chip production company (foundation), the EDA (Electronic Design automation) company and the chip Design company. With the continuous development of integrated circuit technology, new materials, new technologies and new manufacturing processes are continuously developed, so that new semiconductor devices are developed like spring shoots in the rainy season. When a chip design company needs to adopt a chip production factory to produce a novel semiconductor device, firstly, a set of PDK is needed, and the PDK is a base stone for designing a chip by the design company and is also a key factor for the success and failure of a slide.

The content of the PDK comprises: the Device Model (Device Model, simulation File), symbol and View (Symbols & View), component Description Format (CDF), callback function (attribute Description File of Device), parameterization unit (Pcell, parameterized Cell) are written by the SKILL language, and the corresponding Layout passes Design Rule Check (DRC) and Layout and circuit diagram LVS verification, so that designers can conveniently design Layout (Layout) driven by schematic diagram, technical File (Technology File), physical verification Rule (PV Rule), and the like. The parameters in the parameterization unit are CDF parameters, the combination of the CDF parameters can realize all functions customized by a user, and the CDF parameters are the core part of the PDK and determine the application and quality of the PDK.

With the continuous evolution of the PDK development process, the design rule becomes more and more complex, and much effort and cost are required to develop the PDK. However, the designer needs to provide the PDK to the customer and then confirm or modify the CDF parameters in the PDK by the customer, however, the Pcell layout in the PDK may expose the structure of the new semiconductor device, and the designer does not want the customer to see the real Pcell layout when providing the PDK to the customer for protection of the autonomous design scheme of the new semiconductor device, so that improvement is needed.

Disclosure of Invention

The invention aims to provide a design method of a PCell layout, which is used for preventing the PCell layout from exposing a specific structure of a device.

In order to achieve the above object, the present invention provides a method for designing a PCell layout, including:

obtaining a PCell layout of a target device, wherein the PCell layout is provided with a plurality of process layers, and each process layer is provided with a plurality of graphs; and (c) a second step of,

and transforming at least one process layer and/or at least one graph to distort the PCell layout.

Optionally, the sizes and positions of the frame and the pins are kept unchanged after the PCell layout is distorted, and each of the patterns is located in the frame.

Optionally, the maximum width of the frame is 1 μm to 500 μm, and the maximum width of the transformed pattern is less than 5nm.

Optionally, when the process layer is transformed, all the patterns in the process layer are mapped to a newly added process layer.

Optionally, when the process layers are transformed, all the patterns in at least two of the process layers are exchanged.

Optionally, when at least two transformed graphs are provided, the graphs are transformed one by one.

Optionally, when the graph is transformed, the graph is transformed by using a reference point as an origin and using a corresponding transformation rule.

Optionally, the transformation rules corresponding to each graph are the same or different.

Optionally, the transformation rule includes at least one of shrinking, rotating and cutting the graph.

Optionally, the graphs are all rectangular, when the graphs are transformed, a corresponding coordinate transformation formula is obtained based on the transformation rule, coordinates of four distortion points are obtained through calculation based on the coordinates of the four vertexes of the graphs and the coordinate transformation formula, and the four distortion points are enclosed and combined into the transformed graphs.

In the design method of the PCell layout, firstly, the PCell layout of a target device is obtained, the PCell layout is provided with a plurality of process layers, each process layer is provided with a plurality of graphs, and then at least one process layer and/or at least one graph are transformed so as to distort the PCell layout. The distorted PCell layout is provided for a customer, the customer can use the PCell layout corresponding to the default CDF parameter or modify the CDF parameter to update the PCell layout, and meanwhile, the structure leakage of the autonomously designed semiconductor device can be avoided.

Drawings

Fig. 1 is a flowchart of a method for designing a PCell layout according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a PCell layout according to an embodiment of the present invention;

fig. 3a to 3c are schematic diagrams of each process layer of the PCell layout in fig. 2;

FIGS. 4a to 4c are schematic diagrams illustrating the three process layers in FIGS. 3a to 3c after all the graphics have been exchanged;

fig. 5a to 5c are schematic diagrams illustrating that all the patterns in the two process layers in fig. 3a to 3c are mapped to an additional process layer;

fig. 6a is a schematic diagram of the PCell layout after reducing all the patterns provided by the embodiment of the present invention;

fig. 6b is a schematic diagram of all the patterns of the PCell layout reduced and rotated according to the embodiment of the present invention;

fig. 6c is a schematic diagram of the PCell layout after all the patterns are reduced, miscut and rotated according to the embodiment of the present invention;

FIG. 7a is a schematic diagram showing the coordinates of four vertices of the graph a in FIG. 2;

FIG. 7b is a schematic diagram showing coordinates of four distortion points of the graph a in FIG. 6 c;

wherein the reference numbers are:

100-frame; AA. POLY, CT, M, mark-process layer; a. b1, b2, c1, c2, c3, c 4-graph; o-a reference point; a1, A2, A3, A4-vertex; a1', A2', A3', A4' -distortion points; theta-angle of rotation.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 is a flowchart of a method for designing a PCell layout provided in this embodiment. As shown in fig. 1, the method for designing the PCell layout includes:

step S100: acquiring a PCell layout of a target device, wherein the PCell layout is provided with a plurality of process layers, and each process layer is provided with a plurality of graphs; and the number of the first and second groups,

step S200: and transforming at least one process layer and/or at least one graph to distort the PCell layout.

Specifically, step S100 is performed first to provide the target device, which may be a new semiconductor device designed by a designer, different from the existing semiconductor device. And acquiring the PCell layout of the target device. At this time, the PCell layout is a real PCell layout designed by designers.

Furthermore, the PCell layout has a plurality of process layers (layers). It should be understood that the process layers may have various types, such as well layers, active region layers, polysilicon gate layers, via layers, metal layers, text label layers, and pad layers, and each type of the process layers may have one or at least two process layers. The process layers are stacked in sequence, each process layer is provided with a plurality of graphs, and each graph represents the layout mode of structures (such as a source region, a drain region, a grid electrode, a through hole, a bonding pad and the like) in the device. The figures are generally rectangular in shape.

Fig. 2 is a schematic structural diagram of a PCell layout provided in this embodiment, and fig. 3a to fig. 3c are schematic diagrams of each process layer of the PCell layout in fig. 2. As shown in fig. 2 and fig. 3a to 3c, the PCell layout in this embodiment has 3 process layers, which are a process layer AA, a process layer POLY, and a process layer CT, and the process layer AA, the process layer POLY, and the process layer CT are sequentially stacked from bottom to top. Wherein, the process image layer AA is provided with only one figure, namely a figure a; the process pattern layer POLY is provided with two patterns, namely a pattern b1 and a pattern b2; the process image layer CT has 4 graphs, namely graphs c1, c2, c3 and c4. As can be seen from fig. 2, the figures a, b1, b2, c1, c2, c3, c4 are all rectangular.

It should be understood that the PCell layout provided in this embodiment is only an example, and the PCell layout is not limited to have only 3 process layers, and may have less than 3 process layers or more than 3 process layers; each process layer is not limited to have 1, 2 or 4 patterns, and other numbers of patterns can be provided; moreover, the position and distribution mode of the pattern in each process layer are not limited thereto, and are not explained one by one here.

Referring to fig. 2, the PCell layout has a frame 100, where the frame 100 is a graph boundary of the PCell layout and is used to define an area of the PCell layout, and all the graphs (the graphs a, b1, b2, c1, c2, c3, and c 4) of the PCell layout are located in the frame. The PCell layout also has PINs (PINs) leading to the border 100 for connection with input/output signal lines of an external circuit.

In the embodiment, the maximum width of the frame is 1 μm to 500 μm, but the invention should not be limited thereto.

Next, step S200 is executed to transform at least one process layer and/or at least one graph, so as to distort the PCell layout. That is, the present invention can separately transform at least one process layer, so that at least one process layer is distorted, thereby causing distortion of the PCell layout; or at least one graph can be transformed independently, so that at least one graph is distorted, and further the PCell layout is distorted; and simultaneously transforming at least one process layer and at least one graph to simultaneously distort the at least one process layer and the at least one graph, thereby causing the distortion of the PCell layout. The distorted PCell layout is provided for a customer, the customer can use the PCell layout corresponding to the default CDF parameters or modify the CDF parameters to update the PCell layout, and meanwhile, the structure leakage of the semiconductor device which is designed autonomously can be avoided.

Further, when the process layers are transformed, all the patterns in at least two of the process layers may be exchanged. Fig. 4a to fig. 4c are schematic diagrams of all the graphics in the three process layers in fig. 3a to fig. 3c after being exchanged. As shown in fig. 4a to 4c, first, all the patterns in the process layer AA are exchanged with all the patterns in the process layer POLY; and then exchanging all the graphs in the process layer POLY with all the graphs in the process layer CT. After the exchange, the process layer AA includes the patterns b1 and b2, the process layer POLY includes the patterns c1, c2, c3, and c4, and the process layer CT includes the pattern a. In this way, the patterns in the process layer AA, the process layer POLY and the process layer CT are all changed, and the PCell layout is distorted.

It should be understood that, in this embodiment, all the patterns in the process layer AA, the process layer POLY, and the process layer CT are not limited to be exchanged, and all the patterns in any two of the process layer AA, the process layer POLY, and the process layer CT may also be exchanged, for example: only exchanging all the graphs in the process image layer AA and the process image layer POLY; or only exchanging all the graphs in the process layer POLY and the process layer CT.

Further, when the process layer is transformed, all the patterns in the process layer may be mapped to a newly added process layer. Fig. 5a to 5c are schematic diagrams illustrating mapping of all the patterns in the two process layers in fig. 3a to 3c to the newly added process layer. As shown in fig. 5a to 5c, a process layer M and a process layer Mark are newly created, then all the patterns in the process layer AA are mapped into the process layer M, all the patterns in the process layer POLY are mapped into the process layer Mark, and the process layer AA and the process layer POLY are deleted. At this time, the PCell layout includes the process layer M, the process layer Mark, and the process layer CT, and the process layer M includes the pattern a, the process layer Mark includes the patterns b1 and b2, and the process layer CT includes the patterns c1, c2, c3, and c4. In this way, the process layer AA and the process layer POLY are changed, and the PCell layout is distorted.

It should be understood that, in this embodiment, not only all the graphics in the process layer AA and the process layer POLY are mapped into two newly added process layers, but also all the graphics in the process layer AA and the process layer CT are mapped into two newly added process layers; or mapping all the graphs in the process layer POLY and the process layer CT to the two newly added process layers respectively; or mapping all the graphs in any one of the process layer AA, the process layer POLY or the process layer CT to a newly added process layer, or mapping all the graphs in the process layer AA, the process layer POLY and the process layer CT to three newly added process layers.

In this embodiment, when the graph is transformed, the graph may be transformed by using a reference point O as an origin and using a corresponding transformation rule, and when the graph is transformed, the coordinates of the reference point are always unchanged. Referring to fig. 2, in the embodiment, the reference point O is a lower left vertex of the graph a, but it should not be limited thereto, and the reference point O may be other positions.

Further, the transformation rule may be at least one of a reduction, a rotation, and an error cut of the graphic. That is, when the graphics are converted, only the graphics may be reduced, rotated, or cut by mistake, or at least two of the graphics may be reduced, rotated, or cut by mistake. When the graphics are transformed, the transformation rules corresponding to the graphics may be the same or different. Next, a description will be given by taking as an example that all the patterns of the PCell layout are transformed and the transformation rules corresponding to each pattern are the same.

Fig. 6a is a schematic diagram of the PCell layout reduced by all the patterns provided in this embodiment. As shown in fig. 6a, on the basis of fig. 2, the graphs a, b1, b2, c1, c2, c3, c4 are reduced by a predetermined multiple with the reference point O as the origin. In this way, the dimensions of the patterns a, b1, b2, c1, c2, c3, c4 are all reduced, and the PCell layout is distorted.

Fig. 6b is a schematic diagram of the PCell layout provided in this embodiment after reducing and rotating all the patterns. As shown in fig. 6b, on the basis of fig. 2, the graphs a, b1, b2, c1, c2, c3, c4 are reduced by a predetermined multiple with the reference point O as the origin; and then, rotating the graphs a, b1, b2, c1, c2, c3 and c4 by a preset angle by taking the reference point O as an origin. In this way, the dimensions of the graphs a, b1, b2, c1, c2, c3 and c4 are all reduced, and the graphs a, b1, b2, c1, c2, c3 and c4 are rotated by a certain angle, so that the PCell layout is distorted.

Fig. 6c is a schematic diagram of the PCell layout provided in this embodiment after reducing, miscut, and rotating all the patterns. As shown in fig. 6c, on the basis of fig. 2, the graphs a, b1, b2, c1, c2, c3, c4 are reduced by a predetermined multiple with the reference point O as the origin; then, taking the reference point O as an origin, and cutting the graphs a, b1, b2, c1, c2, c3 and c4 in a staggered manner along the transverse direction; then, the graphs a, b1, b2, c1, c2, c3, c4 are rotated by a predetermined angle with the reference point O as an origin. As a result, the dimensions of the patterns a, b1, b2, c1, c2, c3, c4 are all reduced, while the patterns a, b1, b2, c1, c2, c3, c4 are distorted into a parallelogram, and the patterns a, b1, b2, c1, c2, c3, c4 are also rotated by a certain angle, so that the PCell layout is distorted.

It should be understood that the transformation performed on all the graphs of the PCell layout provided in fig. 6a to 6c is only an example, and in practical applications, other forms of transformation may also be performed on all the graphs of the PCell layout, and are not illustrated herein.

Further, in fig. 6a to 6c, after the graphs a, b1, b2, c1, c2, c3, and c4 are reduced by a predetermined multiple, the frame 100 remains unchanged after the PCell layout is distorted, that is, the area of the PCell layout is equal to that of the real PCell layout, so as to avoid that the distorted PCell layout cannot reflect the real size of the device, which causes a problem in chip design (occupies the position of other devices). It should be understood that in some situations where the size requirement is not high, the border 100 may become larger or smaller after the PCell layout distortion.

Further, after the patterns a, b1, b2, c1, c2, c3, and c4 are reduced, the maximum widths of the patterns a, b1, b2, c1, c2, c3, and c4 are all less than 5nm, and the widths of the patterns a, b1, b2, c1, c2, c3, and c4 are integer multiples of the width of the minimum lattice point of the PCell layout. Since the size of the frame 100 is on the micrometer scale and the reduced size of the patterns a, b1, b2, c1, c2, c3, c4 is on the nanometer scale, even if the deformed patterns a, b1, b2, c1, c2, c3, c4 are enlarged, it is difficult to clearly see the real layout of the patterns a, b1, b2, c1, c2, c3, c4.

Further, when the graphics a, b1, b2, c1, c2, c3, and c4 are transformed, the graphics a, b1, b2, c1, c2, c3, and c4 may be transformed one by one with the reference point O as an origin, that is, when there are at least two graphics to be transformed, the graphics are not transformed synchronously, but the graphics are transformed one by one. In the case of transforming the graphs a, b1, b2, c1, c2, c3, c4 by taking the transformation example in fig. 6b, the graph a is reduced by a predetermined multiple by taking the reference point O as an origin on the basis of fig. 2; and then, rotating the graph a by a preset angle by taking the reference point O as an origin. Next, taking the reference point O as an origin, reducing the graph b1 by a predetermined multiple; and then, rotating the graph b1 by a preset angle by taking the reference point O as an origin. Next, with the reference point O as an origin, the graph b2 is reduced by a predetermined multiple; and then, rotating the graph b2 by a preset angle by taking the reference point O as an origin. 8230and finally, reducing the graph c4 by a preset multiple by taking the reference point O as an origin; and then, rotating the graph c4 by a preset angle by taking the reference point O as an origin.

Furthermore, since the graphs are all rectangular, when the graphs are transformed, a corresponding coordinate transformation formula can be obtained based on the transformation rule, coordinates of four distortion points are obtained by calculation based on the coordinates of four vertexes of the graphs and the coordinate transformation formula, and the four distortion points are enclosed and synthesized into the transformed graphs. In this way, the transformation of each graph only needs to calculate 4 coordinates, and the calculation is simpler. Fig. 7a is a schematic diagram showing coordinates of four vertices of the graph a in fig. 2, and fig. 7b is a schematic diagram showing coordinates of four vertices of the graph a in fig. 6 c. As shown in fig. 7a and 7b, taking the example of transforming the graph a in fig. 2 to the graph a in fig. 6c, assuming that the length of the graph a in fig. 2 is L and the width is W, the coordinates of the four vertices of the graph a in fig. 2 are A1 (0, W), A2 (L, W), A3 (L, 0), A4 (0, 0), respectively; a corresponding coordinate transformation formula is obtained based on a transformation rule of the graph a in fig. 2 to the graph a in fig. 6c, and then coordinates of four distortion points A1 '(x 1', y1 '), A2' (x 2', y 2'), A3 '(x 3', y3 '), A4' (0, 0) are calculated based on the coordinates A1 (0, W), A2 (L, W), A3 (L, 0), A4 (0, 0) of the four vertices of the graph a and the coordinate transformation formula in the following manner:

x1’＝W*fy*sinθ，y1’＝W*fy*cosθ；x2＝W*fy*sinθ+L*fx*cosθ，y2’＝W*fy*cosθ-L*fx*sinθ；x3’＝L*fx*cosθ，y3’＝-L*fx*sinθ。

where fx is a reduction factor in the X direction, fy is a reduction factor in the Y direction, and θ is a rotation angle.

The graph a in fig. 6c can be obtained by enclosing the four distortion points A1 '(x 1', y1 '), A2' (x 2', y 2'), A3 '(x 3', y3 '), and A4' (0, 0).

It should be noted that, since the lower left vertex A4 of the graph a is the reference point O, the coordinate of the reference point O does not change after the transformation, and thus the coordinate of A4' is still (0, 0).

It can be understood that after the distorted PCell layout is provided to a customer, if the customer does not modify CDF parameters, corresponding inverse transformation may be performed on the distorted PCell layout, so as to restore a real PCell layout; even if the customer modifies the CDF parameters, the distorted PCell layout can be correspondingly transformed, and at the moment, the distorted PCell layout can be correspondingly inversely transformed and updated.

In summary, in the method for designing a PCell layout provided in the embodiments of the present invention, a PCell layout of a target device is first obtained, where the PCell layout has a plurality of process layers, and each process layer has a plurality of patterns, and then at least one process layer and/or at least one pattern is transformed, so as to distort the PCell layout. The distorted PCell layout is provided for a customer, the customer can use the PCell layout corresponding to the default CDF parameter or modify the CDF parameter to update the PCell layout, and meanwhile, the structure leakage of the autonomously designed semiconductor device can be avoided.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the description of the method part.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art that many changes and modifications can be made, or equivalents employed, to the presently disclosed embodiments without departing from the intended scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention will still fall within the protection scope of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (10)

1. A design method of a PCell layout is characterized by comprising the following steps:

acquiring a PCell layout of a target device, wherein the PCell layout is provided with a plurality of process layers, and each process layer is provided with a plurality of graphs; and the number of the first and second groups,

and transforming at least one process layer and/or at least one graph to distort the PCell layout.

2. The method for designing the PCell layout of claim 1, wherein the dimensions and locations of the borders and the pins remain unchanged after the PCell layout is distorted, and each of the patterns is located within the borders.

3. The method for designing the PCell layout of claim 2, wherein the maximum width of the border is 1 μm to 500 μm, and the maximum width of the transformed pattern is less than 5nm.

4. The method for designing the PCell layout of any of claims 1 to 3, wherein, when transforming the process layer, all the patterns in the process layer are mapped to a newly added process layer.

5. The method for designing the PCell layout of any of claims 1 to 3, wherein all the patterns in at least two of the process layers are exchanged when transforming the process layers.

6. The method for designing a PCell layout of any of claims 1 to 3, wherein when there are at least two transformed patterns, the patterns are transformed one by one.

7. The method for designing the PCell layout of any one of claims 1 to 3, wherein the graphics are transformed with a corresponding transformation rule with a reference point as an origin when transforming the graphics.

8. The method for designing the PCell layout of claim 7, wherein the transformation rules corresponding to each of the patterns are the same or different.

9. The method of designing a PCell layout of claim 7, wherein the transformation rules include at least one of shrinking, rotating and miscutting the pattern.

10. The method for designing the PCell layout of claim 7, wherein the figures are all rectangular, and when the figures are transformed, a corresponding coordinate transformation formula is obtained based on the transformation rule, coordinates of four distortion points are obtained by calculation based on coordinates of four vertices of the figures and the coordinate transformation formula, and the four distortion points are enclosed to form the transformed figures.

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