CN115292238A - FPGA-based method for realizing phase alignment of inter-chip parallel interface - Google Patents

Abstract

The embodiment of the invention discloses a method for realizing phase alignment of an inter-chip parallel interface based on an FPGA. The method comprises the following steps: constructing a circuit with adjustable real-time delay for each signal of the parallel interface by utilizing a programmable logic unit of the FPGA to obtain a delay chain; and compensating the routing delay deviation among the signals by adjusting the delay chain. The method of the embodiment of the invention can reduce the circuit design difficulty of the parallel interface of the FPGA and other chips; the method has the advantages of improving the width of an effective sampling window, saving PLL (phase locked loop) resources, increasing the flexibility of design, realizing more parallel interfaces, increasing the flexibility of FPGA (field programmable gate array) type selection, and realizing adjustable delay of each signal without depending on the FPGA of a specific manufacturer.

Description

FPGA-based method for realizing phase alignment of inter-chip parallel interface

Technical Field

The invention relates to a signal phase alignment method of an FPGA (field programmable gate array) parallel interface, in particular to an implementation method of phase alignment of an inter-chip parallel interface based on an FPGA.

Background

In many interface circuit designs, an application scenario in which an FPGA (Field Programmable Gate Array) and other chips are interconnected through parallel interfaces to realize data transmission is involved, and most of the parallel interfaces are synchronous, that is, one of the signals is a clock signal. The transmitting end outputs the signals from the port according to a certain phase relation, and the receiving end synchronously samples other signals by using a clock signal in the interface, so that parallel data transmission is realized. For example, a GMII (Gigabit Media Independent interface) interface between an FPGA and a PHY (Physical layer) chip of an ethernet network has a group of parallel output interfaces with 11 bits of bit width at a transmitting end for the FPGA, which includes a clock signal, a data valid indication signal, a data error indication signal, and eight data signals, and the clock signal is used to sample other signals at a receiving end of the PHY chip.

In order to ensure that each beat of the clock signal can correctly sample other signals at the receiving end, the phase relationship between the other signals and the clock edge is required to be kept within a certain range, and the range is generally called an effective sampling window. Since the lengths of the wires of the signals in the parallel interface are not consistent in the chip, and the lengths of the wires on the PCB are also not consistent, the transmission delays of the signals which are superposed when the signals reach the receiving end are not consistent, so that the phase relationship between the signals is deviated, as shown in fig. 1. These deviations will affect the width of the effective sampling window, and with the increase of the data bit width and the increase of the data transmission frequency, the effect will be more and more serious, even resulting in the disappearance of the effective sampling window, so that the receiving end cannot correctly receive the data. In addition, these deviations may cause the clock edge to be outside the valid sampling window, so that the receiving end cannot correctly receive the data.

Therefore, how to compensate the transmission delays enables the signals to be aligned in phase at the receiving end, thereby ensuring that the clock edge falls in an effective sampling window and ensuring that the parallel interface with large bit width and high speed can correctly realize the important technical guarantee of data transmission.

The existing general technical scheme is that the phase of a clock edge of a sending end is adjusted at the sending end of an FPGA through a PLL (phase locked loop), so that the clock edge is positioned in an effective sampling window of other signals when reaching the receiving end of an opposite end chip, and the receiving end of the opposite end chip is ensured to realize correct sampling of data; the same implementation scheme is adopted at the receiving end of the FPGA, the phase of the clock edge of the receiving end is adjusted through the PLL, and parallel data sent by an opposite end chip are correctly sampled at the receiving port of the FPGA. However, the scheme only adjusts the phase of the clock edge, so that the clock edge is positioned in the effective sampling window of other signals, and the phases of the other signals are not aligned, that is, the scheme does not have the capability of adjusting the width of the effective sampling window; PLL resources are consumed for both transmission and reception, while PLL resources for FPGAs are very limited. When a plurality of high-speed parallel interfaces are realized on the same FPGA, PLL resources are not enough, an FPGA with a larger model is required to be replaced, or a plurality of FPGAs are selected to realize the design of the interface, the design cost and the design complexity are increased, and the scheme has two preconditions: one is that when other parallel signals reach a receiving end, an effective sampling window still exists; another is that the PLL's range of phase adjustments to the clock can cover the phase offset of the clock edge and the valid sampling window. With the increase of bit width and the increase of speed of the parallel interface, both of the above two conditions may not be satisfied, which makes the solution unfeasible.

In another scheme, a hard digital delay circuit, a branch output delay circuit and an input delay circuit are embedded in a pin of the FPGA. The sending direction can adjust the delay time of each signal in the parallel output interface passing through the output delay circuit in the FPGA on line, and the delay time is used for compensating transmission delay deviation caused by internal routing and PCB routing among the signals, so that the phases of the signals reaching an opposite-end chip are aligned, the maximization of an effective sampling window is maintained, a clock edge is in the middle of the sampling window as much as possible, and the receiving end is ensured to sample data correctly; similarly, the delay time of each signal of the parallel input interface passing through the input delay circuit in the FPGA can be adjusted on line in the receiving direction of the FPGA to compensate delay deviation among the signals caused by internal wiring and PCB wiring, so that the phases of the signals reaching the sampling register in the FPGA are aligned, and correct data sampling is realized. However, this is not a general solution, because the structures of FPGAs developed by different FPGA manufacturers are different, and the FPGAs of some manufacturers have hard digital delay circuits designed on the pins, which can implement the above solution, such as the FPGA of saint; some manufacturers 'FPGAs do not have such hard digital delay circuits on the pins, and cannot use the above scheme, such as intel's FPGA. Because the digital delay circuit is hardened in the pin unit of the FPGA, the delay adjustable range of the digital delay circuit is solidified after the model design is completed, generally 2 to 3ns, the FPGAs of different models have certain difference, at most 3 hard delay circuit cascades are supported, the flexibility and the expandability are not high, and the cascade is that the delay circuit of a plurality of pins is occupied by one pin, the delay adjustable range of other pins is sacrificed to increase the signal delay adjustable range of a certain pin, and the problem of resource shortage can be faced when a plurality of parallel interfaces are provided.

Therefore, it is necessary to design a new method to reduce the circuit design difficulty of the parallel interface between the FPGA and other chips; the method has the advantages of improving the width of an effective sampling window, saving PLL (phase locked loop) resources, increasing the flexibility of design, realizing more parallel interfaces, increasing the flexibility of FPGA (field programmable gate array) type selection, and realizing adjustable delay of each signal without depending on the FPGA of a specific manufacturer.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a method for realizing phase alignment of an inter-chip parallel interface based on an FPGA.

In order to realize the purpose, the invention adopts the following technical scheme: the method for realizing the phase alignment of the parallel interfaces among the chips based on the FPGA comprises the following steps:

constructing a circuit with adjustable real-time delay for each signal of the parallel interface by utilizing a programmable logic unit of the FPGA to obtain a delay chain;

and compensating the trace delay deviation among the signals by adjusting the delay chain.

The further technical scheme is as follows: the method for constructing a circuit with real-time adjustable delay for each signal of a parallel interface by using the programmable logic unit of the FPGA to obtain a delay chain comprises the following steps:

describing an adder with multiple bit widths through a hardware description language to obtain an integrated addition circuit;

and mapping the addition circuit to a programmable logic resource of the FPGA to obtain a delay chain.

The further technical scheme is as follows: the delay chain is a delay circuit cascaded by adders and carry chains in the LAB.

The further technical scheme is as follows: the compensating for the trace delay deviation between the signals by adjusting the delay chain includes:

and the signals are transmitted from the adder at the upper stage to the adder at the lower stage in the delay chain so as to compensate the routing delay deviation among the signals.

The further technical scheme is as follows: the signal is transmitted from the adder at the previous stage to the adder at the next stage in the delay chain to compensate the trace delay deviation among the signals, and the method comprises the following steps:

the signals are directly transmitted from the carry chain output end of the last-stage adder to the carry chain input end of the next-stage adder, or transmitted from the output end of the last-stage adder to one input end of the next-stage adder through the internal interconnection line of the FPGA, and the routing delay deviation among the signals is compensated through the selection of two paths.

The further technical scheme is as follows: the mapping the adder circuit to the programmable logic resource of the FPGA to obtain a delay chain includes:

and inserting the delay chain between a register and a pin corresponding to each signal in a parallel interface of the FPGA.

The further technical scheme is as follows: the delay chain adjusts the adjustable range by increasing or decreasing the stage number of the delay chain.

Compared with the prior art, the invention has the beneficial effects that: the invention constructs a circuit with real-time adjustable time delay for each signal of the parallel interface by utilizing the programmable logic unit of the FPGA to obtain a time delay chain, and adjusts the time delay chain to compensate the routing delay deviation between the signals so as to reduce the circuit design difficulty of the parallel interface of the FPGA and other chips; the method has the advantages of improving the width of an effective sampling window, saving PLL (phase locked loop) resources, increasing the flexibility of design, realizing more parallel interfaces, increasing the flexibility of FPGA (field programmable gate array) type selection, and realizing adjustable delay of each signal without depending on the FPGA of a specific manufacturer.

The invention is further described below with reference to the figures and the specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of routing of signals between chips in a parallel interface in the prior art;

fig. 2 is a schematic flowchart of a method for implementing phase alignment of an inter-chip parallel interface based on an FPGA according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a programmable logic unit of an Intel FPGA according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a delay circuit according to an embodiment of the present invention;

fig. 5 is a sub-flow diagram of a method for implementing phase alignment of an inter-chip parallel interface based on an FPGA according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Referring to fig. 2, fig. 2 is a schematic flowchart of a method for implementing phase alignment of an inter-chip parallel interface based on an FPGA according to an embodiment of the present invention. As shown in fig. 2, the method includes the following steps S110 to S150.

S110, constructing a circuit with adjustable real-time delay for each signal of the parallel interface by using a programmable logic unit of the FPGA to obtain a delay chain.

In this embodiment, the delay chain refers to a circuit configured for signal phase alignment by a programmable logic unit.

The delay chain is constructed through the programmable logic unit, although the FPGA developed by each FPGA manufacturer has difference in the structural details of the programmable logic unit, the whole function is similar, for example, LAB of Intel FPGA and Slice of Sailing FPGA can be used for constructing the delay chain, the delay chain is used for replacing PLL in the first technical scheme, the online phase modulation function of the clock edge can be realized, and PLL resources are saved; the delay chain is used for replacing a hard digital delay unit in the prior art, and the transmission delay of all signals can be adjusted on line, so that the transmission delay of each signal can be adjusted without depending on an FPGA of a specific manufacturer, and the width of a sampling window is maximized. The adjustable range of the delay chain can be flexibly adjusted by increasing or reducing the number of stages of the delay chain, in addition, the delay chain occupies a programmable logic unit of the FPGA, and the most main resource of the FPGA is the programmable logic unit, so that basically, the problem that the resource is insufficient when each signal is configured with the delay chain is not worried, and the method has great advantage when a plurality of parallel interfaces are realized.

In an embodiment, referring to fig. 5, the step S110 may include steps S111 to S112.

And S111, describing a multi-bit-width adder through a hardware description language to obtain the integrated adder circuit.

In this embodiment, the adder circuit is a circuit having a plurality of bit widths, in which the addition output of a lower bit is input as one addition of adjacent higher bits.

And S112, mapping the addition circuit to a programmable logic resource of the FPGA to obtain a delay chain.

In this embodiment, the delay chain is a delay circuit cascaded by adders and carry chains in the LAB. The delay chain adjusts the adjustable range by increasing or decreasing the stage number of the delay chain.

Specifically, the delay chain is inserted between a register and a pin corresponding to each signal in a parallel interface of the FPGA.

Specifically, the programmable logic unit of the FPGA, called LAB, is composed of 10 more basic ALM units, each ALM includes two 1-bit adders with carry, and carry chains of all the adders in the whole LAB are cascaded, as shown in fig. 3. The adders and carry chains in LABs are key to constructing delay chains.

One example of a delay circuit, i.e., delay chain, cascaded by adders and carry chains in LABs is described in Verilog HDL hardware description language, which corresponds to fig. 4.

wire[15:0]a；

wire[15:0]b；

wire[15:0]s；

assign b[0]＝1’b0；

assign a[15:1]＝s[14:0]；

assign s＝a+b。

And S120, compensating the routing delay deviation among the signals by adjusting the delay chain.

In this embodiment, the signal is transmitted from the adder at the previous stage to the adder at the next stage in the delay chain to compensate the trace delay deviation between the signals.

Specifically, the signals are directly transmitted from the carry chain output end of the adder at the previous stage to the carry chain input end of the adder at the next stage, or the signals are transmitted from the output end of the adder at the previous stage to one input end of the adder at the next stage through the internal interconnection line of the FPGA, and the routing delay deviation between the signals is compensated through the selection of two paths.

The signal is transmitted from the adder at the upper stage to the adder at the lower stage in the delay chain by two paths: one is a carry-in chain which is directly connected from the carry-in chain output end of the adder at the previous stage to the carry-in chain input end of the adder at the next stage; and the other is from the output end of the adder at the previous stage to one input end of the adder at the next stage through the internal interconnection line of the FPGA. By setting the value at the other input of the adder, it is possible to select which path the signal will take when it is transmitted at each stage in the delay chain.

Two signal transmission paths from the upper adder to the lower adder have different routing lengths and thus different delays. Assuming a constructed delay chain with n stages of adder cascades, the signal is transmitted in this delay chain with 2 ^n-1 The transmission delay can be set, the resolution of delay adjustment can be in picosecond level, and the delay range can be flexibly controlled by adjusting the stage number of the adder.

The delay chain can be flexibly inserted between the corresponding register and the pin of each signal in the parallel interface of the FPGA, and the delay of each signal on the whole transmission path is adjusted on line, so that the aim of phase alignment is fulfilled.

A delay chain, an output delay circuit and an input delay circuit are embedded between a register and a pin of the FPGA. The sending direction can adjust the delay time of each signal in the parallel output interface passing through the output delay circuit in the FPGA on line, and the delay time is used for compensating transmission delay deviation caused by internal routing and PCB routing among the signals, so that the phases of the signals reaching an opposite end chip are aligned, the maximization of an effective sampling window is maintained, a clock edge is in the middle of the sampling window as much as possible, and a receiving end can be ensured to sample data correctly; similarly, the delay time of each signal of the parallel input interface passing through the input delay chain in the FPGA can be adjusted on line in the receiving direction of the FPGA to compensate delay deviation among the signals caused by internal routing and PCB routing, so that the phases of the signals reaching the sampling register in the FPGA are aligned, and correct data sampling is realized. The problem that a receiving end cannot correctly sample data due to routing delay deviation of each signal in an application scene with large bit width and high speed of parallel interfaces of an FPGA and other chips is solved; the circuit design difficulty of parallel interfaces of the FPGA and other chips is reduced, and particularly in the application scene of large bit width and high speed; the width of an effective sampling window is improved, PLL (phase locked loop) resources are saved, the flexibility of design is improved, and more parallel interfaces are realized; the flexibility of the type selection of the FPGA is increased, and the delay of each signal can be adjusted without depending on the FPGA of a specific manufacturer.

The delay chain is constructed by using the logic resources of the FPGA to replace a PLL (phase locked loop) or a hard digital delay circuit, so that the signal delay of the parallel interface is adjustable, the phase alignment is realized, the signal phase alignment function of the parallel interface with large bit width and high speed of the FPGA can be realized by consuming very few logic resources, and the technical guarantee is provided for the parallel communication of the FPGA and other chips; because the transmission delay of each signal can be adjusted on line, the equal length requirement of the hardware PCB routing can be relaxed, and the difficulty of the PCB routing is simplified.

According to the method for realizing the phase alignment of the parallel interfaces between the chips based on the FPGA, a circuit with real-time adjustable delay is constructed for each signal of the parallel interface by utilizing the programmable logic unit of the FPGA to obtain a delay chain, and the delay chain is adjusted to compensate the routing delay deviation between the signals, so that the circuit design difficulty of the parallel interfaces between the FPGA and other chips is reduced; the method has the advantages of improving the width of an effective sampling window, saving PLL (phase locked loop) resources, increasing the flexibility of design, realizing more parallel interfaces, increasing the flexibility of type selection of the FPGA, and realizing the adjustable delay of each signal without depending on the FPGA of a specific manufacturer.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. The method for realizing the phase alignment of the parallel interfaces among the chips based on the FPGA is characterized by comprising the following steps:

constructing a circuit with adjustable real-time delay for each signal of the parallel interface by utilizing a programmable logic unit of the FPGA to obtain a delay chain;

and compensating the trace delay deviation among the signals by adjusting the delay chain.

2. The method for implementing phase alignment of an inter-chip parallel interface based on an FPGA according to claim 1, wherein the step of constructing a real-time adjustable delay circuit for each signal of the parallel interface by using a programmable logic unit of the FPGA to obtain a delay chain comprises:

describing an adder with multiple bit widths through a hardware description language to obtain an integrated addition circuit;

and mapping the addition circuit to a programmable logic resource of the FPGA to obtain a delay chain.

3. The method according to claim 2, wherein the delay chain is a delay circuit formed by cascading an adder and a carry chain in the LAB.

4. The method according to claim 1, wherein the compensating for the delay deviation of the routing between the signals by adjusting the delay chain includes:

and the signals are transmitted from the adder at the previous stage to the adder at the next stage in the delay chain so as to compensate the routing delay deviation among the signals.

5. The FPGA-based inter-chip parallel interface phase alignment implementation method of claim 4, wherein the signals are transmitted from an adder at a previous stage to an adder at a next stage in the delay chain to compensate for the trace delay deviation between the signals, and the implementation method comprises:

the signals are directly transmitted from the carry chain output end of the last-stage adder to the carry chain input end of the next-stage adder, or transmitted from the output end of the last-stage adder to one input end of the next-stage adder through the internal interconnection line of the FPGA, and the routing delay deviation among the signals is compensated through the selection of two paths.

6. The method for implementing phase alignment of an FPGA-based inter-chip parallel interface according to claim 1, wherein said mapping said adder circuit into programmable logic resources of an FPGA to obtain a delay chain comprises:

and inserting the delay chain between a register and a pin corresponding to each signal in a parallel interface of the FPGA.

7. The method for implementing phase alignment of an inter-chip parallel interface based on FPGA of claim 1, wherein the delay chain adjusts the adjustable range by increasing or decreasing the number of stages of the delay chain.

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