CN115276688A - Receiver and equalization method therefor, clock recovery circuit and method, device and medium - Google Patents

Abstract

The application discloses a receiver and an equalization method thereof, a clock recovery circuit and a method, equipment and a medium thereof, and belongs to the technical field of communication. The receiver comprises a sampling circuit, a TR circuit, an equalization circuit and an equalization coefficient control circuit. The sampling circuit is used for sampling the received signal under the control of the sampling clock signal to obtain a sampling signal; the TR circuit is used for phase discrimination of sampling signals output by the sampling circuit to obtain a phase difference, and adjusting sampling clock signals according to the phase difference; the equalization circuit is provided with N groups of equalization coefficients and is used for carrying out equalization processing on the sampling signal by adopting one group of equalization coefficients corresponding to the phase difference output by the TR circuit in the N groups of equalization coefficients. N is an integer greater than 1; the equalization coefficient control circuit is used for updating a group of equalization coefficients corresponding to the phase difference output by the TR circuit. The equalizing circuit of the receiver can be matched with the optimal response of different sampling positions, and the equalizing performance of the equalizing circuit is improved.

Description

Receiver and its equalization method, clock recovery circuit and method, device and medium

technical field

The present application relates to the technical field of communication, and in particular to a receiver and its equalization method, a clock recovery circuit and method, equipment and media.

Background technique

In a communication system, a transmitter sends a stream of data to a receiver. The receiver needs to extract the clock signal from the received data stream, and use the extracted clock signal to sample the received data, so as to recover the data sent by the transmitter.

Receivers typically include sampling circuits, clock recovery loops, and adaptive equalization circuits. The sampling circuit is used for sampling the received signal under the action of the sampling clock signal to obtain the sampling signal. The clock recovery loop is used to adjust the sampling clock signal based on the phase difference between the sampling signal and the sampling clock signal, so as to ensure the maximum signal-to-noise ratio of the data at the sampling moment. The adaptive equalization circuit dynamically adjusts its own equalization coefficients to adapt to channel changes over time. The self-adaptive equalization circuit is used for equalizing the sampling signal output by the sampling circuit by using the equalization coefficient to obtain an equalized signal.

When the phase difference between the data signal and the sampling clock signal is within a small range, a better equalization response can be obtained through the adaptive equalization circuit. However, during the working process of the communication system, the jitter will make the sampling position deviate. The sampling position deviation will cause serious performance regression of the adaptive equalization circuit and affect the communication quality.

Contents of the invention

Embodiments of the present application provide a receiver and its equalization method, a clock recovery circuit and method, equipment and media, which can improve the equalization performance of the equalization circuit.

In a first aspect, the present application provides a receiver, and the receiver includes a sampling circuit, a TR circuit, an equalization circuit and an equalization coefficient control circuit. Wherein, the sampling circuit is used to sample the received signal under the control of the sampling clock signal to obtain a sampling signal; the clock recovery circuit is used to perform phase discrimination on the sampling signal output by the sampling circuit to obtain the phase difference of the sampling signal, and according to The phase difference adjusts the sampling clock signal; the equalization circuit has N groups of equalization coefficients, and the equalization circuit is used to adopt a group of equalization coefficient pairs corresponding to the phase difference output by the clock recovery circuit among the N groups of equalization coefficients The sampling signal output by the sampling circuit is equalized, wherein N is an integer greater than 1; the equalization coefficient control circuit is used to update the phase difference between the N groups of equalization coefficients and the output of the clock recovery circuit The corresponding set of equalization coefficients.

In the embodiment of the present application, the update of the equalization coefficient of the equalization circuit is coupled with the sampling position (that is, the phase difference between the sampling signal and the sampling clock signal), and each time the equalization coefficient is updated, only the output of the clock recovery circuit is updated. A group of equalization coefficients corresponding to the phase difference enables independent updating of different groups of equalization coefficients. Since the change of the phase difference output by the clock recovery circuit is caused by jitter, and the phase change of the sampling clock signal brought about by the jitter is random, the clock recovery circuit updates a set of equalization coefficients each time is also random. And, after a period of time, each group of equalization coefficients has been updated and converged. Then, for the sampling signal output by the sampling circuit, a set of equalization coefficients corresponding to the phase difference output by the clock recovery circuit is also used for equalization processing, so that the equalization circuit can match the optimal response of different sampling positions based on different sets of equalization coefficients , improve the equalization performance of the equalization circuit, and then improve the communication quality.

In the embodiment of the present application, the equalization circuit has a plurality of taps, and the number of equalization coefficients included in each set of equalization coefficients is equal to or smaller than the number of taps included in the equalization circuit. And the taps corresponding to each group of equalization coefficients are the same.

In some examples, the phase change interval corresponding to the phase difference output by the clock recovery circuit includes N subintervals, and the N subintervals respectively correspond to a group of equalization coefficients in the N groups of equalization coefficients. The equalization coefficient control circuit includes an interval determination subcircuit and a control subcircuit. The interval determination subcircuit is used to determine the target subinterval to which the phase difference belongs from the N subintervals, and the control subcircuit is used to update a set of equalization coefficients corresponding to the target subinterval.

Optionally, the equalization coefficient control circuit further includes: a monitoring subcircuit and an interval determination subcircuit. The monitoring subcircuit is used to monitor the variation range of the phase difference output by the clock recovery circuit within a unit time length, obtain the phase variation interval, and divide the phase variation interval into the N subintervals. By dynamically monitoring the change range of the phase difference, the phase change range can be made more accurate, and the equalization effect can be further improved.

In some examples, the clock recovery circuit includes a clock recovery filter, a phase detector, a low pass filter, and a phase adjuster. The clock recovery filter is used to filter the sampling signal output by the sampling circuit to obtain a filtered sampling signal. The phase detector is used to perform phase detection on the filtered sampling signal to obtain a phase difference. The low-pass filter is used to filter the phase difference output by the phase detector to obtain an average value of the phase difference. The phase adjuster is used to adjust the phase of the sampling clock signal according to the mean value of the phase difference.

In some examples, an input of the equalization circuit is connected to an output of a clock recovery filter. The equalization circuit is used for performing equalization processing on the filtered sampling signal output by the clock recovery filter.

In some other examples, the input end of the equalization circuit is connected to the output end of the sampling circuit. The equalization circuit is used for equalizing the sampling signal output by the sampling circuit.

In some examples, the equalization coefficient control circuit further includes a feedforward filter for filtering the phase difference output by the clock recovery circuit, and outputting the filtered phase difference to the monitor sub-circuit.

Optionally, the N subintervals are equally partitioned intervals, or the N subintervals are non-equally partitioned intervals.

Optionally, the N subintervals respectively correspond to a UI field delay. The receiver also includes a phase detection gain estimation circuit. The phase detection gain estimation circuit is configured to determine the phase detection gain of the phase detector according to the phase delay corresponding to the phase difference output by the phase detector and the UI domain delay corresponding to the N subintervals. The clock recovery circuit is used to adjust the sampling clock signal according to the phase detection gain and the phase difference.

Exemplarily, the clock recovery circuit is configured to adjust the sampling clock signal according to the product of the phase detection gain and the phase difference.

Optionally, the receiver further includes an optimal phase tracking circuit. In a possible implementation manner, the optimal phase tracking circuit is configured to perform statistics on the transmission performance of the equalized signal for the N sub-intervals to obtain statistical results; and determine the optimal sampling phase deviation according to the statistical results. In another possible implementation manner, the receiver further includes an optimal phase tracking circuit. The optimal phase tracking circuit is used to perform statistics on the transmission performance of the filtered sampling signals output by the clock recovery filter for the N sub-intervals to obtain statistical results; and determine the optimal sampling phase deviation according to the statistical results . The clock recovery circuit is also used to adjust the phase of the sampling clock signal according to the optimal sampling phase deviation.

In a second aspect, an equalization method for a receiver is provided. The receiver includes a clock recovery circuit and an equalization circuit, and the equalization circuit has N groups of equalization coefficients, where N is an integer greater than 1. The method includes: the method includes: sampling the received signal under the control of a sampling clock signal to obtain a sampling signal; performing phase detection on the sampling signal through the clock recovery circuit to obtain a phase difference of the sampling signal; Through the equalization circuit, a group of equalization coefficients corresponding to the phase difference among the N groups of equalization coefficients is used to perform equalization processing on the sampled signal to obtain an equalized signal; among the N groups of equalization coefficients, the clock is updated. A group of equalization coefficients corresponding to the phase difference output by the restoration circuit.

Optionally, the phase change interval corresponding to the phase difference output by the clock recovery circuit includes N subintervals, and the N subintervals respectively correspond to a group of equalization coefficients in the N groups of equalization coefficients.

In some examples, the updating a group of equalization coefficients corresponding to the phase difference among the N groups of equalization coefficients includes: determining the target sub-interval to which the current phase difference belongs from the N sub-intervals; controlling the The equalization circuit updates a group of equalization coefficients corresponding to the target sub-interval.

In a possible implementation manner, the updating a group of equalization coefficients corresponding to the phase difference among the N groups of equalization coefficients further includes: monitoring the phase difference output by the clock recovery circuit within a unit time length range of change to obtain the phase change interval; and divide the phase change interval into the N subintervals.

Optionally, the N subintervals are equally partitioned intervals, or the N subintervals are non-equally partitioned intervals.

Optionally, the equalization method further includes: determining the phase detection gain according to the phase delay corresponding to the phase difference and the UI domain delay corresponding to the N subintervals; according to the phase detection gain and the phase difference pair The sampling clock signal is adjusted.

Optionally, the equalization method further includes: performing statistics on the transmission performance of the equalized signal output by the equalization circuit for the N sub-intervals to obtain statistical results; determining the best sampling phase deviation according to the statistical results; according to the The optimal sampling phase offset adjusts the phase of the sampling clock signal.

In a third aspect, a clock recovery circuit is provided, and the clock recovery circuit includes: a sampler, an adaptive equalizer, a phase detector, a low-pass filter, a phase adjuster and a control circuit. The sampler is used to sample the received signal under the control of the sampling clock signal to obtain a sampled signal; the adaptive equalizer has a plurality of equalization coefficients, and the adaptive equalizer is used to perform equalization processing on the sampled signal by using the plurality of equalization coefficients , to obtain an equalized signal; a phase detector is used to phase detect the equalized signal output by the adaptive equalizer to obtain a phase difference of the equalized signal; a low-pass filter is used to filter the phase difference; a phase adjuster is used to The phase of the sampling clock signal is adjusted according to the mean value of the phase difference; the control circuit is used to control the update of the equalization coefficient of the adaptive equalizer according to the phase difference output by the phase detector.

In some examples, the control circuit is configured to control updating of equalization coefficients of the adaptive equalizer in response to determining that the phase difference belongs to a target phase interval; or, the control circuit is configured to respond to determining that the phase difference If it does not belong to the target phase interval, control the equalization coefficient of the adaptive equalizer to remain unchanged.

Optionally, the clock recovery circuit further includes a limiter and an adder, the limiter is used to convert the equalized signal output by the adaptive equalizer into a binary signal, and the adder is used to determine the equalized signal and the error between the binary signal; the control circuit is used to update the equalization coefficient of the adaptive equalizer according to the error and the phase difference output by the phase detector.

Optionally, the clock recovery circuit further includes: an optimal phase tracking circuit, configured to perform statistics on transmission performance according to phase intervals to obtain statistical results; and determine the best sampling point according to the statistical results; The sampling phase offset adjusts the phase of the sampling clock signal.

In a fourth aspect, a method for clock recovery is provided, the method comprising: using an adaptive equalizer to perform equalization processing on the sampling signal output by the sampling circuit to obtain an equalized signal, and the adaptive equalizer has a plurality of equalization coefficients; The equalized signal output by the adaptive equalizer is phase-detected to obtain a phase difference of the equalized signal, and the sampling signal is output by the sampling circuit under the control of the sampling clock signal; according to the phase difference, controlling the update of the equalization coefficient of the adaptive equalizer; and adjusting the phase of the sampling clock signal according to the phase difference.

In some examples, the controlling the update of the equalization coefficient of the adaptive equalizer according to the phase difference includes: controlling the equalization coefficient of the adaptive equalizer in response to determining that the phase difference belongs to a target phase interval updating; or, in response to determining that the phase difference does not belong to the target phase interval, controlling the equalization coefficient of the adaptive equalizer to remain unchanged.

In a fifth aspect, there is provided a computer device, the computer device includes a processor and a memory, wherein: the memory stores computer instructions, and the processor executes the computer instructions, so as to realize the first aspect or the fourth aspect and its possible implementation manners method.

In a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer instructions. When the computer instructions in the computer-readable storage medium are executed by a computer device, the computer device executes the first aspect or the fourth aspect. Aspects and their possible ways of implementing them.

In a seventh aspect, there is provided a computer program product containing instructions, which, when running on a computer device, causes the computer device to execute the method of the first aspect or the fourth aspect and possible implementations thereof.

Description of drawings

FIG. 1 is a schematic structural diagram of a receiver provided in an exemplary embodiment of the present application;

Fig. 2 is a schematic diagram of the relationship between four sets of equalization coefficients provided by an exemplary embodiment of the present application;

FIG. 3 is a schematic structural diagram of a receiver provided in an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of determining a target subinterval according to a phase difference output by a filter in an exemplary embodiment of the present application;

FIG. 5 is a comparison diagram of a BER-based bathtub curve provided by an exemplary embodiment of the present application and related technologies;

FIG. 6 is a comparison diagram of the jitter tolerance test results of the receiver provided by the related technology and an exemplary embodiment of the present application;

FIG. 7 is a comparison diagram of bit error rates under different jitters between a receiver provided by an exemplary embodiment of the present application and a receiver in related technologies;

FIG. 8 is a schematic diagram of a phase detection gain curve obtained through simulation provided by an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of an SNR-based bathtub curve provided by an exemplary embodiment of the present application;

Fig. 10 is a statistical schematic diagram of the number of occurrences of phase differences corresponding to different phase sub-intervals in an exemplary embodiment of the present application;

Fig. 11 is a schematic structural diagram of another receiver provided in an exemplary embodiment of the present application;

FIG. 12 is a schematic flowchart of a receiver equalization method provided by an exemplary embodiment of the present application;

Fig. 13 is a schematic structural diagram of a clock recovery circuit provided by an exemplary embodiment of the present application;

FIG. 14 is a schematic diagram of outputting an enable signal according to a phase difference output by a filter in a clock recovery circuit provided by an exemplary embodiment of the present application;

Fig. 15 is a schematic flowchart of a clock recovery method provided by an exemplary embodiment of the present application;

Fig. 16 is a schematic structural diagram of a computer device provided by an exemplary embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

In order to facilitate the understanding of the present application, the relevant nouns are firstly explained below.

Clock recovery (timing recovery, TR) circuit: for extracting a clock signal from a received data signal.

Jitter: The short-term deviation of a signal at a particular moment from its ideal position in time. For example, the deviation between the zero crossing of a clock signal and the ideal zero crossing position.

Jitter tolerance: within a certain bit error rate range, under the corresponding input jitter frequency, the maximum jitter amplitude allowed to be added to the data, indicating the ability of the clock recovery to track and correctly sample the data signal with jitter.

Bit error rate (BER): The ratio of the number of bit errors generated by the system transmission data to the total number of codes of the system transmission data, which is used to measure the accuracy of data transmission within a specified time.

Phase interpolation (PI): two reference clock signals with the same frequency but different phases are selected for weighted combination, and the required clock phase is obtained according to the weight ratio. Usually, the reference clock signal is generated by a phase-locked loop (phase-locked loop, PLL) or a delay-locked loop (delay-locked loop, DLL).

Optimal Sampling Phase: The phase that minimizes the BER.

Unit interval (unit interval, UI): The unit used to express the jitter amplitude in the jitter test of the communication signal. The time it takes for a bit to transmit information, for example, the time it takes to transmit a 1 bit, or the time it takes to transmit a 0 bit.

Bathtub curve (bath tub): used to observe jitter and timing analysis, it is a function relationship curve of BER or SNR and sampling position in one UI.

A phase detector is a phase comparison device, also known as a phase comparator. Its output voltage is a function of the instantaneous phase difference of the two signals.

Phase detection gain: the ratio of the phase delay corresponding to the phase difference output by the phase detector to the UI delay.

Fig. 1 is a schematic structural diagram of a receiver provided by an exemplary embodiment of the present application. As shown in FIG. 1 , the receiver includes a sampling circuit 10 , a TR circuit 20 , an equalization circuit 30 and an equalization coefficient control circuit 40 . Wherein, the sampling circuit 10 is used for sampling the received signal under the control of the sampling clock signal to obtain the sampling signal. The TR circuit 20 is used for phase detection of the sampling signal output by the sampling circuit 10 to obtain a phase difference of the sampling signal, and adjust the sampling clock signal according to the phase difference. The equalization circuit 30 has N groups of equalization coefficients, and the equalization circuit 30 is used to perform equalization processing on the sampling signal output by the sampling circuit 10 by using a group of equalization coefficients among the N groups of equalization coefficients corresponding to the phase difference output by the TR circuit 20, wherein N is An integer greater than 1. The equalization coefficient control circuit 40 is configured to update a group of equalization coefficients corresponding to the phase difference output by the TR circuit 20 among the N groups of equalization coefficients.

In the embodiment of the present application, the phase difference of the sampling signal refers to a deviation between a sampling position corresponding to the sampling signal and an optimal sampling position.

In the embodiment of the present application, the update of the equalization coefficient of the equalization circuit is coupled with the sampling position (that is, the phase difference of the sampling signal), and each time the equalization coefficient is updated, only the phase difference corresponding to the output of the clock recovery circuit is updated. A set of equalization coefficients, so that different sets of equalization coefficients can be updated independently. Since the change of the phase difference output by the clock recovery circuit is caused by jitter, and the phase change of the sampling clock signal brought about by the jitter is random, the clock recovery circuit updates a set of equalization coefficients each time is also random. And, after a period of time, each group of equalization coefficients has been updated and converged. Then, for the sampling signal output by the sampling circuit, a set of equalization coefficients corresponding to the phase difference output by the clock recovery circuit is also used for equalization processing, so that the equalization circuit can match the optimal response of different sampling positions based on different sets of equalization coefficients , improve the equalization performance of the equalization circuit, and then improve the communication quality.

The equalization circuit has a plurality of taps, and in some examples, the number of equalization coefficients included in each set of equalization coefficients is equal to the number of taps included in the equalization circuit. In some other examples, the number of equalization coefficients included in each group of equalization coefficients is smaller than the number of taps included in the equalization circuit, and the taps corresponding to the equalization coefficients included in each group of equalization coefficients are the same. For example, the equalization circuit has 25 taps, and each group of equalization coefficients includes 5 equalization coefficients, and these 5 equalization coefficients are the equalization coefficients of the 5 taps located in the middle.

FIG. 2 is a schematic diagram of relationships among four sets of equalization coefficients provided by an exemplary embodiment of the present application. In FIG. 2 , the abscissa indicates the number of the taps in the equalization circuit, and the ordinate indicates the value of the coefficient corresponding to the tap. It should be noted that, FIG. 2 only shows identifications of some taps in the equalization circuit, that is, taps numbered 14-28.

The four curves 51-54 in FIG. 2 represent the values of equalization coefficients of different groups respectively. As shown in FIG. 2 , among the four sets of equalization coefficients, the coefficient values corresponding to tap 21 are basically equal, while the coefficient values corresponding to tap 19 , tap 20 , tap 22 and tap 23 are quite different. It can be seen that among different sets of equalization coefficients, the coefficients corresponding to the same tap may be the same or different. In addition, in different sets of equalization coefficients, at least one tap corresponds to a different coefficient.

According to the phase difference output by the TR circuit, a corresponding set of equalization coefficients is selected to equalize the sampling signal, so that the equalization circuit can match the optimal response of different sampling positions based on different sets of equalization coefficients, and improve the equalization performance of the equalization circuit. Thus improving the communication quality.

Fig. 3 is a schematic structural diagram of a receiver provided by an exemplary embodiment of the present application. As shown in FIG. 3 , the receiver includes a sampling circuit 10 , a TR circuit 20 , an equalization circuit 30 and an equalization coefficient control circuit 40 . Wherein, the sampling circuit 10 is used for sampling the received signal under the control of the sampling clock signal to obtain the sampling signal. The TR circuit 20 is used to adjust the sampling clock signal according to the phase difference output by the sampling circuit 10 . The equalization circuit 30 has N sets of equalization coefficients. The equalization circuit 30 is used to equalize the sampling signal output by the sampling circuit 10 by using a group of equalization coefficients corresponding to the phase difference output by the TR circuit 20 among N groups of equalization coefficients, where N is an integer greater than 1. The equalization coefficient control circuit 40 is configured to update a group of equalization coefficients corresponding to the phase difference output by the TR circuit 20 among the N groups of equalization coefficients.

In the embodiment of the present application, the received signal is an analog signal, and the sampling signal is a digital signal. The sampling circuit 10 includes an analog to digital converter (ADC). ADC is used to convert the received analog signal into digital signal and then output this digital signal.

Exemplarily, the received signal is an M-level signal, where M is an integer greater than 1. Exemplarily, M is 2 or 4.

In some examples, the received signal is a modulated signal subjected to M-ary modulation, for example, a PAM-M signal obtained through M-ary pulse amplitude modulation (pulse amplitude modulation, PAM).

In the embodiment of the present application, the sampling rate of the sampling circuit 10 is single sampling or multiple sampling. Among them, single sampling 10 means that the sampling rate is twice the data transmission rate, which is also called baud rate sampling. Multiple sampling means that the sampling rate is X times the data transmission rate, where X is an integer greater than 1. Compared with multiple sampling, single sampling is beneficial to reduce system power consumption.

The TR circuit 20 includes: a TR filter 21 , a phase detector 22 , a low-pass filter 23 , and a phase regulator 24 . The TR filter 21 is used to filter the sampling signal output by the sampling circuit 10 to eliminate inter symbol interference (inter symbol interference, ISI) and output the filtered sampling signal to the phase detector 22 . The phase detector 22 is used to perform phase detection on the filtered sampling signal and the sampling clock signal to obtain the phase difference of the sampling signal. The low-pass filter 23 is used to filter the phase difference output by the phase detector to filter out noise and obtain the average value of the phase difference. The phase adjuster 24 is used to adjust the phase of the sampling clock signal according to the mean value of the phase difference to obtain a new sampling clock signal.

Exemplarily, the TR filter 21 is a finite impulse response (finite impulse response, FIR) filter.

Exemplarily, the phase adjuster 24 is a phase interpolation (phase interpolation, PI) device. The PI device is used to generate the sampling clock signal based on the reference clock signal according to the mean value of the phase difference.

It should be noted that, in other embodiments, the TR circuit may use other phase regulators to obtain the sampling clock signal, such as a PLL.

The equalization circuit 30 includes an adaptive equalizer 31 , a slicer 32 and an adder 33 . The adaptive equalizer 31 is used to equalize the received sampling signal and output the equalized signal. A limiter 32 is used to convert the equalized signal into a binary signal. The adder 33 is used to calculate the error signal of the equalized signal and the binary signal. The equalization coefficient control circuit 40 is used for adjusting the tap coefficient of the adaptive equalizer 31 according to the error signal output by the adder 33 . In the embodiment of the present application, the tap coefficients of the adaptive equalizer 31 are the equalization coefficients of the equalization circuit 30 .

In the embodiment of the present application, the adaptive equalizer 31 only updates a group of tap coefficients for each beat of data.

Exemplarily, the adaptive equalizer is a least mean square (least mean square, LMS) adaptive equalizer. It should be noted that the adaptive equalizer may also be an adaptive equalizer based on other adaptive algorithms, which is not limited in this application.

The equalization coefficient control circuit 40 includes a feedforward filtering subcircuit 41 , a monitoring subcircuit 42 , an interval determination subcircuit 43 and a control subcircuit 44 . Wherein, the feed-forward filtering sub-circuit 41 is used for filtering the phase difference output by the clock recovery circuit, and outputting the average value of the phase difference. The monitoring sub-circuit 42 is used to monitor the change range of the phase difference output by the feed-forward filter sub-circuit 41 within a unit time length, obtain the phase change interval, and divide the phase change interval into N sub-intervals, and the N sub-intervals correspond to N groups of equalization coefficients respectively. A set of equalization coefficients of , and different groups of equalization coefficients corresponding to different subintervals. The interval determination sub-circuit 43 is used to determine the target sub-interval to which the current phase difference belongs from the N sub-intervals, and the control sub-circuit 44 is used to update a group of equalization coefficients corresponding to the target sub-interval. Wherein, the unit duration can be set according to actual needs, which is not limited in this application.

As the environment of the system changes, the jitter range of the sampling clock signal will also change, so it is necessary to monitor the distribution range of the phase difference output by the clock recovery circuit in real time, so that the phase change interval can basically cover the jitter range, and with the jitter Varies with range. The jitter is random. Correspondingly, a group of equalization coefficients updated for each beat data is also random. After a period of time, each group of equalization coefficients of the equalization circuit is updated and converges. In this way, in different sub-intervals, different sets of equalization coefficients of the equalization circuit correspond to optimal responses at different sampling positions.

For each shot of data, the control subcircuit 44 will compare the current phase difference with N sub-intervals respectively, determine the target sub-interval to which the current phase difference belongs, and then determine a set of equalization coefficients corresponding to the identification of the target sub-interval, and The determined set of equalization coefficients is updated.

FIG. 4 is a schematic diagram of determining a target subinterval according to a phase difference output by a filter in an embodiment of the present application. As shown in Figure 4, the phase change interval is divided into five sub-intervals, each sub-interval corresponds to an identifier idxn, where n is the serial number of the sub-interval, and each identifier corresponds to a set of equalization coefficients. When it is determined that the target subinterval is the third subinterval, the identifier idx3 of the third subinterval is output. Correspondingly, a set of equalization coefficients corresponding to idx3 will be selected subsequently to equalize the sampled signal. And, a group of equalization coefficients corresponding to idx3 will be updated.

In some examples, the N subintervals are equally divided intervals. Equal interval refers to dividing the phase interval into N equal parts to obtain N subintervals, and the difference between the upper and lower limits of each subinterval is equal.

In some other examples, the N subintervals are non-equally partitioned intervals. The non-equal interval means that the phase interval is divided into N parts to obtain N subintervals, and the differences between the upper and lower limits of at least two subintervals among the N subintervals are not equal.

Exemplarily, the value of N is set according to actual needs. Exemplarily, the value of N ranges from 3 to 10, for example, N is equal to 7.

It should be noted that, in other embodiments, the phase change interval may be a fixed range, which is set according to experience. For example, if the working environment of the system is relatively stable and the range of jitter changes is small, a fixed phase change interval can be set in advance.

In the embodiment shown in FIG. 2, the input end of the equalization circuit is connected to the output end of the clock recovery filter, that is, the input end of the equalization circuit is indirectly connected to the output end of the sampling circuit through the clock recovery filter. The equalization circuit equalizes the filtered sampling signal output by the clock recovery filter. In this way, the feed-forward delay can be reduced. Here, the feed-forward delay refers to the delay between the equalization circuit receiving the sampling signal and determining a set of equalization coefficients that need to be updated.

Alternatively, in other embodiments, the output terminal of the equalization circuit is directly connected to the output terminal of the sampling circuit. The equalization circuit is used to equalize the sampling signal output by the sampling circuit.

FIG. 5 is a comparison diagram of BER-based bathtub curves provided by the embodiments of the present application and related technologies. In FIG. 5 , the abscissa represents the phase difference (also called sampling phase) output by the phase detector, and the ordinate represents the BER of the equalized signal output by the equalizing circuit. It can be seen from FIG. 5 that in the bathtub curve 51 corresponding to the embodiment of the present application, when the sampling phase changes between -0.2 and 0.2, the BER is always lower than 1.00E-03. In the bathtub curve 52 corresponding to the related art, when the sampling phase is outside -0.02-0.08, the BER exceeds 1.00E-03. It can be seen that, by adopting the receiver provided in the embodiment of the present application, the impact of the sampling position deviation on the BER is weakened, the bathtub is wider, and the anti-jitter capability is strong.

FIG. 6 is a comparison diagram of the jitter tolerance test results of the receiver provided by the related technology and the embodiment of the present application. In FIG. 6, the abscissa indicates the frequency of the sampling clock signal, and the ordinate indicates the magnitude of the jitter, that is, the UI delay. As shown in FIG. 6, curve 61 represents a standard reference line. Curve 62 represents the magnitude of jitter that the receiver in the related art can tolerate at different frequencies, and curve 63 represents the magnitude of jitter that the receiver of the method provided in the embodiment of the present application can tolerate at different frequencies. It can be seen from FIG. 6 that at different frequencies, the UI delay corresponding to the receiver provided by the embodiment of the present application is greater than the UI delay corresponding to the receiver in the related art. It can be seen that the jitter tolerance capability of the receiver provided in the embodiment of the present application and the receiver in the related art can reach the standard, and the receiver provided in the embodiment of the present application has stronger jitter tolerance than the receiver in the related art .

FIG. 7 is a comparison diagram of bit error rates under different jitters between the receiver provided by the embodiment of the present application and the receiver in the related art. In FIG. 7, the abscissa represents the optical power in dBm, and the ordinate represents the BER. As shown in FIG. 7 , the curves 71 to 78 with asterisks indicate the variation of the BER of the equalized signal output by the equalization circuit of the receiver in the related art under different jitters. Curves 79 to 716 with triangular symbols indicate the variation of the BER of the equalized signal output by the equalization circuit of the receiver provided in the embodiment of the present application under different jitters. It can be seen from Fig. 7 that as the UI increases, the bit error rate of the equalized signal output by the equalization circuit of the receiver in the related art increases with the increase of the UI delay, and the equalization performance of the receiver drops back. Obviously, the bit error rate of the equalized signal output by the equalization circuit of the receiver provided by the embodiment of the present application is basically the same under different UI delays, and the equalization performance of the receiver has a small regression. Moreover, the bit error rate of the equalized signal output by the equalization circuit of the receiver provided by the embodiment of the present application is always small, so it can be seen that the equalization performance of the receiver provided by the embodiment of the present application is better.

Optionally, as shown in FIG. 2 , the receiver further includes a phase detection gain estimation circuit 50 . The phase detection gain estimation circuit 50 is used to determine the phase detection gain of the phase detector according to the phase delay corresponding to the phase difference output by the phase detector 22 and the UI domain delay corresponding to the N subintervals. The TR circuit is used to adjust the phase of the sampling clock signal according to the phase difference and phase detection gain.

Exemplarily, the TR circuit 20 is used to adjust the sampling clock signal according to the product of the phase detection gain and the phase difference.

When the system changes, such as temperature, etc., the phase detector gain also changes. By estimating the phase detection gain in real time and adjusting the phase of the sampling clock signal according to the estimated phase detection gain, the sampling clock signal output by the TR circuit can better track the data clock signal.

Fig. 8 is a schematic diagram of a phase detection gain curve obtained through simulation provided by an exemplary embodiment of the present application. The simulation conditions are: direct inspection of the PAM4 system. As shown in FIG. 8 , the abscissa represents the UI delay corresponding to each sub-interval, and the ordinate represents the phase delay corresponding to the phase difference output by the phase detector.

In a possible implementation, Fourier transform is performed on N groups of equalization coefficients, and the phase-frequency response corresponding to each group of coefficients is extracted to obtain N phase values; The first difference between, that is, the a value in Figure 8; then, calculate the second difference between the phases corresponding to the first phase subinterval and the last phase subinterval, that is, the b value in Figure 8; finally , and divide the second difference by the first difference to obtain the phase detection gain.

In the embodiment of the present application, the phase corresponding to the phase sub-interval is the central value of the phase sub-interval, for example, the phase corresponding to the phase sub-interval 0-1 is 0.5.

Optionally, as shown in FIG. 2 , the receiver further includes an optimal phase tracking circuit 60 . The optimal phase tracking circuit 60 is used to perform statistics on the transmission performance of the equalized signals output by the equalization circuit 30 for the N sub-intervals to obtain statistical results; and determine the optimal sampling phase deviation according to the statistical results. The TR circuit 20 is also used to adjust the phase of the sampling clock signal according to the optimal sampling phase deviation. In the embodiment of the present application, the optimal sampling phase deviation is used to indicate the adjustment direction and step size of the sampling clock signal.

Wherein, performing statistics on the transmission performance for the N sub-intervals respectively refers to performing statistics on the transmission performance of each beat data according to the corresponding phase sub-intervals.

In the embodiment of the present application, the transmission performance is SNR or BER. Determining the optimal sampling phase deviation according to the statistical results refers to taking the phase corresponding to the optimal transmission performance as the optimal sampling phase deviation. When the transmission performance is SNR, the optimal transmission performance means that the SNR is the largest. When the transmission performance is BER, the optimal transmission performance refers to the minimum BER.

Exemplarily, the optimal sampling phase deviation is determined according to the bathtub curve.

In a possible implementation, the optimal sampling phase deviation is determined according to an SNR-based bathtub curve. The phase corresponding to the point with the largest SNR in the SNR-based bathtub curve is determined as the optimal sampling phase deviation. In the embodiment of the present application, the SNR values corresponding to each phase sub-interval are connected to obtain the SNR-based bathtub curve.

In another possible implementation, the optimal sampling phase offset is determined according to a BER-based bathtub curve. For the coordinate system where the BER-based bathtub curve is located, the abscissa represents the phase difference output by the phase detector, and the ordinate represents the BER corresponding to the balanced signal. In the BER-based bathtub curve, the phase corresponding to the point with the smallest BER is determined as the optimal sampling phase deviation.

Fig. 9 is a schematic diagram of an SNR-based bathtub curve provided by an exemplary embodiment of the present application. In FIG. 9 , the abscissa represents the phase difference output by the phase detector, and the ordinate represents the SNR corresponding to the equalized signal, and the unit is dB. It can be seen from FIG. 9 that the phase change interval is divided into six phase sub-intervals. The first to sixth phase subintervals are -0.3~-0.2, -0.2~-0.1, -0.1~0, 0~0.1, 0.1~0.2, 0.2~0.3 respectively. The SNRs corresponding to the first to sixth phase subintervals are 17.74, 17.93, 17.97, 17.92, and 17.63, respectively. The phase sub-interval corresponding to the point with the largest SNR is -0.1 to 0, and the sampling phase corresponding to the phase sub-interval is -0.05, therefore, -0.05 is taken as the optimal sampling phase deviation.

In yet another possible implementation, the optimal sampling phase deviation is determined based on a bathtub curve of SNR and a histogram of different jitters. For example, calculate the integral of the SNR and the jitter amount corresponding to each phase subinterval separately to obtain the first integral value; delay the jitter amount by one phase subinterval, and then calculate the SNR corresponding to each phase subinterval and the jitter amount Integrate to get the second integral value; then delay the amount of jitter by one phase subinterval, calculate the third integral value, and so on, until the Nth integral value is calculated, that is, the number of phase subintervals is calculated equal number of integral values, and finally, the delay corresponding to the largest integral value is determined as the optimal sampling phase deviation.

Calculating the integral of the SNR corresponding to each phase subinterval and the amount of jitter refers to multiplying the SNR corresponding to the first phase subinterval by the number of times corresponding to the first phase subinterval, and multiplying the SNR corresponding to the second phase subinterval Multiply by the number corresponding to the second phase subinterval, ... multiply the SNR corresponding to the Nth phase subinterval by the number of times corresponding to the Nth phase subinterval, and then add the products corresponding to the N phase subintervals , to get the first integral value.

Delay the amount of jitter by one phase sub-interval, and then calculate the integral of the SNR corresponding to each phase sub-interval and the jitter amount again, which refers to comparing the SNR corresponding to the first phase sub-interval with the number of times corresponding to the second phase sub-interval Multiply, multiply the SNR corresponding to the second phase subinterval by the number of times corresponding to the third phase subinterval, ... multiply the SNR corresponding to the Nth phase subinterval by the number of times corresponding to the first phase subinterval, Then the products corresponding to the N phase subintervals are added together to obtain the second integral value. By analogy, the Nth integral value is calculated.

Assuming that the maximum integral value is the corresponding integral value when the i-th phase sub-interval is delayed, the phase difference corresponding to the i-th phase sub-interval is taken as the optimal sampling phase deviation.

An example will be described below with reference to FIG. 9 and FIG. 10 .

Fig. 10 is a statistical schematic diagram of the number of occurrences of phase differences corresponding to different phase sub-intervals in an exemplary embodiment of the present application. In FIG. 10 , the abscissa represents the phase subinterval, and the ordinate represents the number of times the phase difference output by the phase detector appears in the corresponding phase subinterval.

In Figure 9 and Figure 10, the number of phase sub-intervals is 6, and the first to sixth phase sub-intervals are -0.3～-0.2, -0.2～-0.1, -0.1～0, 0～0.1, 0.1～0.2, 0.2～0.3. The SNRs corresponding to the first to sixth phase subintervals are 17.74, 17.93, 17.97, 17.94, 17.92, and 17.63, respectively. The times corresponding to the first to sixth phase subintervals are 100, 370, 150, 150, 380 and 80 respectively. In the example shown in Figure 9 and Figure 10, the calculated first integral value is 22014.6, the second integral value is 21962.6, the third integral value is 21929.4, the fourth integral value is 21980.9, and the fifth integral value The value is 21942.9, and the 6th integral value is 21939.5. The maximum integral value is the first integral value, and the delay is 0, so the best sampling phase deviation is 0.

It should be noted that both Fig. 9 and Fig. 10 are data obtained under the scenario where the jitter is UIpp (peak-to-peak) 0.3 and the jitter frequency is 8 MHz.

Fig. 11 is a schematic structural diagram of another receiver provided by an exemplary embodiment of the present application. As shown in FIG. 11 , in the embodiment shown in FIG. 11 , the optimal sampling phase tracking circuit 60 is used to perform transmission performance statistics on the signals output by the TR filter 21 in the TR circuit 20 for the N subintervals, obtaining a statistical result; and determining an optimal sampling phase deviation according to the statistical result.

It should be noted that the connection relationship between the coefficient control subcircuit and the interval determination subcircuit in the equalization coefficient control circuit is omitted in FIG. 11 , which is actually the same as that in FIG. 2 .

In the embodiment of the present application, the receiver is an integrated circuit (integrated circuit, IC) chip.

It should be noted that the structures of the receivers shown in FIG. 1 , FIG. 2 and FIG. 11 are applicable to optical communication systems, for example, direct modulation, direct detection optical communication systems, coherent optical communication systems, and the like. In the direct modulation and direct detection optical communication system, direct modulation refers to the direct modulation of the laser through modulation technology at the transmitting end. Modulation technology includes but not limited to positive amplitude modulation (QAM), phase shift keying (PSK), frequency shift Keying (FSK), Amplitude Shift Keying (ASK), Non-Return to Zero (NRZ) line coding, Pulse Amplitude Modulation (PAM), etc. Direct detection means that the receiver performs photoelectric conversion on the received optical signal through an optical module to obtain an electrical signal, and then directly detects the electrical signal to obtain received data. In a coherent optical communication system, the transmitting end uses the signal to be transmitted to change the frequency, phase and amplitude of the coherent optical carrier to obtain a coherently modulated optical signal. Coherently coupled and then detected by a balanced receiver.

In other examples, the receiver is also suitable for use in wireless communication systems, such as Wireless High Fidelity (WIFI) systems.

Fig. 12 is a schematic flowchart of a receiver equalization method provided by an exemplary embodiment of the present application. Applied to the receiver shown in Figure 1 or Figure 2 or Figure 11. As shown in Figure 12, the method includes the following processes.

1201: Sampling the received signal under the control of the sampling clock signal to obtain a sampling signal.

1202: Determine the phase difference of the sampling signal through a clock recovery circuit.

1203: Perform equalization processing on the sampled signal by using a set of equalization coefficients corresponding to the phase difference among N sets of equalization coefficients through an equalization circuit to obtain an equalized signal.

1204: Update a group of equalization coefficients corresponding to the phase difference output by the clock recovery circuit among the N groups of equalization coefficients.

In the embodiment of the present application, the update of the equalization coefficient of the equalization circuit is coupled with the sampling position (that is, the phase difference of the sampling signal), and each time the equalization coefficient is updated, only a group of equalization coefficients corresponding to the phase difference output by the clock recovery circuit are updated , so that the equalization coefficients of different groups can be updated independently. Since the change of the phase difference output by the clock recovery circuit is generated by jitter, and the phase change caused by the jitter is random, the clock recovery circuit updates a set of equalization coefficients each time is also random. And, after a period of time, each group of equalization coefficients has been updated and converged. Then, for the sampling signal output by the sampling circuit, a set of equalization coefficients corresponding to the phase difference output by the clock recovery circuit is also used for equalization processing, so that the equalization circuit can match the optimal response of different sampling positions based on different sets of equalization coefficients , improve the equalization performance of the equalization circuit, and then improve the communication quality.

Optionally, the phase change interval corresponding to the phase difference output by the clock recovery circuit includes N subintervals, and the N subintervals respectively correspond to a group of equalization coefficients in the N groups of equalization coefficients.

Step 1203 includes: determining the target sub-interval to which the current phase difference belongs from the N sub-intervals; controlling the equalization circuit to update a group of equalization coefficients corresponding to the target sub-interval.

In a possible implementation manner, the phase change interval is a set interval.

In another possible implementation manner, the phase change interval is a phase change interval within a unit time length obtained by monitoring the change range of the phase difference output by the phase detector in real time.

In this embodiment, step 1203 further includes: monitoring the variation range of the phase difference output by the clock recovery circuit within a unit time length to obtain a phase variation interval; and dividing the phase variation interval into N subintervals.

Optionally, the N subintervals are equally partitioned intervals, or the N subintervals are non-equally partitioned intervals.

Optionally, the equalization method further includes: determining the phase detection gain according to the phase delay corresponding to the phase difference and the UI domain delay corresponding to the N subintervals; and adjusting the sampling clock signal according to the phase detection gain and the phase difference.

Optionally, the equalization method further includes: performing statistics on the transmission performance of the equalized signal output by the equalization circuit for the N sub-intervals to obtain statistical results; determining the optimal sampling phase deviation according to the statistical results; adjusting the sampling clock according to the optimal sampling phase deviation the phase of the signal.

Fig. 13 is a schematic structural diagram of a clock recovery circuit provided by an exemplary embodiment of the present application. As shown in Figure 13, the clock recovery circuit 1300 includes a sampler 1301, an adaptive equalizer 1302 (also known as a loop filter or TR filter), a phase detector 1303, a low-pass filter 1304, a phase regulator 1305 and a control Circuit 1307. The sampler 1301 is used to sample the received signal under the control of the sampling clock signal to obtain a sampled signal; the adaptive equalizer 1302 has a plurality of equalization coefficients, and the adaptive equalizer is used to perform equalization processing on the sampled signal by using a plurality of equalization coefficients, Obtain the equalized signal; the phase detector 1303 is used to perform phase detection on the equalized signal output by the adaptive equalizer to obtain the phase difference of the equalized signal; the low-pass filter 1304 is used to filter the phase difference; the phase regulator 1305 is used to filter the phase difference according to The average value of the phase difference adjusts the phase of the sampling clock signal; the control circuit 1306 is used to control the update of the equalization coefficient of the equalizer according to the phase difference output by the phase detector 1303 .

In some examples, the control circuit 1306 is configured to control the update of the equalization coefficient of the adaptive equalizer in response to determining that the phase difference belongs to the target phase interval; or, the control circuit 1306 is configured to control the automatic The equalization coefficients of the adaptive equalizer remain unchanged.

Exemplarily, the sampler 1301 is an ADC. Adaptive equalizer 1302 includes, but is not limited to, FIR filters and the like. The phase regulator 1304 includes but is not limited to a PI device and the like.

The filter can be adaptively locked to any phase by constrained updating of the equalization coefficients of the adaptive equalizer.

Fig. 14 is a schematic diagram of outputting an enable signal according to a phase difference output by a filter in a clock recovery circuit provided by an exemplary embodiment of the present application. As shown in FIG. 14 , a sub-interval is selected from the phase change interval as the target phase interval. When it is determined that the phase difference belongs to the target phase interval, a high level is output as an enabling signal. When it is determined that the phase difference does not belong to the target phase interval, a low level is output.

13 again, the clock recovery circuit 1300 also includes a limiter 1307 and an adder 1308, the limiter 1307 is used to convert the equalized signal output by the adaptive equalizer into a binary signal, and the adder 1308 is used to determine the equalized signal and the binary signal The error between the signals; the controller is used to update the equalization coefficient of the adaptive equalizer according to the error and the phase difference output by the phase detector.

Optionally, the clock recovery circuit also includes: an optimal phase tracking circuit (not shown in the figure), which is used to perform statistics on the transmission performance of the equalized signal according to the phase interval to obtain statistical results; and determine the optimal sampling phase deviation according to the statistical results ; Adjusting the phase of the sampling clock signal according to the optimal sampling phase deviation.

In this embodiment of the present application, adjusting the phase of the sampling clock signal according to the optimal sampling phase deviation includes adjusting the center position of the target phase interval according to the optimal sampling phase deviation. It is equivalent to shifting the target phase interval in the phase change interval.

It should be noted that the structure in FIG. 13 can be combined into the embodiment shown in FIG. 1 or FIG. 2 or FIG. 11 .

The application also provides a receiver. As shown in FIG. 13 , the receiver includes a clock recovery circuit 1300 and an equalization circuit 1400 . The equalization circuit is used to equalize the sampled signal output by the sampler. The structure of the equalization circuit can adopt any one of the related technologies, which is not limited in this application.

FIG. 15 is a schematic flowchart of a clock recovery method provided by an embodiment of the present application. As shown in Figure 15, the clock recovery method includes the following processes.

1501: Using an adaptive equalizer to equalize the sampling signal output by the sampling circuit to obtain an equalized signal.

Wherein, the adaptive equalizer has multiple equalization coefficients, and the sampling signal is output by the sampling circuit under the control of the sampling clock signal.

1502: Perform phase detection on the equalized signal output by the adaptive equalizer to obtain a phase difference.

1503: Control updating of equalization coefficients of the adaptive equalizer according to the phase difference.

1504: Adjust the phase of the sampling clock signal according to the phase difference.

In this embodiment of the application, 1504 includes: in response to determining that the phase difference belongs to the target phase interval, controlling the update of the equalization coefficient of the adaptive equalizer; or in response to determining that the phase difference does not belong to the target phase interval, controlling the equalization of the adaptive equalizer Coefficients remain the same.

In some examples, the clock recovery method further includes: performing statistics on the transmission performance of the equalized signal according to the phase interval to obtain statistical results; and determining the optimal sampling phase deviation according to the statistical results; The phase of the sampling clock signal.

In this embodiment of the present application, adjusting the phase of the sampling clock signal according to the optimal sampling phase deviation includes adjusting the center position of the target phase interval according to the optimal sampling phase deviation. It is equivalent to shifting the target phase interval in the phase change interval.

It should be noted that the equalization method of the receiver provided by the above-mentioned embodiment belongs to the same idea as the embodiment of the receiver, and its specific implementation process is detailed in the embodiment of the receiver, and the clock recovery method and the embodiment of the clock recovery circuit belong to the same idea , and its specific implementation process can be found in the embodiment of the clock recovery circuit, and will not be repeated here.

The embodiment of the present application also provides a computer device. FIG. 16 exemplarily provides a possible architectural diagram of a computer device 11600 .

The computer device 1600 includes a memory 1601 , a processor 1602 , a communication interface 1603 and a bus 1604 . Wherein, the memory 1601 , the processor 1602 , and the communication interface 1603 are connected to each other through a bus 1604 .

The memory 1601 may be a read only memory (Read Only Memory, ROM), a static storage device, a dynamic storage device or a random access memory (Random Access Memory, RAM). The memory 1601 may store programs, and when the programs stored in the memory 1601 are executed by the processor 1602, the processor 1602 and the communication interface 1603 are used to execute the equalization method of the receiver. The memory 1601 may also store data sets. For example, a part of storage resources in the memory 1601 is divided into a data set storage module, which is used to store related data of N subintervals.

The processor 1602 may be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a graphics processing unit (graphics processing unit, GPU) or one or more integrated circuit.

The processor 1602 may also be an integrated circuit chip with signal processing capability. During implementation, part or all of the functions of the device for identifying vehicle operating behavior of the present application may be implemented by hardware integrated logic circuits in the processor 1602 or instructions in the form of software. The above-mentioned processor 1602 may also be a general-purpose processor, a digital signal processor (Digital Signal Processing, DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices , discrete gate or transistor logic devices, discrete hardware components. Various methods disclosed in the foregoing embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory 1601, and the processor 1602 reads the information in the memory 1601, and combines its hardware to complete part of the functions of the equalization device of the receiver in the embodiment of the present application.

The communication interface 1603 uses a transceiver module such as but not limited to a transceiver to implement communication between the computer device 1600 and other devices or communication networks. For example, reception signals and the like can be acquired through the communication interface 1603 .

Bus 1604 may include pathways for transferring information between various components of computer device 1600 (eg, memory 1601 , processor 1602 , communication interface 1603 ).

The descriptions of the processes corresponding to the above-mentioned figures have their own emphasis. For the parts not described in detail in a certain process, you can refer to the relevant descriptions of other processes.

In the embodiment of the present application, a computer-readable storage medium is also provided. The computer-readable storage medium stores computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by a computer device, the computer device executes the above-mentioned The equalization method or clock recovery method of the receiver provided.

In the embodiment of the present application, there is also provided a computer program product including instructions, which, when running on a computer device, causes the computer device to execute the receiver equalization method or the clock recovery method provided above.

In the above-mentioned embodiments, all or part may be implemented by software, hardware, firmware or any combination thereof, and when software is used, all or part may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions, and when the computer program instructions are loaded and executed on the server or terminal, all or part of the processes or functions according to the embodiments of the present application will be generated. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a server or a terminal, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, and a magnetic tape, etc.), an optical medium (such as a digital video disk (Digital Video Disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

Claims (26)

1. A receiver, characterized in that the receiver comprises:

the sampling circuit is used for sampling the received signal under the control of the sampling clock signal to obtain a sampling signal;

the clock recovery circuit is used for demodulating the phase of the sampling signal output by the sampling circuit to obtain the phase difference of the sampling signal and adjusting the sampling clock signal according to the phase difference;

the equalization circuit is provided with N groups of equalization coefficients and is used for performing equalization processing on the sampling signal output by the sampling circuit by adopting one group of equalization coefficients corresponding to the phase difference output by the clock recovery circuit in the N groups of equalization coefficients, wherein N is an integer larger than 1;

and the equalization coefficient control circuit is used for updating a group of equalization coefficients corresponding to the phase difference output by the clock recovery circuit in the N groups of equalization coefficients.

2. The receiver of claim 1, wherein the phase variation interval corresponding to the phase difference output by the clock recovery circuit includes N sub-intervals, and the N sub-intervals respectively correspond to one of the N sets of equalization coefficients;

the equalization coefficient control circuit includes:

an interval determination sub-circuit for determining a target sub-interval to which the current phase difference belongs from among the N sub-intervals, an

And the control sub-circuit is used for updating a group of equalization coefficients corresponding to the target sub-interval.

3. The receiver of claim 2, wherein the equalization coefficient control circuit further comprises:

and the monitoring sub-circuit is used for monitoring the change range of the phase difference output by the clock recovery circuit in unit time length to obtain the phase change interval and dividing the phase change interval into the N sub-intervals.

4. The receiver of claim 3, wherein the equalization coefficient control circuit further comprises a feed-forward filter for filtering the phase difference output by the clock recovery circuit and outputting the filtered phase difference to the monitoring sub-circuit.

5. The receiver according to any of claims 2 to 4, wherein the N subintervals are equally spaced intervals or wherein the N subintervals are non-equally spaced intervals.

6. The receiver of any of claims 2 to 5, wherein the clock recovery circuit comprises:

the clock recovery filter is used for filtering the sampling signal output by the sampling circuit to obtain a filtered sampling signal;

the phase discriminator is used for carrying out phase discrimination on the filtered sampling signals to obtain the phase difference;

the low-pass filter is used for filtering the phase difference output by the phase discriminator to obtain a phase difference average value;

the phase adjuster is used for adjusting the phase of the sampling clock signal according to the phase difference average value;

and the equalizing circuit is used for equalizing the filtered sampling signal output by the clock recovery filter.

7. The receiver according to any of claims 2 to 5, wherein each of the N subintervals corresponds to a UI domain delay, the receiver further comprising:

the phase discrimination gain estimation circuit is used for determining phase discrimination gain according to the phase delay corresponding to the phase difference output by the clock recovery circuit and the UI domain delay corresponding to the N subintervals;

the clock recovery circuit is used for adjusting the sampling clock signal according to the phase discrimination gain and the phase difference.

8. The receiver according to any of claims 2 to 5, characterized in that the receiver further comprises:

the optimal phase tracking circuit is used for respectively carrying out transmission performance statistics on the balanced signals output by the balancing circuit aiming at the N subintervals to obtain a statistical result; determining the optimal sampling phase deviation according to the statistical result;

the clock recovery circuit is further configured to adjust a phase of a sampling clock signal according to the optimal sampling phase offset.

9. The receiver of claim 6, further comprising:

the optimal phase tracking circuit is used for respectively carrying out transmission performance statistics on the filtered sampling signals output by the clock recovery filter aiming at the N subintervals to obtain a statistical result; determining the optimal sampling phase deviation according to the statistical result;

the clock recovery circuit is further configured to adjust a phase of a sampling clock signal according to the optimal sampling phase offset.

10. An equalization method for a receiver, characterized in that the receiver comprises a clock recovery circuit and an equalization circuit, the equalization circuit having N sets of equalization coefficients, where N is an integer greater than 1,

the method comprises the following steps:

sampling the received signal under the control of a sampling clock signal to obtain a sampling signal;

carrying out phase discrimination on the sampling signals through the clock recovery circuit to obtain the phase difference of the sampling signals;

the equalization circuit performs equalization processing on the sampling signal by adopting a group of equalization coefficients corresponding to the phase difference in the N groups of equalization coefficients to obtain an equalization signal;

and updating a group of equalization coefficients corresponding to the phase difference in the N groups of equalization coefficients.

11. The equalizing method according to claim 10, wherein the phase change section corresponding to the phase difference output by the clock recovery circuit includes N subintervals, and each of the N subintervals corresponds to one of the N sets of equalizing coefficients;

updating a set of equalization coefficients corresponding to the phase difference from the N sets of equalization coefficients, including:

determining a target subinterval to which the current phase difference belongs from the N subintervals;

and controlling the equalization circuit to update a group of equalization coefficients corresponding to the target subintervals.

12. The equalizing method according to claim 11, wherein the updating a set of equalization coefficients corresponding to the phase difference from among the N sets of equalization coefficients further comprises:

monitoring the variation range of the phase difference output by the clock recovery circuit in unit time length to obtain the phase variation interval;

dividing the phase change interval into the N subintervals.

13. Equalizing method according to claim 11 or 12, wherein said N sub-intervals are equally divided intervals or wherein said N sub-intervals are non-equally divided intervals.

14. Equalizing method according to one of the claims 11 to 13, characterized in that the equalizing method further comprises:

determining phase discrimination gain according to the phase delay corresponding to the phase difference and the UI domain delay corresponding to the N subintervals;

and adjusting the sampling clock signal according to the phase discrimination gain and the phase difference.

15. Equalizing method according to one of the claims 11 to 14, characterized in that the equalizing method further comprises:

respectively carrying out transmission performance statistics on the balanced signals aiming at the N subintervals to obtain a statistical result;

determining the optimal sampling phase deviation according to the statistical result;

and adjusting the phase of the sampling clock signal according to the optimal sampling phase deviation.

16. A clock recovery circuit, the clock recovery circuit comprising:

the sampler is used for sampling the received signal under the control of the sampling clock signal to obtain a sampling signal;

the adaptive equalizer is used for carrying out equalization processing on the sampling signal by adopting the plurality of equalization coefficients to obtain an equalized signal;

the phase discriminator is used for discriminating the phase of the equalized signal output by the self-adaptive equalizer to obtain the phase difference of the equalized signal;

the low-pass filter is used for filtering the phase difference to obtain a phase difference mean value;

the phase adjuster is used for carrying out phase adjustment on the sampling clock signal according to the phase difference average value;

and the control circuit is used for controlling the updating of the equalization coefficient of the self-adaptive equalizer according to the phase difference output by the phase discriminator.

17. The clock recovery circuit of claim 16, wherein the control circuit is configured to control equalization coefficient updates of the adaptive equalizer in response to determining that the phase difference belongs to a target phase interval; or,

the control circuit is configured to control an equalization coefficient of the adaptive equalizer to remain unchanged in response to determining that the phase difference does not belong to a target phase interval.

18. The clock recovery circuit of claim 16 or 17, further comprising a slicer for converting an equalized signal output by the adaptive equalizer into a binary signal, and an adder for determining an error between the equalized signal and the binary signal;

and the control circuit is used for updating the equalization coefficient of the self-adaptive equalizer according to the error and the phase difference output by the phase discriminator.

19. The clock recovery circuit of claim 17, wherein the clock recovery circuit further comprises:

the optimal phase tracking circuit is used for carrying out transmission performance statistics on the balanced signals according to the phase subintervals to obtain a statistical result; determining an optimal sampling point according to the statistical result; and adjusting the phase of the sampling clock signal according to the optimal sampling phase deviation.

20. The clock recovery circuit of claim 19, wherein the optimal phase tracking circuit is configured to adjust the position of the target phase interval based on the optimal sampling phase offset.

21. A receiver, characterized in that the receiver comprises: a clock recovery circuit according to any one of claims 16 to 19 and an equalization circuit for equalizing the sampled signal output by the sampler.

22. A method of clock recovery, the method comprising:

the method comprises the steps that a sampling signal output by a sampling circuit is equalized by a self-adaptive equalizer to obtain an equalized signal, the self-adaptive equalizer is provided with a plurality of equalization coefficients, and the sampling signal is output by the sampling circuit under the control of a sampling clock signal;

performing phase discrimination on the equalized signals output by the self-adaptive equalizer to obtain the phase difference of the equalized signals;

controlling the updating of the equalization coefficient of the self-adaptive equalizer according to the phase difference;

and carrying out phase adjustment on the sampling clock signal according to the phase difference.

23. The method of claim 22, wherein controlling the updating of the equalization coefficients of the adaptive equalizer according to the phase difference comprises:

in response to determining that the phase difference belongs to a target phase interval, controlling an equalization coefficient update of the adaptive equalizer; or,

controlling equalization coefficients of the adaptive equalizer to remain unchanged in response to determining that the phase difference does not belong to a target phase interval.

24. The method of claim 23, further comprising:

determining an optimal sampling phase deviation;

and adjusting the position of the target phase interval according to the optimal sampling phase deviation.

25. A computer device, comprising a processor and a memory, wherein:

the memory having stored therein computer instructions;

the processor executes the computer instructions to implement the method of any of claims 10 to 15 or the method of any of claims 22 to 24.

26. A computer-readable storage medium storing computer instructions which, when executed by a computer device, cause the computer device to perform the method of any one of claims 10 to 15 or to implement the method of any one of claims 22 to 24.

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