CN115274806A - Display substrate, display panel and display device - Google Patents

Abstract

The application discloses a display substrate, a display panel and a display device. The display substrate is provided with a display area and a non-display area at least partially surrounding the display area, and the non-display area comprises a binding area; the display substrate includes: a substrate; a plurality of data lines on the substrate and in the display region; a plurality of first connection lines on the substrate and in the display region, the first connection lines transmitting signals from the binding region to the data lines; the at least partially stripe first connection line comprises a first portion and a second portion, the second portion is connected between the first portion and the data line, and an orthographic projection of the first portion on the substrate at least partially overlaps with an orthographic projection of the second portion on the substrate. According to the embodiment of the application, the display uniformity is improved.

Description

Display substrate, display panel and display device

technical field

The present application relates to the field of display technology, in particular to a display substrate, a display panel and a display device.

Background technique

With the continuous update of display panel technology, the display panel is gradually developing towards thinner and lighter, higher screen-to-body ratio, and ultra-narrow bezel.

The display panel generally includes a display area and a non-display area located around the display area, and the non-display area is used for arranging signal lines. For example, the non-display area can be used to route fan-out traces. In related technologies, part of the fan-out wiring can be arranged in the display area to reduce the width of the non-display area, thereby achieving a narrower border. However, in the related art, there is still a problem of poor display.

Contents of the invention

Embodiments of the present application provide a display substrate, a display panel, and a display device, which are beneficial to improving display uniformity.

In a first aspect, an embodiment of the present application provides a display substrate, which has a display area and a non-display area at least partially surrounding the display area, the non-display area includes a binding area; the display substrate includes: a substrate; a plurality of data lines located on the substrate on the bottom and located in the display area; a plurality of first connection lines, located on the substrate and located in the display area, the first connection lines transmit signals from the binding area to the data lines; at least some of the first connection lines include the first part and The second part, the second part is connected between the first part and the data line, the orthographic projection of the first part on the substrate and the orthographic projection of the second part on the substrate at least partially overlap.

Based on the same inventive concept, in the second aspect, the embodiments of the present application provide a display panel, including the display substrate according to any one of the embodiments in the first aspect.

Based on the same inventive concept, in a third aspect, the embodiments of the present application provide a display device, including the display panel according to any one of the embodiments in the second aspect.

According to the display substrate, display panel and display device provided by the embodiments of the present application, since the first part and the second part overlap at least in part, for the first connection wiring including the first part and the second part, it adopts a folding The design method of the wiring, so that the total length of the first connecting wiring can be extended in a limited plane space, so that the resistance of the first connecting wiring can be adjusted by extending at least part of the total length of the first connecting wiring, which has It is beneficial to make the resistances of the first connecting wires tend to be consistent, thereby reducing the difference in resistance loading (R Loading) of the first connecting wires, thereby improving display uniformity.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals represent the same or similar features, appended Figures are not drawn to scale.

FIG. 1 shows a schematic structural view of a display substrate provided by an embodiment of the present application;

FIG. 2 shows an enlarged schematic diagram of area Q1 in FIG. 1;

Fig. 3 shows a schematic cross-sectional view of A-A' direction in Fig. 2;

FIG. 4 shows a schematic diagram of a layer structure of a display substrate provided by an embodiment of the present application;

FIG. 5 shows a schematic structural view of a display substrate provided by an embodiment of the present application;

Fig. 6 shows an enlarged schematic view of area Q2 in Fig. 5;

FIG. 7 shows a schematic structural diagram of a display panel provided according to an embodiment of the present application;

FIG. 8 shows a schematic structural diagram of a display device provided according to an embodiment of the present application.

Detailed ways

The characteristics and exemplary embodiments of various aspects of the application will be described in detail below. In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only configured to explain the application, not to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the statement "comprising..." does not exclude the presence of additional same elements in the process, method, article or device comprising said element.

It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the part is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

It should be understood that the term "and/or" used herein is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B, which may mean that A exists alone, and A and B exist simultaneously. B, there are three situations of B alone. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

In the embodiment of the present application, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not an actual circuit unit.

It will be apparent to those skilled in the art that various modifications and changes can be made in the application without departing from the spirit or scope of the application. Therefore, the present application intends to cover the modifications and changes of the present application falling within the scope of the corresponding claims (technical solutions to be protected) and their equivalents. It should be noted that, the implementation manners provided in the embodiments of the present application may be combined with each other if there is no contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the related technologies:

In the related art, part of the fan-out lines can be arranged in the display area, and the fan-out lines arranged in the display area can be connected with part of the data lines. The inventor found that the distribution positions of the data lines are different, and the lengths of the fan-out lines connected to the data lines arranged in the display area are different, resulting in different impedances caused by the fan-out lines, which is not conducive to achieving display uniformity.

In order to solve the above problems, embodiments of the present application provide a display substrate, a display panel, and a display device. Embodiments of the display substrate, display panel, and display device will be described below with reference to the accompanying drawings.

Firstly, the display substrate provided by the embodiment of the present application is introduced.

FIG. 1 shows a schematic structural diagram of a display substrate provided by an embodiment of the present application. FIG. 2 shows an enlarged schematic view of area Q in FIG. 1 . Fig. 3 shows a schematic cross-sectional view of A-A' direction in Fig. 2 . As shown in FIG. 1 , the display substrate 100 may have a display area AA and a non-display area NA. The non-display area NA at least partially surrounds the display area AA. FIG. 1 shows that the non-display area NA completely surrounds the display area AA.

Edges of the display area AA may form a right angle, for example, the display area AA may be a rectangle. The edges of the display area AA may also form curved corners.

The non-display area NA may include a binding area BA. The binding area BA may include binding terminals (not shown in the figure), the flexible circuit board may be bound and connected to the binding terminals, and the driving chip may be bound to the flexible circuit board. The flexible circuit board can be bent to the back of the display substrate 100 , so that the driving chip can be located on the back of the display substrate 100 to achieve a narrow frame. The binding terminals in the binding area BA can transmit driving signals, for example, the binding terminals can be used to transmit data signals to the display area.

Continuing to refer to FIG. 1 , the display substrate 100 may include a substrate 10 , a plurality of data lines 21 and a plurality of first connection lines 31 .

The substrate 10 may be a flexible substrate or a rigid substrate. The substrate 10 may include a display area AA and a non-display area NA.

A plurality of data lines 21 are located on the substrate 10 and disposed in the display area AA. A plurality of data lines 21 may be arranged in the first direction X, and the data lines 21 may extend along the second direction Y. The first direction X may be a row direction, and the second direction Y may be a column direction.

The display substrate 100 may also include a plurality of scanning lines (not shown in the figure) and a plurality of pixel circuits (not shown in the figure). The extending direction of the scan lines intersects with the data lines 21 . A plurality of pixel circuits may be arranged in an array.

A plurality of first connection lines 31 are located on the substrate 10 and located in the display area AA. The total number of data lines 21 can be more than the total number of first connection lines 31, part of the data lines 21 are connected to the first connection lines 31, and the first connection lines 31 transmit the signal from the binding area BA to the data connected to it. Line 21.

As an example, the display substrate 100 may further include a second connection line 32, and the second connection line 32 is located in the non-display area NA. Specifically, the second connection line 32 may be located in the non-display area between the binding area BA and the display area NA. District NA. Another part of the data line 21 can be connected to the second connection line 32 , and the second connection line 32 transmits the signal from the bonding area BA to the data line 21 connected thereto.

In order to better distinguish the data lines connected by the first connection line 31 and the second connection line 32 respectively, the data line connected by the first connection line 31 is called the first type data line 211 herein, and the data line connected by the second connection line 32 The data lines are called the second type data lines 212 . In the first direction X, multiple first-type data lines 211 may be disposed on both sides, and multiple second-type data lines 212 may be disposed between the first-type data lines 211 .

The first connection line 31 and the second connection line 32 are connected to the bonding terminals in the bonding area BA. The first connection line 31 and the second connection line 32 can also be called fanout lines. The difference between the two is , the first connection line 31 is set in the display area AA, and the second connection line 32 is set in the non-display area AA.

Exemplarily, in order to realize the connection between the first connection line 31 and the binding terminal in the binding area BA, a third connection line 33 can also be set in the non-display area NA, and the third connection line 33 is connected between the first connection line 31 and the binding terminal. Between the binding terminals in the binding area BA.

As shown in FIG. 2 and FIG. 3 , among the plurality of first connecting wires 31, at least some of the first connecting wires 31 may include a first part 311 and a second part 312 connected to each other, and the second part 312 may be connected to the Between a part 311 and the first type of data line 211 . As shown in FIG. 2 , the orthographic projection of the first portion 311 on the substrate 10 and the orthographic projection of the second portion 312 on the substrate 10 may at least partially overlap.

In order to show the overlapping first part 311 and second part 312 more clearly, the second part 312 is represented by a thick gray solid line in the drawings of the present application, and the first part 311 is represented by a slightly thinner black solid line, which is not used for Line widths of the first portion 311 and the second portion 312 are defined.

As an example, one end of the second part 312 is connected to the first part 311 , and the other end is connected to the first-type data line 211 .

It can be understood that the first part 311 and the second part 312 are located in different film layers. The first part 311 and the second part 312 may be connected through via holes. FIG. 3 shows that the second part 312 and the data line 21 are also located in different film layers, and the second part 312 and the data line 21 can be connected through via holes.

Exemplarily, the first part 311 may include multiple line segments connected to each other and extending in different directions. The second portion 312 may include one line segment extending in one direction. It can be understood that, since the first part 311 and the second part 312 at least partially overlap, there is a line segment extending in the same direction between the first part 311 and the second part 312, and the line segment extending in the same direction on the substrate 10 The orthographic projections may at least partially overlap. The line segments extending in the same direction and partially overlapping included in the first part 311 and the second part 312 have a certain length, and the lengths of the two line segments may be different.

As an example, the extending direction of the second portion 312 may be the same as the extending direction of the data line 21 . At least part of the line segments of the first portion 311 extend in the same direction as the second portion 312 , and the line segments in the first portion 311 that extend in the same direction as the second portion 312 overlap with the second portion 312 .

For the first connection trace 31 including the first part 311 and the second part 312, it can be understood that it adopts the design method of folded trace, so that the first connection trace 31 can be extended in a limited plane space. of the total length.

As an example, taking the first first connecting wire 31 on the left and the fifth first connecting wire 31 on the left in FIG. 311, its length will be less than the length of the fifth first connecting wire 31 on the left. In the case where the first first connecting wire 31 on the left side includes a first part 311 and a second part 312, that is, the first first connecting wire 31 on the left side adopts a folded wire design, which can extend the left side The total length of the first first connecting wire 31 is such that the lengths of the first left first connecting wire 31 and the fifth left first connecting wire 31 tend to be the same.

As shown in FIG. 1 and FIG. 2 , the first connecting trace 31 may include a first-type connecting trace 31 a and a second-type connecting trace 31 b, the first-type connecting trace 31 a may be designed in a folded trace, and the first-type connecting trace 31 a may adopt a folded trace design. The second-type connection wiring 31b may not adopt the design method of folded wiring. That is to say, the first type of connection trace 31a may include a first portion 311 and a second portion 312 that are at least partially overlapped and connected to each other, and the second type of connection trace 31b may not include an overlapping line segment.

Of course, FIG. 1 and FIG. 2 are only examples, and all the first connection traces 31 may be designed in a folded trace manner.

According to the display substrate provided by the embodiment of the present application, since the first part 311 and the second part 312 are at least partially overlapped, for the first connection wiring 31 including the first part 311 and the second part 312, it adopts a folding route. In this way, the total length of the first connecting trace 31 can be extended in a limited plane space, so that the resistance of the first connecting trace 31 can be adjusted by extending at least part of the total length of the first connecting trace 31 , it is beneficial to make the resistances of the first connecting wires 31 tend to be consistent, so as to reduce the difference in resistance loading (R Loading) of the first connecting wires 31 , and further improve the display uniformity.

Exemplarily, as shown in FIG. 1 , there may be no intersection between the multiple first connection lines 31 .

In some optional embodiments, the lengths of the multiple first connecting lines 31 may tend to be the same. For example, the lengths of the multiple first connecting wires 31 can be the same, so as to further reduce the difference in R Loading among the first connecting wires 31 .

In some optional embodiments, both the second portion 312 and the data line 21 may extend along the second direction Y. As shown in FIG. 3 , the orthographic projection of the second portion 312 on the substrate 10 at least partially overlaps the orthographic projection of the data line 21 connected thereto on the substrate 10 . It can be understood that the signals transmitted by the second part 312 and the data line 21 connected thereto are the same, and the two are overlapped, that is, the second part 312 is prevented from overlapping with other signal lines, so that the second part 312 can be avoided. The coupling between the portion 312 and other signal lines improves signal stability.

The length of the second portion 312 can be much smaller than the length of the data line 21 . In the case where the line width of the second part 312 is the same as the line width of the data line 21, the orthographic projection of the data line 21 connected to the second part 312 on the substrate 10 can cover the space of the second part 312 on the substrate 10. orthographic projection.

Exemplarily, the orthographic projection of the second part 312 on the substrate 10 at least partially overlaps the orthographic projection of the data line 211 connected to it on the substrate 10, and the orthographic projection of the second part 312 on the substrate 10 and the second part 312 connected to the first The orthographic projections of the part 311 on the substrate 10 also at least partially overlap, and the orthographic projections of the first part 311 on the substrate 10 and the orthographic projections of the data lines 21 connected thereto on the substrate 10 may also at least partially overlap.

Under the condition that the line width of the first part 311 and the second part 312 are the same as the line width of the data line 21, the orthographic projection of the data line 21 on the substrate 10 can cover the second part 312 connected by the data line 21 on the substrate. 10 , and the orthographic projection of the data line 21 on the substrate 10 may cover at least part of the orthographic projection of the first portion 311 connected by the data line 21 on the substrate 10 .

In some optional embodiments, please continue to refer to FIG. 3 , the second portion 312 may be located on the side of the data line 21 facing away from the substrate 10 , and the first portion 311 may be located on the side of the second portion 312 facing away from the substrate 10 . That is to say, in the thickness direction of the display substrate, the film layer where the second part 312 is located is located between the film layer where the data line 21 is located and the film layer where the first part 311 is located, and the second part 312 passes through the via hole and the data line 21 and the first part respectively. Part of 311 connection. Since the second part 312 is connected between the first part 311 and the data line 21, by setting the film layer where the second part 312 is located between the film layer where the data line 21 is located and the film layer where the first part 311 is located, the second part 312 can be avoided. The connection via hole between the data line 21 and the first part 311 is too deep, which can reduce the difficulty of process preparation and avoid a larger area occupied by the via hole.

As shown in FIG. 1 , taking the first direction X as the row direction as an example, the second portion 312 of each first connection line 31 and the connection via holes of each first type data line 211 may not be in the same row. The inventor further researched and found that, for example, for each first type of data line 211 connected to the first row of pixel circuits, even if the length of each first connection line 31 is set to be consistent by folding the wiring, that is, the The resistance of each first connection line 31 is set to tend to be consistent, and the path lengths of the data signals required to connect the first row of pixel circuits of each first type of data line 211 on the data line 21 are different, so There are still differences in the voltage drops corresponding to the first-type data lines 211 connected to the pixel circuits in the first row.

In some optional embodiments, the resistivity of the metal in the film layer where the data line 21 is located may be smaller than the resistivity of the metal in the film layer where the second part 312 is located, and the resistivity of the metal in the film layer where the data line 21 is located is smaller than that of the first part 311 The resistivity of the metal in the film layer. That is to say, the resistivity of the metal in the film layer where the data line 21 is located is relatively small, so that when the line widths of the data line 21, the first part 311, and the second part 312 are the same, the resistance of the data line 21 per unit length is less than the unit length. The resistance of the first part 311 of the length is smaller than the resistance of the second part 312 of the unit length. The resistance of the data line 21 is small, so the difference in voltage drop caused by the different path lengths of various data signals passing through the data line 21 can be reduced, thereby further improving display uniformity.

Exemplarily, the data line 21 can be prepared by using a metal material with a lower resistivity, and the first part 311 and the second part 312 can be made by using a metal material with a higher resistivity than the corresponding resistivity of the data line 21 .

As an example, the resistivity of the metal in the film layer where the first part 311 is located may be equal to the resistivity of the metal in the film layer where the second part 312 is located. The first part 311 and the second part 312 may be made of the same metal material. Of course, the resistivity of the metal in the film layer where the first part 311 is located may also be set to be different from the resistivity of the metal in the film layer where the second part 312 is located according to actual conditions.

As an example, the resistance of the second portion 312 per unit length is equal to the resistance of the first portion 311 per unit length. In the case that the resistivity of the metal of the film layer where the first part 311 and the second part 312 are located is equal, the line widths of the two can be equal; or, the resistivity of the metal of the film layer where the first part 311 and the second part 312 are located Under different circumstances, the line widths of the two can be adjusted so that the resistance of the second part 312 per unit length is equal to the resistance of the first part 311 per unit length.

FIG. 4 shows a schematic diagram of a layer structure of a display substrate provided by an embodiment of the present application. FIG. 4 is only used to introduce the film layer structure of the display substrate in the thickness direction, and does not specifically refer to the cross-sectional structure of a specific position of the display substrate. In some optional embodiments, as shown in FIG. 4 , the display substrate further includes a first metal layer M1, a capacitor metal layer MC, a gate metal layer MD, and a second metal layer stacked in a direction away from the substrate 10. M2, the third metal layer M3 and the fourth metal layer M4. An insulating layer may be provided between any adjacent metal layers. The display substrate may include at least two types of transistors, for example, the display substrate may include low temperature polysilicon transistors and oxide transistors. The film layer structure of the display substrate may further include a first semiconductor layer b1 and a second semiconductor layer b2. The first semiconductor layer b1 is located between the first metal layer M1 and the substrate 10 , and an insulating layer is disposed between the first semiconductor layer b1 and the first metal layer M1 . The second semiconductor layer b2 may be located between the capacitor metal layer MC and the gate metal layer MD, and insulation is provided between the second semiconductor layer b2 and the capacitor metal layer MC and between the second semiconductor layer b2 and the second metal layer M2. Floor.

As an example, the data line 21 may be located on the second metal layer M2, the second portion 312 may be located on the third metal layer M3, and at least part of the first portion 311 may be located on the fourth metal layer M4.

As an example, the resistivity of the metal of the second metal layer M2 may be smaller than the resistivity of the metal of the third metal layer M3, and the resistivity of the metal of the second metal layer M2 may be smaller than the resistivity of the metal of the fourth metal layer M4. .

As an example, the resistivity of the metal of the third metal layer M3 may be equal to the resistivity of the metal of the fourth metal layer M4.

In still some optional embodiments, in order to avoid that the path lengths of the data signals passing through the data lines 21 are not the same, the connection vias between the first connection lines 31 and the first type data lines 211 can be arranged in the the same line.

FIG. 5 shows a schematic structural diagram of a display substrate provided by an embodiment of the present application. FIG. 6 shows an exemplary enlarged schematic view of the area Q2 in FIG. 5 . Exemplarily, as shown in FIG. 5 and FIG. 6 , taking the first via hole h1 as an example for connecting each first connection line 31 and each first type data line 211 , each first via hole h1 may be located at the same line, so that the path lengths of each data signal on the data line 21 are the same, thereby avoiding the difference in voltage drop caused by the different path lengths of each data signal on the data line 21, and further improving display uniformity .

In FIG. 5 and FIG. 6 , the first connection line 31 is designed as an example in which folded lines are used. For example, the connecting vias between the first part 311 and the second difference 312 are the second vias h2 , and a plurality of second vias h2 can be dislocated. Fig. 5 and Fig. 6 exemplarily show that, in the second direction Y, the first via hole h1 corresponding to the same first connection line 311 is located on the side of the second via hole h2 away from the bonding area BA, which does not It is not intended to limit this application. For example, in the second direction Y, the first via hole h1 corresponding to the first connection line 311 may be located on a side of the second via hole h2 close to the bonding area BA. Alternatively, in the second direction Y, the first via hole h1 corresponding to part of the first connection line 311 is located on the side of the second via hole h2 away from the binding area BA, and the first via hole h1 corresponding to part of the first connection line 311 It may be located on a side of the second via hole h2 close to the bonding area BA.

Please continue to refer to FIG. 5 or FIG. 6, for the first connection trace 31 adopting the folded trace design, its first part 311 may at least include a first segment 3111, a second segment 3112 and a third segment 3113, the second The segment 3112 is connected between the first segment 3111 and the third segment 3113 , the first segment 3111 is connected to the binding area BA, and the third segment 3113 is connected to the second part 312 . The orthographic projection of the third segment 3113 on the substrate 10 at least partially overlaps the orthographic projection of the second portion 312 on the substrate 10 .

The extension direction of the third segment 3113 may be the same as the extension direction of the second portion 312 . Exemplarily, the extension directions of the third segment 3113, the second portion 312 and the data line 21 are all the same. In the drawings herein, it is shown that the length of the third section 3113 is shorter than the length of the second part 312 , which is not intended to limit the present application.

The extending direction of the third segment 3113 and the extending direction of the first segment 3111 may be the same, and the extending direction of the second segment 3112 intersects with the extending direction of the third segment 3113 . In the second direction Y, the third section 3113 may be located on a side of the second section 3112 close to the binding area BA. Of course, according to actual needs, the third section 3113 can also be arranged on the side of the second section 3112 away from the binding area BA in the second direction Y.

Please refer to FIG. 2 , for the first connection trace 31b that does not adopt the folded trace design, it may at least include a fourth segment 3114 and a fifth segment 3115 connected to each other, and the fourth segment 3114 passes through the third connection wire 33 Connected to the binding area, the fifth segment 3115 is connected to the data line 21. The extending direction of the fourth segment 3114 may be the same as that of the first segment 3111 , and the extending direction of the fifth segment 3115 may be the same as that of the second segment 3112 .

As shown in FIG. 6 , the display substrate further includes a first signal line 41 and a second signal line 42 , and the first signal line 41 and the second signal line 42 transmit constant voltage signals. For example, the first signal line 41 may include a power signal line (PVDD line), and the second signal line 42 may include an initialization signal line (Vref line).

The extending direction of the first signal line 41 may be the same as that of the first segment 3111 , and the extending direction of the second signal line 42 may be the same as that of the second segment 3112 . The orthographic projection of the first segment 3111 on the substrate 10 may at least partially overlap the orthographic projection of the first signal line 41 on the substrate 10, and the orthographic projection of the second segment 3112 on the substrate 10 overlaps with the second signal line 42 The orthographic projections on the substrate 10 at least partially overlap. Since the first signal line 41 and the second signal line 42 transmit fixed signals, the overlapping arrangement of the first section 3111 and the first signal line 41 and the overlapping arrangement of the second section 3112 and the second signal line 42 can reduce the cost of the first section. 3111, the coupling between the second segment 3112 and other signal lines improves the stability of the signal transmitted by the first segment 3111 and the second segment 3112.

Based on the same inventive concept, the present application also provides a display panel. FIG. 7 shows a schematic structural diagram of a display panel provided according to an embodiment of the present application. As shown in FIG. 7 , the display panel 1000 provided in the embodiment of the present application may include the display substrate 100 described in any of the above embodiments. Exemplarily, the display panel 1000 may include a light emitting layer 200 on one side of the display substrate 100 . The light emitting layer 200 may include a plurality of light emitting elements distributed in an array.

The display panel shown in FIG. 7 may be an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel.

Those skilled in the art should understand that, in other implementation manners of the present application, the display panel may also be a micro light emitting diode (Micro LED) display panel, a quantum dot display panel, and the like.

The display panel provided in the embodiment of the present application has the beneficial effects of the display substrate provided in the embodiment of the present application. For details, reference may be made to the specific descriptions of the display substrate in the above embodiments, and details will not be repeated in this embodiment.

The present application also provides a display device, including the display panel provided in the present application. Please refer to FIG. 8 , which is a schematic structural diagram of a display device provided by an embodiment of the present application. The display device 2000 provided in FIG. 8 includes the display panel 1000 provided in any one of the above-mentioned embodiments of the present application. The embodiment in FIG. 8 only takes a mobile phone as an example to illustrate the display device 2000. It can be understood that the display device provided in the embodiment of the present application can be wearable products, computers, televisions, vehicle-mounted display devices and other devices with display functions. The display device is not specifically limited in this application. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application. For details, reference may be made to the specific descriptions of the display panel in the above embodiments, and details will not be described in this embodiment here.

In accordance with the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. This application is to be limited only by the claims, along with their full scope and equivalents.

Claims (11)

1. A display substrate having a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area;

the display substrate includes:

a substrate;

a plurality of data lines on the substrate and in the display area;

a plurality of first connection lines on the substrate and in the display area, the first connection lines transmitting signals from the bonding area to the data lines;

the at least partial strip of the first connection line includes a first portion and a second portion, the second portion is connected between the first portion and the data line, and an orthographic projection of the first portion on the substrate at least partially overlaps with an orthographic projection of the second portion on the substrate.

2. The display substrate of claim 1, wherein an orthographic projection of the second portion on the substrate at least partially overlaps an orthographic projection of a data line connected thereto on the substrate.

3. The display substrate of claim 2, wherein the second portion is located on a side of the data line facing away from the substrate, and the first portion is located on a side of the second portion facing away from the substrate.

4. The display substrate according to claim 3, wherein the display substrate further comprises a first metal layer, a capacitor metal layer, a gate metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in a direction away from the substrate, the data line is located in the second metal layer, the second portion is located in the third metal layer, and at least a partial line segment of the first portion is located in the fourth metal layer.

5. The display substrate according to claim 3, wherein the resistivity of the metal of the film layer in which the data line is located is smaller than the resistivity of the metal of the film layer in which the second portion is located, and the resistivity of the metal of the film layer in which the data line is located is smaller than the resistivity of the metal of the film layer in which the first portion is located.

6. The display substrate according to any one of claims 1 to 4, wherein the resistance per unit length of the second portion is equal to the resistance per unit length of the first portion.

7. A display substrate according to any one of claims 1 to 4, wherein the lengths of the plurality of first connection lines tend to be uniform.

8. The display substrate according to claim 1, wherein the plurality of data lines extend in a column direction and are arranged in a row direction, the plurality of first connection lines are connected with the plurality of data lines in a one-to-one correspondence manner through a plurality of via holes, and the plurality of via holes are located in the same row.

9. The display substrate according to claim 1, wherein the first portion comprises at least a first segment, a second segment and a third segment, the second segment is connected between the first segment and the third segment, the first segment is connected to the bonding region, and the third segment is connected to the second portion;

an orthographic projection of the third segment on the substrate at least partially overlaps with an orthographic projection of the second portion on the substrate;

the display substrate further comprises a first signal line and a second signal line, the first signal line and the second signal line transmit constant voltage signals, the extending direction of the first signal line is the same as that of the first section, and the extending direction of the second signal line is the same as that of the second section;

an orthographic projection of the first segment on the substrate at least partially overlaps an orthographic projection of the first signal line on the substrate, and an orthographic projection of the second segment on the substrate at least partially overlaps an orthographic projection of the second signal line on the substrate.

10. A display panel comprising the display substrate according to any one of claims 1 to 9.

11. A display device characterized by comprising the display panel according to claim 10.

Images