CN115274626A - Anti-irradiation power semiconductor device with isolated voltage division layer - Google Patents
Anti-irradiation power semiconductor device with isolated voltage division layer Download PDFInfo
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- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
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Abstract
The invention discloses a semiconductor device, which comprises an intermediate layer, a voltage division layer and an isolation region, wherein the intermediate layer plays a role in cutting off an electric field, the voltage division layer can play a role in bearing voltage when being irradiated by high-energy particles in a cut-off state, and the isolation region can enable the voltage bearing function of the voltage division layer to be better and avoid dynamic avalanche breakdown of the semiconductor device. The semiconductor device has an anti-radiation characteristic and high reliability.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
Power semiconductor devices are core components in electrical energy conversion applications. In the cosmic space environment and in high-altitude areas, power semiconductor devices are exposed to cosmic ray radiation. Single event failure is the most important mechanism of radiation failure of power semiconductor devices, which is manifested as permanent damage to the power semiconductor device, causing it to be short-circuited or open-circuited. Through the anti-irradiation design of the power semiconductor device, the single event failure resistance of the power semiconductor device can be effectively improved. At present, silicon power semiconductor devices are applied in the cosmos environment and high-altitude areas, and the anti-radiation design of the silicon power semiconductor devices has a certain maturity but still has an improved space. The single event failure problem of the wide bandgap power semiconductor device is serious. For example, silicon carbide power semiconductor devices may degrade or even fail when subjected to particle incidence at reverse bias voltages above 30% of the rated breakdown voltage. The radiation-resistant design of wide bandgap power semiconductor devices also needs to be improved.
Disclosure of Invention
The invention aims to provide an anti-irradiation power semiconductor device which can effectively inhibit single-particle failure compared with a common power semiconductor device.
Referring to fig. 1 to 3, the present invention provides a semiconductor device, a cell structure of which includes: at least one top region 30, a voltage-withstanding layer (20, or 21 and 22), at least one intermediate layer 12, a bottom region 40 and at least one isolation region 50, characterized in that,
the bottom plane of the top region 30 is in direct contact with the top plane of the voltage-withstanding layers (20, or 21 and 22), the bottom plane of the voltage-withstanding layers (20, or 21 and 22) is in direct contact with the top plane of the middle layer 12 and the top plane of the isolation region 50; the intermediate layer 12 and the isolation regions 50 are alternately arranged in the horizontal direction; a lamination layer 11 is arranged between the bottom plane of the middle layer 12 and the isolation region 50 and the top plane of the bottom region 40; the pressure-dividing layer 11 is in direct contact with the intermediate layer 12 or indirectly via at least one connecting zone 13; when the pressure-dividing layer 11 and the intermediate layer 12 are indirectly in contact through the connection region 13, the isolation region 50 divides the connection region 13 into a plurality of regions; at least a part of the bottom plane of the bottom region 40 is in direct contact with the first conductor 1, and at least a part of the top plane of the top region 30 is in direct contact with the second conductor 2;
the top region 30 is composed of a semiconductor material of a first conductivity type and/or a semiconductor material of a second conductivity type;
the voltage-resistant layer (20, or 21 and 22) is composed of a drift region 20 of a first conduction type or is composed of super junction regions (21 and 22), and the super junction regions (21 and 22) are composed of column regions 21 of the first conduction type and column regions 22 of a second conduction type which are alternately arranged in the horizontal direction;
the doping types of the intermediate layer 12, the voltage-dividing layer 11 and the connection region 13 are all first conductivity types; the average doping concentration of the connection region 13 is higher than the average doping concentration of the voltage-dividing layer 11; when the voltage-proof layer (20, or 21 and 22) is composed of a drift region 20 of the first conductivity type, the average doping concentration of the intermediate layer 12 is higher than that of the drift region 20 of the first conductivity type; when the voltage-proof layers (20, or 21 and 22) are composed of super junction regions (21 and 22), the average doping concentration of the intermediate layer 12 is higher than that of the first conductivity type column region 21;
the doping type of the isolation region 50 is a first conductive type or a second conductive type; when the doping type of the isolation region 50 is the first conductivity type, the average doping concentration of the isolation region 50 is lower than the average doping concentration of the intermediate layer 12;
the bottom region 40 is composed of a semiconductor material of a first conductivity type and/or a semiconductor material of a second conductivity type.
Referring to fig. 4-6, the semiconductor device contains PiN diode cells and/or schottky diode cells and/or junction barrier schottky diode cells and/or hybrid PiN schottky diode cells;
the bottom region 40 is composed of a first heavily doped first conductivity type semiconductor region 41, the first conductor 1 is in direct contact with the first heavily doped first conductivity type semiconductor region 41 to form an ohmic contact and is connected to a cathode K;
in the PiN diode cell, the top region 30 is composed of a first heavily doped second conductivity type semiconductor region 31, and the second conductor 2 is in direct contact with the first heavily doped second conductivity type semiconductor region 31 to form an ohmic contact and is connected to the anode a;
in the schottky diode cell, the top region 30 has the same doping type and doping concentration as the first conductive-type drift region 20 or the first conductive-type column region 21, so as to communicate with the first conductive-type drift region 20 or the first conductive-type column region 21 as the same region; the second conductor 2 is in direct contact with the drift region 20 of the first conductivity type or the pillar region 21 of the first conductivity type to form a schottky contact and is connected to the anode a;
in the junction barrier schottky diode cell and the hybrid PiN schottky barrier diode cell, the top region 30 is composed of a first heavily doped second conductive-type semiconductor region 31, the first heavily doped second conductive-type semiconductor region 31 is separated into a plurality of regions by the first conductive-type drift region 20 or the first conductive-type pillar region 21, the second conductor 2 is in direct contact with the first conductive-type drift region 20 or the first conductive-type pillar region 21 to form a schottky contact and is connected to the anode a, and the second conductor 2 is in direct contact with the first heavily doped second conductive-type semiconductor region 31 to form an ohmic contact and is connected to the anode a.
Referring to fig. 7-8, the semiconductor device contains bipolar transistor cells and/or thyristor cells;
the top region 30 is composed of a base region 32 of the first and second conductivity types, the base region 32 of the first and second conductivity types contains at least one semiconductor region 33 of the second heavily doped second conductivity type, the base region 32 of the first and second conductivity types is in direct contact with the at least one semiconductor region 34 of the second heavily doped first conductivity type, the second conductor 2 is in direct contact with the semiconductor region 33 of the second heavily doped second conductivity type to form an ohmic contact and is connected to the base B, and the top plane of the semiconductor region 34 of the second heavily doped first conductivity type is covered with a third conductor 3 to form an ohmic contact and is connected to a low potential electrode E.
In the bipolar transistor cell, the bottom region 40 is formed by a first heavily doped semiconductor region 41 of the first conductivity type, and the first conductor 1 is in direct contact with the first heavily doped semiconductor region 41 of the first conductivity type to form an ohmic contact and is connected to a high potential electrode C;
in the thyristor cell, the bottom region 40 is composed of a collector region 42 of the second conductivity type and a buffer region 43 of the first conductivity type, a bottom plane of the buffer region 43 of the first conductivity type is in direct contact with a top plane of the collector region 42 of the second conductivity type, and a bottom plane of the collector region 42 of the second conductivity type is in direct contact with the first conductor 1 to form an ohmic contact and is connected to the high potential electrode C.
Referring to fig. 9-12, the semiconductor device contains metal-oxide-semiconductor field effect transistor cells and/or insulated gate bipolar transistor cells;
the top region 30 is composed of a base region 35 of the second conductivity type, the base region 35 of the second conductivity type contains at least one semiconductor region 37 of the third heavily doped second conductivity type, the base region 35 of the second conductivity type is directly contacted with at least one semiconductor region 36 of the third heavily doped first conductivity type, and the second conductor 2 is directly contacted with the semiconductor region 37 of the third heavily doped second conductivity type and the semiconductor region 36 of the third heavily doped first conductivity type to form an ohmic contact and is connected to a low potential electrode (S or E);
the cell structure comprises at least one gate structure (61 and 4), the gate structure (61 and 4) is composed of a gate insulating medium layer 61 and a gate conductor region 4, and the gate structure (61 and 4) is a planar gate structure or a groove gate structure; the gate insulating dielectric layer 61 is in direct contact with the drift region 20 of the first conductivity type or the column region 21 of the first conductivity type, and is in direct contact with the base region 35 of the second conductivity type and the semiconductor region 36 of the third heavily doped first conductivity type; the gate conductor region 4 is in direct contact with the gate insulating medium layer 61, and is separated from the drift region 20 of the first conductivity type, the column region 21 of the first conductivity type, the base region 35 of the second conductivity type, and the semiconductor region 36 of the third heavily doped first conductivity type by the gate insulating medium layer 61; the gate conductor region 4 is made of a heavily doped polycrystalline semiconductor material and/or a metal conductor material, the gate conductor region 4 is connected to the gate G;
in the metal-oxide-semiconductor field effect transistor unit cell, the bottom region 40 is composed of a first heavily doped first conductivity type semiconductor region 41, the first conductor 1 is in direct contact with the first heavily doped first conductivity type semiconductor region 41 to form an ohmic contact and is connected to a high potential electrode D;
in the igbt cell, the bottom region 40 is composed of a second conductivity type collector region 42 and a first conductivity type buffer region 43, a bottom plane of the first conductivity type buffer region 43 directly contacts with a top plane of the second conductivity type collector region 42, and a bottom plane of the second conductivity type collector region 42 directly contacts with the first conductor 1 to form an ohmic contact and is connected to the high potential electrode C.
Drawings
FIG. 1 is a diagram of a semiconductor device according to the present invention, in which a voltage-withstanding layer is formed by a drift region;
FIG. 2 shows a semiconductor device of the present invention, wherein the voltage-withstanding layer is formed by a super junction region;
FIG. 3 is a further semiconductor device of the present invention having a connection region;
FIG. 4 is a schematic diagram of a semiconductor device according to the present invention having a PiN diode cell according to FIG. 1;
FIG. 5 is a view showing still another semiconductor device of the present invention including Schottky diode cells according to FIG. 1;
fig. 6 is a view of still another semiconductor device of the present invention including junction barrier schottky diode cells or hybrid PiN schottky diode cells according to fig. 1;
FIG. 7 is a schematic view of the semiconductor device of FIG. 1, including a bipolar junction transistor cell according to the present invention;
FIG. 8 is a view showing still another semiconductor device of the present invention including thyristor cells according to FIG. 1;
FIG. 9 (a) is a view showing a semiconductor device according to FIG. 1, which includes a metal-oxide-semiconductor field effect transistor cell, and which has a planar gate structure;
FIG. 9 (b) is a view showing still another semiconductor device according to FIG. 1, which includes metal-oxide-semiconductor field effect transistor cells, and which employs a trench gate structure;
FIG. 10 (a) is a view showing a semiconductor device according to FIG. 2, which includes a metal-oxide-semiconductor field effect transistor cell, and which has a planar gate structure;
FIG. 10 (b) is a view showing a semiconductor device according to FIG. 2, which includes a metal-oxide-semiconductor field effect transistor cell, and which has a trench gate structure;
FIG. 11 is a view showing still another semiconductor device according to the present invention, which includes IGBT cells, according to FIG. 1;
FIG. 12 is a view showing still another semiconductor device according to FIG. 1, which includes both MOSFET cells and IGBT cells;
FIG. 13 is a current waveform of three junction barrier Schottky diodes during single particle incidence;
FIG. 14 is a graph of the peak temperature waveforms of three junction barrier Schottky diodes during single particle incidence.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Generally, the single-particle failure of the power semiconductor device is mainly single-particle burning and single-particle gate penetration. Both single particle burnout and single particle gate punch-through typically occur when the device is subjected to high energy particle incidence in the blocking state. The single-particle burnout is caused by the fact that high-energy particles generate a large number of electrons and holes to trigger a dynamic avalanche effect in a voltage-resistant layer and finally cause thermal failure, and can occur in any type of power semiconductor devices. The single-particle gate penetration is caused by the fact that after high-energy particles generate a large number of electrons and holes, carrier accumulation and potential elevation of the interface of the gate oxide dielectric layer and a semiconductor are caused, and the breakdown failure of the gate oxide dielectric layer is caused.
Fig. 1 shows a typical structure of a power semiconductor device according to the present invention, in which a drift region (n-drift region 20) of a first conductivity type (n-type) is used as a voltage-withstanding layer. The top region (top region 30) is formed of semiconductor material of the first conductivity type (n-type) and/or semiconductor material of the second conductivity type (p-type) to ensure that the device will normally block, possible configurations of which are given in fig. 4-12. The bottom region (bottom region 40) is composed of a semiconductor material of the first conductivity type (n-type) and/or a semiconductor material of the second conductivity type (p-type), possible configurations of which are given in fig. 4-12. Different combinations of top regions (top regions 30) and bottom regions (bottom regions 40) may represent different types of power semiconductor devices. However, different power semiconductor devices all use the same voltage withstanding structure. Taking fig. 1 as an example, the voltage-resistant structure is a drift region (n-drift region 20) of the first conductivity type (n-type), an n-doped intermediate layer (middle layer 12), an n-doped voltage-dividing layer (n-divider layer 11), and an isolation region (divider region 50). Therefore, fig. 1 covers various types of power semiconductor devices including a drift region (n-drift region 20), an intermediate layer (middle layer 12), a voltage dividing layer (n-divider layer 11), and an isolation region (divider region 50). Similarly, fig. 2 and 3 each also cover various different types of power semiconductor devices.
Compared with the common power semiconductor device, the significant characteristic of fig. 1 is that the voltage division layer (n-divider layer 11) and the isolation region (divider region 50) are provided, and the purpose of the voltage division layer is to improve the single event failure resistance of the power semiconductor device. In the static blocking state, the drift region (n-drift region 20) is depleted under an external bias, and the intermediate layer (n-middle region 12) functions as a cut-off electric field, so that the voltage-dividing layer (n-divider layer 11) does not withstand voltage. The isolation region (divider region 50) divides the intermediate layer (n-middle region 12) into a plurality of regions, and a path of current flowing from one intermediate layer (n-middle region 12) to the other intermediate layer (n-middle region 12) has a certain resistance. When the doping type of the isolation region (divider region 50) is the first conductivity type (n-type), the doping concentration of the isolation region (divider region 50) is not higher than that of the intermediate layer (n-middle region 12), which does not affect the static breakdown voltage. When the doping type of the isolation region (divider region 50) is the second conductivity type (p-type), the doping concentration of the isolation region (divider region 50) should be sufficiently low. Optimally, the built-in potential of the isolation region (divider region 50) and the intermediate layer (n-middle region 12) may be such that the isolation region (divider region 50) is fully depleted. Thus, the isolation region (divider region 50) does not affect the static breakdown voltage.
In the static blocking state, if energetic particles are incident from the top plane of the device to the inside, the energetic particles will generate a large number of electrons and holes inside the drift region (n-drift region 20), where the electrons will move down and the holes will move up.
For a conventional power semiconductor device, the positive charge concentration at the top of the drift region (n-drift region 20) increases due to the increase of the hole concentration, thereby increasing the electric field at the top of the drift region (n-drift region 20) and causing dynamic avalanche breakdown, while the negative charge concentration at the bottom of the drift region (n-drift region 20) increases due to the increase of the electron concentration, and when the doping concentration exceeds the doping concentration, the region at the bottom of the drift region (n-drift region 20) forms a high electric field to cause dynamic avalanche breakdown. When dynamic avalanche breakdown occurs at the top and the bottom of the drift region (n-drift region 20) simultaneously, electrons generated from dynamic avalanche at the top of the drift region (n-drift region 20) further increase the electric field at the bottom of the drift region (n-drift region 20), and holes generated from dynamic avalanche at the bottom of the drift region (n-drift region 20) further increase the electric field at the top of the drift region (n-drift region 20), which causes the dynamic avalanche breakdown to be continuously maintained, and thus single-particle burnout is initiated.
With respect to fig. 1, the doping concentration and thickness of the voltage divider layer (n-divider layer 11) may be the same as or relatively close to the doping concentration and thickness of the drift region (n-drift region 20). When high-energy particles enter the drift region (n-drift region 20) to generate a large number of electrons and holes, the resistance of the drift region (n-drift region 20) can be instantly reduced, and the resistance of the drift region (n-drift region 20) is far lower than that of the voltage division layer (n-divider layer 11), so that the voltage division layer (n-divider layer 11) can also instantly bear the action of an external voltage, the electric field of the drift region (n-drift region 20) is directly reduced, the occurrence of dynamic avalanche breakdown of the drift region (n-drift region 20) is avoided, and the burning of single particles is avoided. In addition, since the isolation region (divider region 50) separates the intermediate layer (n-middle region 12) into a plurality of regions, there is a certain resistance on the path from one intermediate layer (n-middle region 12) to another intermediate layer (n-middle region 12). Thus, the electrons collected by the region of one of the intermediate layers (n-middle region 12) are hardly laterally diffused and directly flow down into the partial pressure layer (n-divider layer 11), which enables a relatively concentrated current to flow through the partial pressure layer (n-divider layer 11), and contributes to the voltage withstand of the partial pressure layer (n-divider layer 11). Without the isolation region (divider region 50), the electrons collected by the intermediate layer (n-middle region 12) would laterally diffuse and then flow down into the voltage-dividing layer (n-divider layer 11), which would increase the cross-sectional area through which current flows through the voltage-dividing layer (n-divider layer 11), and would not be conducive to the voltage-dividing layer (n-divider layer 11) withstanding well.
Further, in the most extreme case (the high energy particles penetrate the whole device), although a large number of electrons and holes are generated in the voltage division layer (n-divider layer 11), at the moment of incidence of the high energy particles, the voltage division layer (n-divider layer 11) does not bear voltage, and there is no high electric field inside, so that dynamic avalanche does not occur in the voltage division layer (n-divider layer 11), but dynamic avalanche occurs in the drift region (n-drift region 20), which means that the resistance of the drift region (n-drift region 20) is still lower than that of the voltage division layer (n-divider layer 11), and the voltage division layer can still play a role of sharing most of the applied voltage.
In addition, if the incident position of the high-energy particle is just above the isolation region (divider region 50), the partial pressure effect of the partial pressure layer (n-divider layer 11) is more prominent. It is worth mentioning that the top of the isolation region (divider region 50) is not lower than the top plane of the intermediate layer (n-middle layer 12) and the bottom is not higher than the top plane of the partial pressure layer (n-divider layer 11) to significantly hinder the lateral diffusion of electrons in the intermediate layer (n-middle layer 12).
In FIG. 2, the main difference from FIG. 1 is that the voltage-withstanding layer uses super junction regions (n-pillar region 21 and p-pillar region 22). Under the same thickness, if the doping concentrations of the column region (n-pillar region 21) and the drift region (n-drift region 20) of the first conductivity type are equal, the super junction region (n-pillar region 21 and p-pillar region 22) adopted by the voltage-resisting layer can have higher breakdown voltage than the drift region (n-drift region 20).
In fig. 3, the main difference from fig. 1 is that there is an n-doped connection region (n-con region 13) between the intermediate layer (n-middle region 12) and the partial pressure layer (n-divider layer 11). The first connection region (n-con region 13) functions as: first, the lattice and stress mismatch between the intermediate layer (n-middle region 12) and the voltage divider layer (n-divider layer 11) is reduced by the doping concentration of the first connection region (n-con region 13) being between the doping concentrations of the intermediate layer (n-middle region 12) and the voltage divider layer (n-divider layer 11); second, it acts as a low resistance to conduct current.
Fig. 4-12 show possible configurations of the top region (top region 30) and the bottom region (bottom region 40) of fig. 1-3. Any one or more of the cell structures shown in fig. 4-12 may be incorporated into the semiconductor device of the present invention.
In fig. 4, the top region (top region 30) is formed by a semiconductor region of the second conductivity type (1 p) which is heavily doped with the first dopant, in comparison with fig. 1 + Region 31) and the bottom region (bottom region 40) is formed by a semiconductor region of the first conductivity type (1 n + region 41) which is heavily doped, forming a PiN diode cell.
In fig. 5, compared to fig. 1, the top region (top region 30) is doped the same as the drift region (n-drift region 20) and thus communicates with the drift region (n-drift region 20) as one region, the bottom region (bottom region 40) is formed by a first heavily doped semiconductor region (1 n + region 41) of the first conductivity type, and the second conductor (2) forms a schottky contact with the drift region (n-drift region 20) to form a schottky diode cell.
In fig. 6, the top region (top region 30) is formed of a plurality of first heavily doped second regions as compared to fig. 1A semiconductor region (1 p) of two conductivity types + 31 region), the bottom region (bottom region 40) being formed by a first heavily doped semiconductor region of the first conductivity type (1 n + region 41), the second conductor (2) forming a schottky contact with the drift region (n-drift region 20) forming a junction barrier schottky diode cell or a hybrid PiN schottky diode cell.
In fig. 7, compared to fig. 1, the top region (top region 30) is formed by the base region of the first second conductivity type (p-b 1 region 32), and further by the semiconductor region of the second heavily doped second conductivity type (2 p + region 33) and the semiconductor region of the second heavily doped first conductivity type (2 n + region 34), and the bottom region (bottom region 40) is formed by the semiconductor region of the first heavily doped first conductivity type (1 n + region 41), forming a bipolar transistor cell.
In fig. 8, the main difference from fig. 7 is that the bottom region (bottom region 40) is composed of a collector region of the second conductivity type (p-collector region 42) and a buffer region of the first conductivity type (n-buffer region 43), forming a thyristor cell.
In fig. 9 (a), compared to fig. 1, the top region (top region 30) is formed by the base region of the second conductivity type (p-b 2 region 35), and further by the semiconductor region of the third heavily doped second conductivity type (3 p + region 37) and the semiconductor region of the third heavily doped first conductivity type (3 n + region 36), and the bottom region (bottom region 40) is formed by the semiconductor region of the first heavily doped first conductivity type (1 n + region 41), including the planar gate structures (61 and 4), forming a mosfet cell.
In fig. 9 (b), the main difference from fig. 9 (a) is that a trench gate structure (61 and 4) is employed.
In FIG. 10 (a), the main difference from FIG. 9 (a) is that the voltage-proof layer is the super junction region (n-pillar region 21 and p-pillar region 22).
In FIG. 10 (b), the main difference from FIG. 9 (b) is that the voltage-proof layer is the super junction region (n-pillar region 21 and p-pillar region 22).
In fig. 11, the main difference from fig. 9 (b) is that the bottom region (bottom region 40) thereof is constituted by a collector region (p-collector region 42) of the second conductivity type and a buffer region (n-buffer region 43) of the first conductivity type, forming an insulated gate bipolar transistor cell.
In fig. 12, the main difference from fig. 11 is that it further includes the mosfet cell shown in fig. 10 (b). Based on the teachings of fig. 12, a semiconductor device having two or more of the cell structures shown in fig. 4-12 can be easily obtained by those skilled in the art. For example, a semiconductor device having both of the cell structures shown in fig. 5 and 9 (a), and the like.
To illustrate the superiority of the present invention, the present invention was compared in simulation with the junction barrier schottky diode structure shown in fig. 6 and a general structure in which the division layer (n-divider layer 11) and the isolation region (divider region 50) are eliminated on the basis of the structure of fig. 6. Important structural parameters and simulation parameters are given here.
The simulation used a plurality of cells (width 328.3 μm) of the structure of fig. 6; siC material is adopted; a semiconductor region (1 p) of a first heavily doped second conductivity type + 31 region) of 0.68 μm and 1 × 10 19 cm -3 (ii) a The thickness and doping concentration of the drift region (n-drift region 20) were 8.8 μm and 9.1 × 10, respectively 15 cm -3 (ii) a The thickness and doping concentration of the intermediate layer (n-middle layer 12) were 50 μm and 1X 10, respectively 19 cm -3 (ii) a The thickness and doping concentration of the partial pressure layer (n-divder layer 11) were 20 μm and 9.1 × 10, respectively 15 cm -3 (ii) a Totally 4 isolation regions (divider region 50) are adopted, the average interval is 55 μm, and the doping concentration is 1 × 10 14 cm -3 (ii) a The thickness and doping concentration of the first heavily doped semiconductor region of the first conductivity type (1 n + region 41) are 130 μm and 1 × 10, respectively 19 cm -3 (ii) a The barrier height of the schottky contact is set to 1.27 eV; the incident heavy ions adopted by the single-particle incident simulation are 70 MeV irradiation energy, the LET value is 37.2 MeV, seeds and cm 2 The Ge particles/mg had an incident depth of 12.98 μm and a track width of 0.48. Mu.m. The common structure is shown in the figureOn the basis of the 6-structure, a voltage division layer (n-divider layer 11) and an isolation region (divider region 50) are cancelled, and other parameters (including single-particle incident simulation parameters) are unchanged.
Fig. 13 and 14 show transient current and peak temperature versus waveform during single particle incidence for the junction barrier schottky diode of the present invention and the conventional junction barrier schottky diode of fig. 6. Fig. 13 and 14 also show the result of eliminating the isolation region (divider region 50) based on the structure of fig. 6, in order to understand the function of the isolation region (divider region 50). From the figure, it can be derived: current peak value after single particle incidence of common junction barrier Schottky diode (I R ) 0.129A, peak temperature: (T) 1698K; after the isolation region (divider region 50) is eliminated on the basis of the structure of figure 6,I R (0.048A) by 63%,T(549K) by 67%; after further addition of the isolation region (divder region 50), i.e. the structure of figure 6,I R (0.033A) was further reduced by 31%,T(388K) is a further reduction of 29%. Obviously, the partial pressure layer (n-divider layer 11) has the capability of improving the resistance to single event burnout, and the isolation region (divider region 50) can further improve the resistance to single event burnout.
In fact, the fundamental reason for the radiation resistance of the present invention is the excellent resistance to dynamic avalanche. Therefore, the semiconductor device of the present invention not only has the radiation-resistant characteristic but also has excellent high-voltage turn-off capability and high-current turn-off capability, and thus the semiconductor device of the present invention cannot be classified as a radiation-resistant semiconductor device only, and should also be classified as a high-reliability semiconductor device.
In the above description of many embodiments of the present invention, the first conductivity type may be considered as n-type, and the second conductivity type may be considered as p-type. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (5)
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