CN115274615A - Small chip interconnection packaging structure based on silicon bridge and manufacturing method thereof - Google Patents

Abstract

The invention relates to a small chip interconnection packaging structure based on a silicon bridge and a manufacturing method thereof. The small chip interconnection packaging structure based on the silicon bridge comprises: the chip comprises a first small chip, a second small chip, a dummy sheet and a silicon bridge chip, wherein the upper surface of the first small chip and the second small chip is provided with a plurality of first lugs and a plurality of second lugs, the height of the first lugs is greater than that of the second lugs, the upper surface of the dummy sheet is provided with a plurality of third lugs, the lower surface of the silicon bridge chip is provided with a plurality of fourth lugs and a plurality of fifth lugs, the dummy sheet is positioned between the first small chip and the second small chip, the first small chip, the second small chip and the dummy sheet are arranged on the lower surface of the silicon bridge chip side by side, the fourth lugs are connected with the second lugs, the fifth lugs are connected with the third lugs, the first small chip, the second small chip, the dummy sheet and the silicon bridge chip are packaged through plastic packaging materials, and the first lugs expose out of a packaging structure. The small chip interconnection packaging structure based on the silicon bridge is low in cost and firm.

Description

A small chip interconnect packaging structure based on a silicon bridge and its manufacturing method

technical field

The invention relates to the technical field of chip packaging, in particular to a small chip interconnect packaging structure based on a silicon bridge and a manufacturing method thereof.

Background technique

With the development of computer technology, chips have penetrated into all walks of life as computing and processing units. In order to reduce the occupation of products by chips, existing chips are becoming more and more miniaturized. Miniaturized chips are difficult to process when packaging integrated circuits. Also getting bigger and bigger. The existing small-chip interconnect packages based on Si bridges can be found to be mainly summarized into the following schemes; one is based on EMIB (Embedded Multi-die Interconnect Bridge, embedded multi-die interconnect bridge) The first is to embed high-density interconnected silicon bridges into the organic substrate, and multiple small chips are interconnected through the silicon bridges; the second is to integrate the silicon bridges into the organic interposer in the form of fan-out. The chip is mounted on the adapter board by flip-chip. The first type of packaging based on the EMIB solution is difficult to process. It is necessary to mount the thin silicon bridge chip by slotting the substrate during the substrate manufacturing process. The mounting difficulty is high and there are risks such as tilt/offset. At the same time In the packaging process, there are also small chip bumps that need to use different sizes to meet the mounting requirements. In the actual processing process, problems such as bump coplanarity are likely to affect soldering, so the overall solution cost is high and the manufacturing process is difficult; second. A fan-out way to integrate the silicon bridge into an organic adapter board is to use the fan-out method to form a silicon bridge to form an adapter board, and then use the flip-chip method to mount the small chip , In this solution, an additional adapter board needs to be manufactured, and the cost will increase. In addition, the adapter board manufactured by fan-out will have small chip offset problems due to the overall adapter board expansion and contraction/chip offset. In addition, there are still some solutions that interconnect the silicon bridge chip with two adjacent small chips through flip-chip, and then use plastic packaging and reconstruction to lead out the connection points on the small chips that need to be fanned out. The interconnection bumps are formed at the end of the wiring. This solution has greatly improved the difficulty of manufacturing, but the bump structure of the silicon bridge chip and the small chip interconnection is extremely fragile. During the debonding process and the final single chip There is a greater risk in the reliability of the product.

Therefore, the existing small chip interconnection packaging method, on the one hand, has high production costs, and on the other hand, the bump structure is extremely fragile and easily damaged.

Contents of the invention

Based on this, it is necessary to provide a silicon bridge-based small-chip interconnect packaging structure and a manufacturing method thereof that can reduce manufacturing costs and build a stronger bump structure.

A small chip interconnection packaging structure based on a silicon bridge, including: a first small chip, a second small chip, a dummy chip and a silicon bridge chip, and a plurality of first bumps and a plurality of first bumps and A plurality of second bumps, the height of the first bump is greater than the height of the second bump, a plurality of third bumps are arranged on the upper surface of the dummy chip, and a plurality of fourth bumps and a plurality of fifth bumps are arranged on the lower surface of the silicon bridge chip. block, the dummy is located between the first small chip and the second small chip, the first small chip, the second small chip, and the dummy are arranged side by side on the lower surface of the silicon bridge chip, the fourth bump is connected to the second bump, and the second bump is connected to the second bump. The five bumps are connected to the third bump, the first small chip, the second small chip, the dummy chip and the silicon bridge chip are encapsulated by the plastic encapsulant, and the first bump exposes the packaging structure.

In one of the embodiments, the cross-sectional area of the third bump is greater than the cross-sectional areas of the first bump and the second bump.

In one embodiment, the third bump is a UBM.

In one of the embodiments, the density and spacing of the plurality of fourth bumps are in one-to-one correspondence with the density and spacing of UBMs at the tops of the plurality of second bumps, and the density and spacing of the plurality of fifth bumps are the same as The density and pitch of the plurality of third bumps correspond one to one.

In one embodiment, the height of the first bump exceeds the sum of the heights of the fourth bump and the second bump by 10 um.

In one embodiment, the cross-sectional area of the third bump is greater than or equal to twice the cross-sectional area of the second bump.

In one embodiment, the small chip interconnection package structure based on the silicon bridge further includes: a thermal conduction layer disposed on the lower surfaces of the first small chip, the second small chip, and the dummy chip.

In one embodiment, the silicon bridge-based small chip interconnection packaging structure further includes: solder ball bumps connected to the first bumps.

A small chip interconnect packaging method based on a silicon bridge, comprising:

Attaching a temporary bonding layer to a temporary carrier with an expansion coefficient similar to that of the chiplet;

An adhesive layer is set on the bottom of the first small chip, dummy chip and second small chip, and the first small chip, dummy chip, and second small chip are placed side by side on the temporary carrier board to complete the mounting;

Curing the adhesive layer at the bottom of the first small chip, dummy chip, and second small chip after mounting;

Welding the second bump on the first chiplet, the second bump on the second chiplet, the fourth bump on the silicon bridge chip, and the third bump on the dummy chip to the fifth bump on the silicon bridge chip;

Fill the gap between the soldered silicon bridge chip and the first small chip, the dummy chip, and the second small chip with an underfill glue;

Bake and cure the underfill;

Plastic encapsulant is used to restructure the structural package of the silicon bridge chip on the temporary carrier board, the first small chip, the dummy chip, and the second small chip to form a packaging package; wherein, the silicon bridge chip and the first small chip, the dummy chip, the second small chip The second small chip is wrapped inside the package;

The upper surface of the package is thinned by wafer thinning until all the first bumps are exposed

Connecting the solder ball bumps to the first bumps through a rewiring process to form an interconnection structure;

The temporary carrier board of the interconnection structure is removed, and the wafer is diced to form a single silicon bridge-based small chip interconnection packaging structure.

In one of the embodiments, the removal of the temporary carrier of the interconnection structure, and dicing by wafer dicing to form a single silicon bridge-based small chip interconnection packaging structure includes: removing the temporary carrier of the interconnection structure Laser or heat removal is used to obtain the semi-finished product of the small-chip interconnection package structure based on the silicon bridge; the semi-finished product of the small-chip interconnection package structure of the silicon bridge is cut by wafer cutting, and a heat conduction layer is added on the bottom surface to form a single chip-based package. Small chip interconnect package structure of silicon bridge.

The above silicon bridge-based small chip interconnection packaging structure and its manufacturing method connect the first small chip and the first small chip on the silicon bridge chip through a dummy chip, and can form interconnection with the silicon bridge chip through a bump with a large cross-sectional area. Enhance the strength of the overall packaging structure, and provide a capillary traction platform for the underfill process, which is conducive to filling the underfill between chips; at the same time, by adding large bumps on the silicon bridge chip to form interconnections with small chips and dummy chips, increasing The contact area between the silicon bridge chip and other chips is enlarged, and the stress originally concentrated on the small bump of the silicon bridge is transferred to the large bump with no actual electrical performance.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the traditional technology. Obviously, the accompanying drawings in the following description are only the present invention For some embodiments of the application, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a structural schematic diagram of a small chip interconnection packaging structure based on a silicon bridge in an embodiment;

Fig. 2 is a structural schematic diagram of a small chip in an embodiment;

Fig. 3 is a schematic structural view of a dummy chip and a silicon bridge chip in an embodiment;

4 is a schematic diagram of the bumps of the dummy chip and the silicon bridge chip in an embodiment;

Fig. 5 is a schematic diagram of the bonding structure of the first chiplet, the second chiplet, the dummy sheet and the temporary carrier in an embodiment;

Fig. 6 is a schematic structural view of the first small chip, the second small chip, the dummy chip and the silicon bridge chip filled with underfill glue in an embodiment;

7 is a top view of the connection between the first chiplet, the second chiplet, the dummy chip and the silicon bridge chip in an embodiment;

FIG. 8 is a schematic structural diagram of the thinned part of the packaging package in an embodiment.

Explanation of reference signs:

100-first small chip; 101-second small chip; 102-dummy chip; 103-silicon bridge chip; 104-thermal conduction layer; 200-first bump; 201-second bump; 202-fourth bump ;203-fifth bump; 204-third bump; 205-solder ball bump; 300-adhesive layer; ;401-Temporary bonding layer.

Detailed ways

In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the application are given in the drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance could be termed a second resistance, and, similarly, a second resistance could be termed a first resistance, without departing from the scope of the present application. Both the first resistance and the second resistance are resistances, but they are not the same resistance.

It can be understood that the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have the transmission of electric signals or data between each other.

When used herein, the singular forms "a", "an" and "the/the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising/comprising" or "having" etc. specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more The possibility of other features, integers, steps, operations, components, parts or combinations thereof. Meanwhile, the term "and/or" used in this specification includes any and all combinations of the related listed items.

In the prior art, the silicon bridge is first mounted or fixed on the substrate or the adapter board. The silicon bridge chip has a high density of bumps (soldering points), so it requires high mounting accuracy. After the assembly is completed, the substrate/adapter board that is loaded needs to be processed in the follow-up process, which poses a great challenge to its position accuracy; secondly, the small chips that are mounted need to be processed with bumps, and in order to be compatible with larger bumps For the application of dot pitch, it is necessary to manufacture bumps of different sizes on the same small chip. Due to the different relationship between the electroplating current density, it is difficult to keep the ball coplanarity of the bumps consistent. Based on these shortcomings, the present invention considers fixing small chips on temporary carrier boards, attaching non-functional dummy chips between small chips, and forming a large UBM pad on it to interconnect with the silicon bridge. Two kinds of small bumps are used to interconnect with different chiplets and dummy chips; bumps with different heights can be manufactured on the chiplets (the silicon bridge interconnection area does not need to be long, if it is longer, the coplanarity must be kept the same), and the bumps The bumps in the area with a large point spacing do not need to control the coplanarity, but the minimum height of the higher bumps needs to be controlled to ensure that the subsequent thinning of the plastic package can be fully exposed; after the placement is completed, the underfill and plastic package are used to stabilize the whole Structure; the plastic package is thinned to expose the connection points, and then the RDL (Re-distributed layer, redistribution layer) interconnection is performed, and finally the welding bumps are electroplated; the temporary bonding layer can be removed by laser/heat, etc., for the overall stability Add a layer of heat conduction layer on the back of the chip for better performance and heat dissipation.

In one embodiment, as shown in FIGS. 1-3 , a silicon bridge-based chiplet interconnection packaging structure is provided, which includes: a first chiplet 100, a second chiplet 101, a dummy chip 102, and a silicon bridge In the chip 103, a plurality of first bumps 200 and a plurality of second bumps 201 are arranged on the upper surfaces of the first small chip 100 and the second small chip 101, the height of the first bumps 200 is greater than the height of the second bumps 201, assuming A plurality of third bumps 204 are arranged on the upper surface of the sheet 102, a plurality of fourth bumps 202 and a plurality of fifth bumps 203 are arranged on the lower surface of the silicon bridge chip 103, and the dummy sheet 102 is located on the first small chip 100, the second small chip 101, the first small chip 100, the second small chip 101, and the dummy 102 are arranged side by side on the lower surface of the silicon bridge chip 103, the fourth bump 202 is connected to the second bump 201, the fifth bump 203 is connected to the third The bumps 204 are connected, and the first chiplet 100 , the second chiplet 101 , the dummy chip 102 and the silicon bridge chip 103 are encapsulated by the molding compound 302 , and the first bump 200 exposes the packaging structure. Wherein, the dummy chip 102 is a dummy chip. The chiplets can be microchips such as image processing chips and voice chips, and the types of chips are not limited here.

Wherein, the cross-sectional area of the third bump 204 is larger than the cross-sectional area of the first bump 200 and the second bump 201 . In this embodiment, the bump can be made of a conductive material similar to copper.

In this embodiment, the first small chip and the first small chip are fixed on the silicon bridge chip through a dummy chip, and the interconnection between the bump and the silicon bridge chip with a large cross-sectional area can be formed to enhance the strength of the overall package structure. And it provides a capillary traction platform for the underfill process, which is conducive to filling the underfill between chips; at the same time, by adding large bumps on the silicon bridge chip to form interconnections with small chips and dummy chips, it increases the size of the silicon bridge chip and The contact area of other chips, and transfer the stress that would have been concentrated on the small bumps of the silicon bridge to the large bumps with no actual electrical performance.

In one embodiment, the third bump 204 is a UBM. Among them, UBM (Under Bump Metallurgy, under the bump metal layer), is the metallization transition layer between the chip pad and the bump, mainly plays the role of adhesion and diffusion barrier, it is usually composed of adhesion layer, diffusion barrier Layer and wetting layer and other multi-layer metal film. At present, sputtering, evaporation, electroless plating, electroplating and other methods are usually used to form UBM, so the production of UBM layer is one of the key processes in bump production, and its quality will directly affect the quality of bumps and the finished products of flip chip welding. rate and post-package bump reliability.

In one of the embodiments, the density and spacing of the plurality of fourth bumps 202 correspond one-to-one to the density and spacing of UBMs at the tops of the plurality of second bumps 201 , and the density and spacing of the plurality of fifth bumps 203 The pitch and the density correspond one-to-one to the density and pitch of the plurality of third bumps 204 . Wherein, the number of the fourth bump on the silicon bridge chip is the same as the number of the second bump, and the fourth bump and the second bump are welded in one-to-one correspondence; the number of the fifth bump and the third bump on the silicon bridge chip Similarly, the fifth bump and the third bump are welded in one-to-one correspondence.

In one embodiment, the height of the first bump 200 exceeds the sum of the heights of the fourth bump 202 and the second bump 201 by 10 um. In this embodiment, the height of the first bump 200 exceeds the sum of the heights of the fourth bump 202 and the second bump 201 by 10 um to ensure the subsequent process.

In one embodiment, as shown in FIG. 4 , the cross-sectional area of the third bump 204 is greater than or equal to twice the cross-sectional area of the second bump 201 . In this embodiment, the third bump is a large-area bump, and the silicon bridge chip is interconnected with the small chip and the dummy chip through the large-area bump, which increases the contact area between the silicon bridge chip and other chips, and The stress originally concentrated on the small bumps of the silicon bridge is transferred to the large bumps without actual electrical performance, which improves the compressive performance of the small chip interconnection packaging structure based on the silicon bridge.

In one embodiment, as shown in FIG. 1 , the silicon bridge-based chiplet interconnection packaging structure further includes: a heat conduction layer 104 disposed on the lower surfaces of the first chiplet 100 , the second chiplet 101 , and the dummy sheet 102 . Wherein, the heat conduction layer may be a copper layer. In this embodiment, a heat conduction layer is added on the back of the small chip to increase heat dissipation and structural strength of the overall packaging structure.

In one embodiment, as shown in FIG. 1 , the silicon bridge-based small chip interconnection packaging structure further includes: solder ball bumps 205 connected to the first bumps 200 .

In one embodiment, as shown in Fig. 1, Fig. 5-Fig. 8, a silicon bridge-based small chip interconnect packaging method is provided, comprising the following steps:

a1, attaching a layer of temporary bonding layer 401 on a temporary carrier 400 with an expansion coefficient similar to that of the small chip; wherein, the bonding layer is a photosensitive bonding layer or a thermal bonding layer, and the material and attachment method are not limited;

a2, set the adhesive layer 300 at the bottom of the first small chip, dummy, and second small chip, and mount the first small chip, dummy, and second small chip side by side with the temporary carrier 400; as shown in Figure 5, The first small chip, the dummy, and the second small chip are fixed on the temporary carrier 400 through an adhesive layer;

a3, curing the adhesive layer 300 at the bottom of the first small chip, the dummy chip, and the second small chip after mounting;

a4, welding the second bump on the first chiplet, the second bump on the second chiplet, the fourth bump on the silicon bridge chip, and the third bump on the dummy chip to the fifth bump on the silicon bridge chip;

a5, fill the gap between the soldered silicon bridge chip and the first small chip, dummy, and second small chip; wherein, as shown in Figure 6 and Figure 7, the gap between the small chip and the silicon bridge Filling with the underfill 301, because the dummy 102 is added under the silicon bridge, the capillary phenomenon of the underfill 301 will be more obvious, and the underfill 301 can smoothly penetrate into the silicon bridge chip, the first small chip, and the dummy , The gap between the second small chip, after baking, the silicon bridge chip can be well fixed with the first small chip, dummy chip, and the second small chip;

a6, bake and cure the underfill glue;

a7, use the plastic encapsulant 302 to restructure the structural package of the silicon bridge chip on the temporary carrier 400, the first small chip, the dummy chip, and the second small chip to form a packaging package; wherein, the silicon bridge chip and the first small chip, The dummy chip and the second small chip are wrapped inside the package;

a8, thinning the upper surface of the package by wafer thinning until all the first bumps are exposed;

a9, connecting the solder ball bump 205 to the first bump by a rewiring process to form an interconnection structure;

a10, remove the temporary carrier board of the interconnection structure, and cut it by wafer dicing to form a single small chip interconnection package structure based on the silicon bridge. Wherein, the temporary bonding layer can be removed by means of laser/heat, etc., so as to remove the temporary carrier board of the interconnection structure.

Among them, preparations need to be made before small chip interconnection packaging: use electroplating on the first small chip 100 and second small chip 101 that need to be interconnected to grow into a first bump 200 of sufficient length, the length of the first bump 200 is generally It needs to exceed the sum of the heights of the fourth bump 202, the second bump 201 and the silicon bridge chip by more than 10um to ensure the progress of the subsequent manufacturing process; in the area where the first chiplet and the second chiplet need to be interconnected, it is formed in the form of UBM Welding layer and stress absorbing layer; the dummy sheet 102 does not contain functions, and has a large-sized third bump 204 on it, and the cross-sectional size of the third bump 204 is more than twice the cross-sectional size of the UBM in the small chip interconnection area; the silicon bridge Chip 103 is a high-density interconnection chip connected to adjacent small chips (100, 101), on which there is a fourth bump 202 with high density and small spacing in the corresponding small chip area, and its density and spacing are the same as those of small chips (100, 101 ) correspond one-to-one to the second bumps 201 , and the fifth bumps 203 with large spacing correspond to the third bumps 204 on the dummy 102 .

Specifically, as shown in Figure 8, after using plastic encapsulant to package and reconstruct the structure of the silicon bridge chip on the temporary carrier board, the first small chip, the dummy chip, and the second small chip to form a package, the wafer is reduced In a thinning manner, the upper surface of the package is thinned until all the first bumps are exposed. Wherein, the thinned part 303 is located on the upper part of the packaging package, and the wafer packaging package will have a large warp after the curing is completed. The silicon bridge 103 and the molding compound 302 are thinned by using the wafer thinning method, and the interconnection bumps 200 exposed for subsequent rewiring process.

In one of the embodiments, the removal of the temporary carrier of the interconnection structure, and dicing by wafer dicing to form a single silicon bridge-based small chip interconnection packaging structure includes: removing the temporary carrier of the interconnection structure Laser or heat removal is used to obtain the semi-finished product of the small-chip interconnection package structure based on the silicon bridge; the semi-finished product of the small-chip interconnection package structure of the silicon bridge is cut by wafer cutting, and a heat conduction layer is added on the bottom surface to form a single chip-based package. Small chip interconnect package structure of silicon bridge. In this embodiment, by adding a heat conduction layer at the bottom of the small chip, the heat dissipation and structural strength of the overall package structure can be increased.

For the specific limitations of the silicon bridge-based chiplet interconnection packaging method, please refer to the above-mentioned limitation of the silicon bridge-based chiplet interconnection packaging structure, which will not be repeated here.

In the description of this specification, descriptions referring to the terms "some embodiments", "other embodiments", "ideal embodiments" and the like mean that specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in this specification. In at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A chiplet interconnect package structure based on silicon bridges, comprising: the chip packaging structure comprises a first small chip (100), a second small chip (101), a dummy wafer (102) and a silicon bridge chip (103), wherein the upper surfaces of the first small chip (100) and the second small chip (101) are provided with a plurality of first bumps (200) and a plurality of second bumps (201), the height of the first bumps (200) is larger than that of the second bumps (201), the upper surface of the dummy wafer (102) is provided with a plurality of third bumps (204), the lower surface of the silicon bridge chip (103) is provided with a plurality of fourth bumps (202) and a plurality of fifth bumps (203), the dummy wafer (102) is positioned between the first small chip (100) and the second small chip (101), the first small chip (100), the second small chip (101) and the dummy wafer (102) are arranged on the lower surface of the silicon bridge chip (103) side by side, the fourth bumps (202) are connected with the second bumps (201), the fifth bumps (203) are connected with the third bumps (204), the first small chip (100), the second small chip (101), the dummy wafer (102) and the silicon bridge chip (103) are packaged through a first plastic packaging structure (302), and the dummy wafer (200) is exposed out of the silicon bridge chip.

2. The silicon bridge-based chiplet interconnection package structure of claim 1 wherein the third bump (204) has a cross-sectional area greater than the cross-sectional areas of the first and second bumps (200, 201).

3. The silicon bridge-based chiplet interconnection package structure of claim 1 wherein the third bump (204) is a UBM.

4. The silicon bridge-based chiplet interconnection package structure of claim 3, wherein the density and spacing of the fourth plurality of bumps (202) corresponds one-to-one with the density and spacing of the UBMs of the second plurality of bumps (201), and the density and spacing of the fifth plurality of bumps (203) corresponds one-to-one with the density and spacing of the third plurality of bumps (204).

5. The silicon bridge based chiplet interconnection package structure of claim 1 wherein the height of the first bump (200) exceeds the sum of the heights of the fourth bump (202) and the second bump (201) by 10um.

6. The silicon bridge based chiplet interconnect package structure of claim 1 wherein the third bump (204) has a cross-sectional area greater than or equal to 2 times the cross-sectional area of the second bump (201).

7. The silicon bridge-based chiplet interconnect package structure of claim 1 further comprising: and the heat conduction layer (104) is arranged on the lower surfaces of the first small chip (100), the second small chip (101) and the dummy sheet (102).

8. The silicon bridge-based chiplet interconnect package structure of claim 1 further comprising: and solder bump 205 connected to the first bump 200.

9. A method for interconnecting and packaging small chips based on silicon bridges is characterized by comprising the following steps:

attaching a temporary bonding layer on a temporary carrier plate with expansion coefficient similar to that of the small chip;

bonding layers are arranged at the bottoms of the first small chip, the dummy chip and the second small chip, and the first small chip, the dummy chip and the second small chip are attached to the temporary carrier plate side by side;

curing the bonding layers at the bottoms of the first small chip, the dummy wafer and the second small chip after the mounting is finished;

respectively welding a second bump on the first small chip and the second small chip with a fourth bump on the silicon bridge chip and a third bump on the dummy wafer with a fifth bump on the silicon bridge chip;

filling underfill in gaps among the welded silicon bridge chip, the first small chip, the dummy wafer and the second small chip;

baking and curing the underfill;

packaging and reconstructing the structures of the silicon bridge chip, the first small chip, the dummy chip and the second small chip on the temporary carrier plate by adopting a plastic package material to form a packaging bag; the silicon bridge chip, the first small chip, the dummy chip and the second small chip are wrapped in the packaging bag;

thinning the upper surface of the packaging bag by adopting a wafer thinning mode until the first bump is completely exposed;

connecting the solder ball salient points with the first bumps by adopting a rewiring process to form an interconnection structure;

and the temporary carrier plate of the interconnection structure is detached, and a wafer cutting mode is adopted for cutting to form a single small chip interconnection packaging structure based on the silicon bridge.

10. The method of claim 9, wherein the removing the temporary carrier plate of the interconnect structure and dicing the temporary carrier plate by wafer dicing to form a single silicon bridge-based chiplet interconnect package structure comprises:

the temporary carrier plate of the interconnection structure is removed in a laser or thermal mode, and a semi-finished product of the small chip interconnection packaging structure based on the silicon bridge is obtained;

and cutting the semi-finished product of the small chip interconnection packaging structure of the silicon bridge in a wafer cutting mode, and adding a heat conduction layer on the bottom surface to form a single small chip interconnection packaging structure based on the silicon bridge.

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