CN115274460B - Semiconductor structure, manufacturing method thereof and wafer bonding method - Google Patents
Semiconductor structure, manufacturing method thereof and wafer bonding method Download PDFInfo
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- CN115274460B CN115274460B CN202110484058.8A CN202110484058A CN115274460B CN 115274460 B CN115274460 B CN 115274460B CN 202110484058 A CN202110484058 A CN 202110484058A CN 115274460 B CN115274460 B CN 115274460B
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 abstract description 51
- 229910052751 metal Inorganic materials 0.000 abstract description 51
- 230000000694 effects Effects 0.000 abstract description 9
- 235000012431 wafers Nutrition 0.000 description 46
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000001125 extrusion Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present disclosure provides a semiconductor structure, a method for manufacturing the same and a wafer bonding method. The semiconductor structure comprises a substrate, a conductive connecting line and a conductive contact pad, wherein the conductive connecting line is positioned in the substrate, a first surface of the conductive contact pad is connected with the conductive connecting line, a second surface of the conductive contact pad is provided with a first area and a second area, the first area corresponds to the conductive connecting line in position, the second area is an area, except for the first area, of the second surface of the conductive contact pad, the first area is provided with a first roughness, the second area is provided with a second roughness, and the first roughness is larger than the second roughness. The embodiment of the disclosure can improve the uniformity of metal bonding in the wafer bonding process and optimize the wafer bonding effect.
Description
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technology, and in particular, to a semiconductor structure capable of improving wafer bonding effect, a manufacturing method thereof, and a wafer bonding method.
Background
Bonding between wafers is achieved by metal conductive contact pads (bonding pads) on the wafers being interconnected. The metal conductive contact pad is usually formed after the conductive connection is manufactured, and if the height of the metal conductive contact pad is lower than the surface of the substrate during the manufacturing process, connection failure is caused to open a circuit, and if the height of the metal conductive contact pad is higher than the surface of the substrate, metal extrusion occurs during the bonding process of the two metal conductive contact pads, so that bonding separation is caused or short circuit occurs to an adjacent circuit.
In addition, in the bonding process, because the metal amounts corresponding to the areas of the conductive contact pad are different (the metal amount corresponding to the conductive connection line area is large, the metal layer is thick, the metal amount of other areas is small, and the metal layer is thin), under the same bonding strength, the metal extrusion amounts (metal expansion) of the areas are different, so that the metal bonding effect of the different areas on the surface of the conductive contact pad is uneven, and the bonding strength and the conductivity are affected.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure provides a semiconductor structure, a method for manufacturing the same and a wafer bonding method for solving the problem that a metal conductive contact pad is easy to have connection failure in a bonding process at least to a certain extent.
According to a first aspect of the disclosure, a semiconductor structure is provided, and the semiconductor structure comprises a substrate, a conductive connecting wire and a conductive contact pad, wherein the conductive connecting wire is located in the substrate, a first surface of the conductive contact pad is connected with the conductive connecting wire, a second surface of the conductive contact pad is provided with a first area and a second area, the first area corresponds to the conductive connecting wire, the second area is an area, except for the first area, of the second surface of the conductive contact pad, the first area is provided with a first roughness, the second area is provided with a second roughness, and the first roughness is larger than the second roughness.
In one exemplary embodiment of the present disclosure, the first region includes a plurality of first recesses having a first depth and the second region includes a plurality of second recesses having a second depth, the second depth being greater than the first depth.
In an exemplary embodiment of the present disclosure, the bottom of the first recess includes a plane, an arc surface, and an included angle, and the bottom of the second recess includes a plane, an arc surface, and an included angle, and the bottom of the first recess is not exactly the same as the bottom of the second recess.
In one exemplary embodiment of the present disclosure, the first recess has a top view shape comprising a circle, an ellipse, a parallelogram, and the second recess has a top view shape comprising a circle, an ellipse, a parallelogram, the top view shape of the first recess being the same as the top view shape of the second recess, or the top view shape of the first recess being different from the top view shape of the second recess.
In one exemplary embodiment of the present disclosure, the second region includes a third recess located at an interface of the conductive contact pad and the substrate, the third recess having a third depth, the third depth being greater than the second depth.
In an exemplary embodiment of the present disclosure, the difference between the first roughness and the second roughness is greater than 5nm.
In an exemplary embodiment of the present disclosure, the second roughness is less than 1nm.
According to a second aspect of the present disclosure, a wafer bonding method is provided, including providing a first wafer, the first wafer including a first substrate, a first conductive connection line, and a first conductive contact pad, the first conductive connection line being located in the first substrate, a first surface of the first conductive contact pad being connected to the first conductive connection line, a second surface of the first conductive contact pad being provided with a first region and a second region, the first region corresponding to a position of the first conductive connection line, the second region being a region of the second surface of the first conductive contact pad other than the first region, the first region having a first roughness, the second region having a second roughness, the first roughness being greater than the second roughness, providing a second wafer, the second wafer including a second substrate, a second conductive connection line, a second conductive contact pad, the second conductive connection line being located in the second wafer, the second surface of the second conductive contact pad being connected to the second region, the second region having a second roughness, the second region corresponding to a third conductive connection line, the second region having a second roughness, the second region corresponding to a fourth region, the second contact pad, the second region having a second contact region, and a fourth contact region, the second contact region having a second contact region, and the fourth contact region.
In one exemplary embodiment of the present disclosure, the first region has a first recess with a first protrusion between two adjacent first recesses, the second region has a second recess with a second protrusion between two adjacent second recesses, the third region has a third recess with a third protrusion between two adjacent third recesses, the fourth region has a fourth recess with a fourth protrusion between two adjacent fourth recesses, the controlling the first conductive contact pad to contact the first region and the third region of the second conductive contact pad, the second region and the fourth region to contact includes aligning the first protrusion with the third recess center, the third protrusion with the first recess center, the second protrusion with the fourth recess center, and the fourth protrusion with the second recess center during the contacting of the first region and the third region.
In an exemplary embodiment of the present disclosure, the shape and size of the first recess corresponds to the shape and size of the third protrusion, the shape and size of the second recess corresponds to the shape and size of the fourth protrusion, and the shape and size of the third recess corresponds to the shape and size of the first protrusion.
According to a third aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, including providing a substrate, wherein a conductive connection line is formed in the substrate, forming a conductive contact pad on the surface of the conductive connection line, wherein the cross-sectional area of the conductive contact pad is larger than that of the conductive connection line, and etching a position, corresponding to the conductive connection line, in the conductive contact pad to form a first region, and the first region has a first roughness.
In one exemplary embodiment of the present disclosure, the etching the locations of the conductive contact pads corresponding to the conductive wires to form a first region includes etching the locations of the conductive contact pads corresponding to the conductive wires to form a plurality of first recesses, the first recesses having a first depth.
In one exemplary embodiment of the present disclosure, etching the conductive contact pad at a location other than the first region to form a second region having a second roughness that is less than the first roughness is further included.
In one exemplary embodiment of the present disclosure, the etching the locations of the conductive contact pads other than the first region to form a second region includes etching the locations of the conductive contact pads other than the first region to form a plurality of second recesses, the second recesses having a second depth.
In one exemplary embodiment of the present disclosure, the interface of the conductive contact pad and the substrate is etched to form a plurality of third recesses having a third depth.
According to the embodiment of the disclosure, the larger roughness is arranged at the position of the surface of the conductive contact pad corresponding to the conductive connecting wire, so that a larger accommodating space can be provided for extruded metal at the position corresponding to the conductive connecting wire, the problem of non-uniform bonding of the metal on the surface of the conductive contact pad in the bonding process in the related technology is effectively solved, and the wafer bonding effect is effectively optimized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 2A to 2E are schematic views of a second surface of the conductive contact pad according to the embodiments of the disclosure.
Fig. 3 is a flow chart of a method for fabricating the semiconductor structure shown in fig. 1 or fig. 2A to fig. 2E.
Fig. 4 is a flowchart of a wafer bonding method provided in an exemplary embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a first wafer and a second wafer before bonding in an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a first wafer and a second wafer before bonding according to another embodiment of the disclosure.
Reference numerals:
1. Substrate and method for manufacturing the same
2. Conductive wire
3. Conductive contact pad
31. First region
32. Second region
311. First recess
321. Second recess
322. Third recess
312. Fourth recess
51. First wafer
510. A first substrate
511. First conductive connection line
512. First conductive contact pad
513. First region
514. Second region
5131. First recess
5141. Second recess
52. Second wafer
520. A second substrate
521. Second conductive wire
522. Second conductive contact pad
523. Third region
524. Fourth region
5231. Third recess
5241. Fourth recess
61. First wafer
610. A first substrate
611. First conductive connection line
612. First conductive contact pad
613. First region
614. Second region
6131. First recess
6141. Second recess
62. Second wafer
620. A second substrate
621. Second conductive wire
622. Second conductive contact pad
623. Third region
624. Fourth region
6231. Third recess
6241. Fourth recess
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
Referring to fig. 1, a semiconductor structure 100 may include:
A substrate 1;
a conductive wire 2, the conductive wire 2 being located in the substrate 1;
The conductive contact pad 3, the first surface of the conductive contact pad 3 is connected with the conductive connecting wire 2, the second surface of the conductive contact pad 3 is provided with a first area 31 and a second area 32, the first area 31 corresponds to the conductive connecting wire 2 in position, the second area 32 is an area of the second surface of the conductive contact pad 3 except the first area 31, the first area 31 has a first roughness, the second area 32 has a second roughness, and the first roughness is larger than the second roughness.
In some embodiments, the first roughness may be greater than 20nm, for example, and in other embodiments, the difference between the first roughness and the second roughness may be greater than 5nm, for example.
In order to realize good contact between conductive contact pads in the bonding process, the related technology generally needs to control the height of metal to be 1-5 nm different from the surface of a substrate, so that the control difficulty is very high, and the influence on the production cost and the production yield is larger. In addition, since the amount of metal on the conductive contact pad 3 corresponding to the conductive wire 2 is larger than that of other regions, the expansion coefficient of metal at the position is also larger than that of other regions during the bonding process, resulting in uneven fusion degree of metal grains of the two conductive contact pads for bonding.
Through setting up the great first region of roughness in the surface of conductive contact pad 3 and the position that conductive connection line 2 corresponds, set up the less second region of roughness in other positions, can provide bigger accommodation space for the metal expansion of conductive connection line 2 corresponding region, and then solve the inhomogeneous problem of metal grain fusion in the bonding process, can avoid simultaneously the open circuit problem that appears easily and the short circuit problem that the metal extrusion leads to in the bonding process.
In the disclosed embodiments, the substrate 1 may include, but is not limited to, a silicon substrate. For example, the conductive line 2 may be located in a dielectric layer, and the entire semiconductor structure including the dielectric layer is referred to as a substrate 1, and in addition, all or part of other semiconductor structures (such as other conductive lines or active regions of transistors) may be included in the substrate 1, and since the substrate 1 is not described with emphasis, the disclosure will not be described herein. The conductive connection line 2 may be, for example, a through silicon via. The materials of the conductive wires 2 and the conductive contact pads 3 may include, for example, metals such as copper and tungsten. The outer insulating material of the conductive wire 2 is, for example, an insulating material such as silicon oxide, silicon nitride, etc., and the cross section of the conductive wire 2 is, for example, circular, elliptical or rectangular.
In the embodiment shown in fig. 1, after the general conductive contact pad is manufactured, the surface of the conductive contact pad may be etched in regions to manufacture first regions 31 and second regions 32 of different roughness, some embodiments of the present disclosure below.
Fig. 2A to 2E are schematic views of the second surface of the conductive contact pad 3 according to the embodiment of the disclosure.
Referring to fig. 2A and 2B, in one embodiment, the first region 31 of the second face of the conductive contact pad 3 is provided with a plurality of recesses 311, the second region 32 is provided with a plurality of second recesses 321, the first recesses 311 have a first depth, the second recesses 321 have a second depth, and the second depth is less than the first depth.
In the embodiment shown in fig. 2A, the first recess 311 and the second recess 321 are each circular or elliptical, or the like, with a curved edge.
In the embodiment shown in fig. 2B, the first recess 311 and the second recess 321 are each rectangular, diamond-shaped, or other parallelogram.
In the embodiment shown in fig. 2A and 2B, the conductive line 2 has a circular cross section, so that the first region 31 has a circular shape, and the second region 32 surrounds the first region 31. In other embodiments, the cross-section of the conductive wire 2 may be elliptical, rectangular, etc., and the first region 31 and the cross-section of the conductive wire 2 are the same, and the second region 32 surrounds the first region 31.
In the embodiment of the present disclosure, the bottom form of the first recess 311 includes a plane, an arc surface, and an included angle, and the bottom form of the second recess 321 includes a plane, an arc surface, and an included angle, and the bottom form of the first recess 311 may be the same as or different from the bottom form of the second recess 321.
In other embodiments of the present disclosure, more kinds of recesses may be further provided, for example, the first recess 311 and the second recess 321 may be implemented by other forms such as grooves, which are not listed herein.
In some embodiments, the second region 32 may be, for example, a flat region, i.e., the second roughness may be less than 1nm. The processing accuracy (without maintaining the original error limit of 1 to 5 nm) in the CMP processing of the second region 32 can be reduced, and at this time, the roughness of the first region 31 can be still made larger than that of the second region 32.
In the embodiment shown in fig. 2C, the second region 32 is not recessed, but is merely a natural interface after the CMP (CHEMICAL MECHANICAL polish, chemical mechanical polishing) process, and no intentional etching is required to form a rough interface, so that the second roughness is lower and approaches a smooth surface. In the embodiment of the present disclosure, since the etching process is required to be performed on at least the first region 31 later, it is not necessary to precisely control the metal height in the CMP process, and only the surface of the substrate 1 needs to be exposed. In some embodiments, the metal height of the conductive contact pad 3 after the CMP process is slightly higher than the surface of the substrate 1 by increasing the polishing force on the corresponding position of the substrate 1 and reducing the polishing force on the conductive contact pad 3, so as to adjust the metal height of the conductive contact pad 3 by etching the grooves in the subsequent etching process. Since the metal height does not need to be controlled with high precision in the CMP process, the production efficiency can be greatly improved.
Furthermore, in some embodiments of the present disclosure, a third recess may also be provided at the interface of the conductive contact pad 3 and the substrate 1 to prevent the protrusion composed of metal from diffusing out of the substrate 1 sideways.
Referring to fig. 2D, in some embodiments, whether the second region 32 may be provided with the second recess 321 or not, the second region 32 may be provided with the third recess 322, where the third recess 322 is located at the junction of the conductive contact pad 3 and the substrate 1, and has a third depth, so as to prevent the metal material from extending and diffusing along the horizontal direction of the substrate 1 due to insufficient storage space after expanding the metal material at the junction of the conductive contact pad 3 and the substrate 1, which ultimately results in shorting of the adjacent conductive contact pad 3. In some cases, the third depth may be equal to the first depth, which is not particularly limited by the present disclosure.
Referring to fig. 2E, in an embodiment, in order to prevent the metal in the area of the conductive line 2 from generating a transition backlog on the metal in other areas, so as to cause the edge metal to deform and overflow, a fourth recess 312 may be disposed at the edge position of the first area 31, where the fourth recess 312 has a fourth depth, and the fourth depth may be greater than the first depth, for example.
Furthermore, in other embodiments of the present disclosure, the roughness of the first region 31 may be greater than the roughness of the second region 32 by other means. For example, the interval between the first recesses 311 is set to be larger than the interval between the second recesses 321, or the surface area of the first recesses 311 is set to be larger than the surface area of the second recesses 321, or the like. There are various ways of achieving the roughness differentiation, which the present disclosure does not impose as a particular limitation.
Fig. 3 is a flow chart of a method for fabricating the semiconductor structure shown in fig. 1 or fig. 2A to fig. 2E.
Referring to fig. 3, a manufacturing method 300 may include:
step S31, providing a substrate, wherein a conductive connecting wire is formed in the substrate;
step S32, forming a conductive contact pad on the surface of the conductive connecting wire, wherein the cross-sectional area of the conductive contact pad is larger than that of the conductive connecting wire;
and step S33, etching the position, corresponding to the conductive connection line, in the conductive contact pad to form a first area, wherein the first area has a first roughness.
In the embodiment shown in fig. 3, the surface of the conductive contact pad may be etched multiple times using a wet etching process (e.g., hcl+h 2O2 mixed solution) or other etching process.
In some embodiments, step S33 may include etching a location in the conductive contact pad corresponding to the conductive connection line to form a plurality of first recesses, the first recesses having a first depth.
After the first area is etched, the roughness of the first area is larger than that of other areas of the conductive contact pad, so that a larger accommodating space can be provided for extruded metal at the corresponding position of the conductive connecting wire in the bonding process, and a more uniform bonding interface is provided.
Further, in order to provide a better bonding effect, etching may be performed again at a position of the second surface of the conductive contact pad except the first region to form a second region having a second roughness, which is smaller than the first roughness.
The process of forming the second region includes, for example, etching the conductive contact pad at a location other than the first region to form a plurality of second recesses having a second depth that is less than the first depth.
In one embodiment, the recess depth may be controlled by controlling the etching time or etching concentration. When the recesses are etched, the first depth and the second depth can be determined according to the surface area of the first recess and the second recess and the cross-sectional area ratio of the conductive connecting line and the conductive contact pad.
For example, when the ratio of the cross-sectional areas of the conductive connection lines and the conductive contact pads is greater than a first preset value, and the top-view surface of the first recess may be set to be larger (the ratio of the top-view area of the first recess to the area of the first region is greater than a second preset value), the first depth may be set to be shallower, so as to reduce the etching amount of the surface metal and avoid open circuit in the bonding process. When the ratio of the cross-sectional areas of the conductive connecting lines and the conductive contact pads is smaller than or equal to the first preset value, and the top-view surface of the first recess is set smaller (the ratio of the top-view area of the first recess to the area of the first area is smaller than or equal to the second preset value), the first depth can be set deeper, so that the accommodating space of extruded metal in the first area is increased.
Similarly, when the ratio of the cross-sectional area of the conductive connection line to the conductive contact pad is greater than a first preset value, the difference between the second depth and the first depth can be set smaller when the ratio of the cross-sectional area of the conductive connection line to the conductive contact pad is smaller than or equal to the first preset value, and the difference between the second depth and the first depth can be set larger when the ratio of the cross-sectional area of the conductive connection line to the conductive contact pad is larger when the ratio of the cross-sectional area of the second area of the conductive connection line to the conductive contact pad is smaller than or equal to the first preset value, so that the difference between the second depth and the first depth is smaller, the etched metal amount is reduced, and open circuits are avoided.
Still further, the interface of the conductive contact pad and the substrate may be etched to form a plurality of third recesses having a third depth. In some embodiments, the third depth may be greater than or equal to the first depth to avoid metal extension of the conductive contact pad region toward the substrate.
The semiconductor structure shown in fig. 1 or fig. 2A-2E is manufactured by using the method shown in fig. 3, so that a larger accommodating space can be formed for extruded metal at the position corresponding to the conductive connecting wire, a more uniform bonding interface is provided, and the bonding effect is optimized.
In the method, the metal height is not required to be precisely controlled in the process of carrying out CMP on the surface of the conductive contact pad, but the metal height is manufactured by Cheng Shikong times of subsequent etching, so that the condition that the surface of the conductive contact pad is lower than the surface of the substrate in the related art is avoided, and the open circuit phenomenon caused by the fact that the surface of the conductive contact pad is lower than the surface of the substrate in the bonding process can be effectively avoided.
In order to prevent the extruded metal from not completely filling the recess to cause the void, the upper surface of the recess may be set large and the bottom form of the recess may be set flat.
Fig. 4 is a flowchart of a wafer bonding method provided in an exemplary embodiment of the present disclosure. The embodiment shown in fig. 4 may be implemented by the semiconductor structure shown in fig. 1 or fig. 2A to fig. 2E. The semiconductor structure described above may be fabricated by the method of the embodiment shown in fig. 3.
Referring to fig. 4, a wafer bonding method 400 may include:
Step S41, providing a first wafer, wherein the first wafer comprises a first substrate, a first conductive connecting line and a first conductive contact pad, the first conductive connecting line is positioned in the first substrate, the first surface of the first conductive contact pad is connected with the first conductive connecting line, the second surface of the first conductive contact pad is provided with a first area and a second area, the first area corresponds to the first conductive connecting line in position, and the second area is an area of the second surface of the first conductive contact pad except the first area, wherein the first area is provided with a first roughness, the second area is provided with a second roughness, and the first roughness is larger than the second roughness;
Step S42, providing a second wafer, wherein the second wafer comprises a second substrate, a second conductive connecting line and a second conductive contact pad, the second conductive connecting line is positioned in the second substrate, the first surface of the second conductive contact pad is connected with the second conductive connecting line, a third area and a fourth area are arranged on the second surface of the second conductive contact pad, the third area corresponds to the second conductive connecting line in position, and the fourth area is an area, except for the third area, of the second surface of the second conductive contact pad, wherein the third area has the first roughness, and the fourth area has the second roughness;
and step S43, controlling the first conductive contact pad to be contacted with the first area and the third area of the second conductive contact pad, and the second area and the fourth area to be contacted so as to bond the first wafer and the second wafer.
In the presently disclosed embodiments, "wafer" refers broadly to a semiconductor material that requires a bonding process, and is not limited to a silicon substrate. During the bonding process, different wafers are connected by metal contact pads to form a complex circuit with a multi-layered structure. In order to complete the die bonding process, it is first necessary that the wafer surfaces bonded to each other must be flat, smooth and clean in order for bonding to be successful.
However, in the embodiment of the present disclosure, the surfaces of the conductive contact pads of the two wafers bonded to each other are provided with rough surfaces, contrary to the common practice of the related art, the technical prejudice that the bonding process surfaces need to be flat and smooth to achieve good bonding is overcome. By bonding the first region and the third region which are rough, the accommodating space of extruded metal in the region corresponding to the conductive connecting wire can be increased, and the uniformity of a bonding interface is improved. Because the metal height is not required to be precisely controlled in the CMP processing part, the problems that the surface of the conductive contact pad is lower than the surface of the substrate and an open circuit occurs in the bonding process in the related art can be avoided, the wafer bonding method provided by the embodiment of the disclosure not only can realize bonding with a larger area through the contact surfaces of the two conductive contact pads with the increased surface area, but also can improve the metal distribution uniformity degree of the bonding interface and optimize the wafer bonding effect while avoiding the open circuit in the bonding process.
Fig. 5 is a schematic diagram of a first wafer and a second wafer before bonding in an embodiment of the present disclosure.
Referring to fig. 5, a first substrate 510, a first conductive line 511, and a first conductive contact pad 512 are disposed on a first wafer 51, and a second substrate 520, a second conductive line 521, and a second conductive contact pad 522 are disposed on a second wafer 52.
The surface of the first conductive contact pad 512 is provided with a first region 513 and a second region 514, and the surface of the second conductive contact pad 522 is provided with a third region 523 and a fourth region 524. The first region 513 corresponds to the first conductive line 511, the second region 523 corresponds to the second conductive line 521, the roughness of the first region 513 is greater than the roughness of the second region 514, and the roughness of the third region 523 is greater than the roughness of the fourth region 524.
In one embodiment, the first conductive contact pad 512 and the second conductive contact pad 522 have the same shape and area. In another embodiment, the first conductive contact pad 512 is the same shape and different area from the second surface of the second conductive contact pad 522. In yet another embodiment, the first conductive contact pad 512 is shaped differently and has a different area than the second face of the second conductive contact pad 522. The second surfaces of the first conductive contact pad 512 and the second conductive contact pad 522 may have a circular shape, an oval shape, a rectangular shape, etc., which is not limited in this disclosure.
In the embodiment shown in fig. 5, the first region 513 is provided with a first recess 5131, the second region 514 is provided with a second recess 5141, the third region 523 is provided with a third recess 5231, the fourth region 524 is provided with a fourth recess 5241, the depth of the first recess 5131 is greater than the depth of the second recess 5141, and the depth of the third recess 5231 is greater than the depth of the fourth recess 5241.
The bottom forms of the first recess 5131, the second recess 5141, the third recess 5231 and the fourth recess 5241 can be, for example, a plane, an arc surface, an included angle and the like, and the present disclosure is not limited thereto. The bottom forms of the first recess 5131, the second recess 5141, the third recess 5231, and the fourth recess 5241 may be the same or different.
In one embodiment, a first protrusion is provided between two adjacent first recesses 5131, a second protrusion is provided between two adjacent second recesses 5141, a third protrusion is provided between two adjacent third recesses 5231, and a fourth protrusion is provided between two adjacent fourth recesses 5241.
Step S43 of the embodiment shown in fig. 4 may include the first bump contacting the third bump and the second bump contacting the fourth bump during the contacting of the first region 513 and the third region 523 and the contacting of the second region 514 and the fourth region 524.
In order to achieve better bonding, the first recesses 5131 and the fourth recesses 5241 may be provided in the same number and in the same plan view, and the second recesses 5141 and the third recesses 5231 may be provided in the same number and in the same plan view. Thus, by reasonably arranging the arrangement of the recesses on the conductive contact pads, the first conductive contact pad 512 and the second conductive contact pad 522 can be contacted with each other through the side walls between the recesses in the bonding process, and the shortest contact distance and the largest extruded metal accommodating space are manufactured in the bonding process, so as to achieve better bonding effect.
When the first recess 5131 and the fourth recess 5241, the second recess 5141 and the third recess 5231 are all in the arc-shaped peripheral configuration shown in fig. 2A and the parallelogram-shaped peripheral configuration shown in fig. 2B, the first recess 5131 and the fourth recess 5241 have the same top-view shape, the same size and the same number, and the second recess 5141 and the third recess 5231 have the same top-view shape, the same size and the same number. In this case, the first and second recesses 5131 and 5141 may have different planar shapes, different planar dimensions, and different numbers.
That is, the two types of recesses on the same conductive contact pad may differ in plan view, or may differ in plan view size, or may differ in number. The two concave top-down shapes, top-down morphological dimensions and numbers of the two concave depressions which are aligned in the center in the bonding process are the same only by keeping the two opposite conductive contact pads.
Of course, in other embodiments, the roughness of the first region 513, the second region 514, the third region 523 and the fourth region 524 may not be implemented by a regular pattern, and the second region 514 and the fourth region 524 may also be flat or near flat surfaces, which is not particularly limited in comparison with the present disclosure.
In one embodiment, step S43 of the embodiment shown in FIG. 4 may further comprise aligning the first protrusion with a center of the third recess, aligning the third protrusion with a center of the first recess, aligning the second protrusion with a center of the fourth recess, and aligning the fourth protrusion with a center of the second recess during the contacting of the first region and the third region. At this time, the shape and size of the first recess correspond to those of the third protrusion, the shape and size of the second recess correspond to those of the fourth protrusion, and the shape and size of the third recess correspond to those of the first protrusion.
Fig. 6 is a schematic diagram of a first wafer and a second wafer before bonding according to another embodiment of the disclosure.
In the embodiment shown in fig. 6, a first substrate 610, a first conductive connection 611 and a first conductive contact pad 612 are disposed on the first wafer 61, and a second substrate 620, a second conductive connection 621 and a second conductive contact pad 622 are disposed on the second wafer 62.
Referring to fig. 6, in another embodiment of the present disclosure, the first recess 6131 may receive a third protrusion, the second recess 6141 may receive a fourth protrusion, the third recess 6231 may receive the first protrusion, and the fourth recess 6241 may receive the second protrusion. I.e., the first conductive contact pad 612 is connected to the second conductive contact pad 622 in a "zipper" configuration.
In the serrated connection embodiment shown in fig. 6, the bottom surface of each recess may still have a shape of a plane, an arc surface, an included angle, etc., and the top view of each recess may have a shape of a straight line edge or a curved edge, or may have a smooth edge or a serrated edge.
In one embodiment, conductive line 2, first conductive line 511 and second conductive line 521, first conductive line 611 and second conductive line 621 are through silicon vias (TSVs, through Silicon Via).
Better bonding can be achieved by bonding wafers in the embodiments shown in fig. 5 or 6. Since more extrusion metal accommodating spaces are arranged at the positions corresponding to the conductive connecting wires, the bonding uniformity between the conductive contact pads can be effectively improved and the bonding effect is optimized while the copper extrusion phenomenon and the open circuit phenomenon existing in the related technology can be avoided.
In summary, in order to bond a wafer heterogeneously (Hybrid Bonding), the embodiment of the disclosure better bonds a copper conductive contact Pad (Bonding Cu Pad) and a copper conductive contact Pad (Bonding Cu Pad), and reduce the control difficulty when manufacturing a copper depth (1-5 nm), a first region with larger roughness is formed at a position corresponding to a conductive wire by using a wet etching method (such as hcl+h 2O2 mixed solution) or other methods, more metal expansion spaces can be reserved at the position corresponding to the conductive wire, so that the metal uniformity of a Bonding interface is better, and meanwhile, the design makes the depth control of copper not strict (1-5 nm) as that of the conventional planar Bonding design during production, so that the product processing yield is higher and the processing speed is faster.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (15)
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| CN109994444A (en) * | 2019-03-29 | 2019-07-09 | 长江存储科技有限责任公司 | Bonding chip structure and preparation method thereof |
| CN111883520A (en) * | 2020-09-03 | 2020-11-03 | 长江存储科技有限责任公司 | Semiconductor structure and manufacturing method thereof |
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| CN111883520A (en) * | 2020-09-03 | 2020-11-03 | 长江存储科技有限责任公司 | Semiconductor structure and manufacturing method thereof |
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