CN115268581A - A high-performance computing power AI edge server system architecture - Google Patents

Abstract

The present application discloses an AI edge server system architecture with high-performance computing power, which is used to improve the flexibility of use and meet the increasing demands for real-time data and security. The AI edge server system architecture in this application includes: a chassis, a CPU computing node module, an accelerator card computing node module, a routing board, and a power supply module. The CPU computing node module includes a PCIe channel, and the accelerator card computing node module is provided with There is a first accelerator card hot-swap module, the accelerator card installed on the first accelerator card hot-swap module is connected to the network, and the first accelerator card hot-swap module is exchanged and converged on the acceleration card computing node module network through the exchange module. Interface, the acceleration card computing node module is also provided with a second accelerator card plug-in module, the second accelerator card plug-in module is connected to the CPU computing node module through a cable, and the second accelerator card plug-in module is connected to the The inserted acceleration card is converged on the network interface of the computing node module of the acceleration card through the PCIe channel and through the switching module, and the network interface is connected with the network interface of the routing board.

Description

A high-performance computing AI edge server system architecture

technical field

This application relates to the field of computer technology, and in particular to an AI edge server system architecture with high-performance computing power.

Background technique

With the rapid increase in the number of IoT terminal devices and the increasing demand for real-time data and security, edge computing will become crucial in many industry application scenarios, such as road management and autonomous driving for smart traffic, and smart manufacturing. Quality inspection and equipment monitoring, disease monitoring and auxiliary diagnosis of smart medical care, etc. Edge computing is still in the early stage of development in China. As the data becomes more and more complex, the number of accelerator cards widely used in the market for edge computing servers is limited, which will limit the computing power of edge computing.

At present, in order to solve the problem of the limited number of accelerator cards for edge computing servers, a large number of accelerator cards will be expanded to increase the computing power of edge computing. Generally, a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) expansion method is used for expansion.

Using the existing accelerator card expansion method, a complex backplane structure is required when expanding the accelerator card. The PCIE bus rate is very high, and many high-speed connectors and signal reconstruction or signal amplification chips are required. It is difficult to operate and maintain, and it is difficult to meet changing requirements. need.

Contents of the invention

In order to solve the above technical problems, this application provides an AI edge server system architecture with high-performance computing power, which is used to solve the problems of difficult operation and maintenance based on standard servers, limited number of expanded accelerator cards, and limited computing power. It improves the flexibility of use and meets the growing demand for data real-time and security.

This application provides a high-performance computing AI edge server system architecture, including:

Chassis, CPU computing node module, accelerator card computing node module, routing board and power supply module;

The power supply module is electrically connected to the CPU computing node module, the accelerator card computing node module and the routing board;

The CPU computing node module is installed on the lower layer of the chassis, and the CPU computing node module includes a PCIe channel;

The accelerator card node module is installed on the upper layer of the chassis, the accelerator card computing node module is provided with a first accelerator card hot-swap module, and the accelerator card inserted on the first accelerator card hot-swap module Connecting to the network, the accelerator card is provided with a switch module, and the first accelerator card hot-swappable module exchanges and converges on the network interface of the accelerator card computing node module through the switch module, and the accelerator card computing node The module is also provided with a second accelerator card plug-in module, the second accelerator card plug-in module is connected to the CPU computing node module through a cable, and the second accelerator card plug-in module is The inserted accelerator card is converged to the network interface of the accelerator card computing node module through the PCIe channel and the switch module, and the network interface of the accelerator card computing node module is connected to the network interface of the routing board.

Optionally, the CPU computing node module is provided with a PCIe slot for inserting a GPU card.

Optionally, the CPU computing node module further includes a hard disk module for providing a storage function.

Optionally, a fan is further provided on the CPU computing node module for dissipating heat from the CPU computing node module.

Optionally, the CPU computing node module is provided with a memory for storing data.

Optionally, a midplane is installed on the accelerator card computing node module;

The network interface of the accelerator card computing node module is connected to the mid-board through a connector, and the network interface of the mid-board is connected to the network cable of the network interface of the routing board.

Optionally, an OCP3.0 module is set on the CPU computing node module.

Optionally, the second accelerator card plug-in module includes 18 accelerator card modules supporting PCIe

Optionally, the chassis is a 4U double-layer chassis.

Optionally, the chassis also includes a chassis cover;

The casing upper cover is arranged at the opening of the casing, and is used for sealing the casing.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

In this application, the CPU computing node module includes a PCIe channel, the accelerator card computing node module is provided with a first accelerator card hot-swappable module, and the accelerator card installed on the first accelerator card hot-swap module is connected to the network to accelerate The card is provided with a switch module, and the first accelerator card hot-swappable module is exchanged and converged at the network interface of the accelerator card computing node module through the switch module, and the second accelerator card plug-in module is also set on the accelerator card computing node module , the second accelerator card plug-in module is connected to the CPU computing node module through a cable, and the accelerator card installed on the second accelerator card plug-in module is converged to the accelerator card computing node module through the PCIe channel and the switch module. Network interface, the network interface of the accelerator card computing node module is connected to the network interface of the routing board. The acceleration cards are exchanged through the switching module, connected through the network, and converged at the network interface of the routing board. Through the conversion of the routing board, two IPs can be connected to the terminal. Each accelerator card works independently and can provide multiple signal channels. Improve AI computing capabilities, improve the flexibility of use, simplify operation and maintenance, and meet the growing demand for data real-time and security.

Description of drawings

In order to illustrate the technical solutions in this application more clearly, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the application. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of an AI edge server system architecture with high-performance computing power in this application;

FIG. 2 is a schematic top view of the CPU computing node module in this application;

FIG. 3 is a schematic top view of the accelerator card computing node module in this application;

FIG. 4 is a schematic top view of the accelerator card in the present application;

FIG. 5 is a schematic diagram of the power supply circuit of the high-performance computing AI edge server system architecture in this application.

Detailed ways

In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", The orientation or positional relationship indicated by "vertical", "horizontal", "horizontal", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings, and is only used to illustrate the relative positional relationship between components or components , does not specifically limit the specific installation orientation of each component or component.

Moreover, some of the above terms may be used to indicate other meanings besides orientation or positional relationship, for example, the term "upper" may also be used to indicate a certain attachment relationship or connection relationship in some cases. Those skilled in the art can understand the specific meanings of these terms in this application according to specific situations.

Furthermore, the terms "installed", "disposed", "provided", "connected", "connected" are to be interpreted broadly. For example, it may be a fixed connection, a detachable connection, or an integral structure; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediary; internal connectivity. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

In addition, the structures, proportions, sizes, etc. drawn in the accompanying drawings in this application are only used to match the content disclosed in the specification, for those skilled in the art to understand and read, and are not used to limit the implementation of this application. Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this application without affecting the effect and purpose of this application. within the scope covered by the technical content disclosed in the application.

The embodiment of this application provides an AI edge server system architecture with high-performance computing power, which is used to solve the problems of difficult operation and maintenance based on standard servers, limited number of expanded accelerator cards, and limited computing power, while improving the flexibility of use. Meet the growing data real-time and security requirements.

Typically, edge computing is often associated with the Internet of Things. IoT devices are involved in increasingly powerful processing, and thus the vast amounts of data generated need to be migrated to the "edge" of the network, where the data does not have to be continuously transferred back and forth between centralized servers for processing. As a result, edge computing is more efficient at managing large volumes of data from IoT devices, with lower latency, faster processing, and scalability. Edge computing is still in the early stage of development in China. As the data becomes more and more complex, the number of accelerator cards for edge computing servers widely used in the market is currently limited, which limits the computing power of edge computing. In the past, if you want to expand a large number of Acceleration card with PCIe expansion requires a complex backplane structure. The PCIe bus rate is very high and can reach 2.5Gbps-16Gbps. It requires many high-speed connectors and signal reconstruction or signal amplification chips, which makes operation and maintenance more difficult. , it is difficult to meet the changing needs. The high-performance computing AI edge server system architecture in this application can effectively solve the above problems,

Please refer to Figure 1. Figure 1 is a schematic structural diagram of the high-performance computing AI edge server system architecture in this application, including:

Chassis, CPU computing node module 1, accelerator card computing node module 2, routing board and power supply module 11;

The power supply module 11 is electrically connected to the CPU computing node module 1, the accelerator card computing node module 2 and the routing board;

CPU computing node module 1 is installed on the lower layer of the chassis, and CPU computing node module 1 includes PCIe channels;

The accelerator card node module is installed on the upper layer of the chassis. The accelerator card computing node module 2 is provided with a first accelerator card hot-swappable module 21. The accelerator card installed on the first accelerator card hot-swap module 21 is connected to the network. The accelerator card A switch module 24 is arranged on the top, and the first accelerator card hot-swappable module 21 exchanges and converges on the network interface of the accelerator card computing node module 2 through the switch module 24, and the accelerator card computing node module 2 is also provided with a second accelerator card The plug-in module, the second accelerator card plug-in module is connected to the CPU computing node module 1 through a cable, and the accelerator card installed on the second accelerator card plug-in module is converged in the acceleration card through the PCIe channel and through the switch module 24. The network interface of the card computing node module 2, and the network interface of the acceleration card computing node module 2 are connected to the network interface of the routing board.

Among them, as network devices have higher requirements on bandwidth, flexibility and performance, the PCIe standard has emerged as the times require. PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are assigned exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot swapping and quality of service, etc. function, and the data transfer rate is high. A channel is a path or interface for connecting external signals. A PCIe channel is a PCIe signal. One channel corresponds to one signal, such as measuring force, temperature, humidity, etc. at multiple points. The signals collected by each channel are generally sequentially sent to the signal Conditioning circuits, followed by A/D conversion, and then passed to the microprocessor. The number of channels is usually a multiple of 8, that is, 8 channels, 16 channels, etc.

Please refer to Fig. 2, Fig. 3 and Fig. 4 further, in which, the power supply module 11 is connected to the connector of the main board through hot-swapping to supply power to the main board. Under the circumstances, modules and boards can be inserted into or pulled out of the system without affecting the normal operation of the system, thereby improving the reliability, rapid maintenance, redundancy and timely recovery of disasters of the system. The main board is provided with PCIe slot 13, which is used to install GPU cards. Generally, there are 3 PCIE 5.0 slots, which can expand 3 A100 GPU cards, which can optimize the utilization of computing resources; CPU computing nodes The module 1 also includes a hard disk module 12, the hard disk module 12 is 12 3.5-inch hard disk modules, the backplane of the hard disk module 12 is connected with the slimsas interface cable on the motherboard through the PCIe channel, providing storage function, improving Computer performance and flexibility of use. The CPU computing node module is also provided with a fan 15, which is used to dissipate heat for the CPU computing node module to reduce the decrease in CPU computing performance under high temperature; the CPU computing node module is provided with a memory 14, and the set memory is 32 pieces of DDR5 memory , used to store data. The CPU computing node module 1 also includes a main board, an OCP3.0 module, two Sapphire Rapids series processors, a routing board, and a set of 1+1 hot-swappable power supply modules 11, 1+1 is to share 50% of the load , if there is a problem with one power supply module 11, the other will bear all the loads, preventing the situation that only a single power supply module 11 fails and causes outage. Among them, the first accelerator card computing node module 2 includes two front-mounted hot-swappable modules of 25 first accelerator cards, and two rear-mounted hot-swappable modules of 16 first accelerator cards, including 18 PCIe channels The second accelerator card computing node module 2 has a total of 100 accelerator cards. The switch module 24 is arranged on the accelerator card, and also includes a set of 1+1 hot-swappable power supply modules 11 and cooling fans. Optionally, the accelerator card computing node module 2 is also equipped with a middle board 23, the network interface of the accelerator card computing node module 2 is connected to the middle board 23 through a connector, and the network interface on the middle board 23 is connected to the network interface of the routing board connected by the network cable.

Wherein, please further refer to FIG. 5 , the power supply circuit scheme may be: 16 first accelerator card hot-swap modules and 25 first accelerator card hot-swap modules are directly connected through the network. The 18 second accelerator card hot-swappable modules use the PCIe channels on the motherboard of the CPU computing node module, and the clock numbers of each channel are different. The power supply of the 18 second accelerator card hot-swappable modules of the accelerator card computing node module 2 is the power supply of the CPU computing node module 1. The 2000W1+1 redundant hot-swappable power supply of the CPU computing node module supplies power to the main board, and supplies power to 18 second accelerator card hot-swappable modules and fans of the CPU computing node module through cables; 16 of the accelerator card computing node module 2 The first accelerator card hot-swap module and 25 first accelerator card hot-swap modules are directly powered by the above 2000W1+1 hot-swap power supply.

The 25 first accelerator card hot-swappable modules and 16 first accelerator card hot-swap modules of the accelerator card node are directly connected to the network. One switch module can exchange a maximum of 9 accelerator cards, and two groups of 25 first accelerator cards The card hot-swappable module and two groups of 16 hot-swappable modules of the first accelerator card are exchanged and converged on 10 network interfaces through the 10 switching modules placed on the back of the accelerator card, and are connected to the first mid-plane through a connector. The 10 network interfaces on the first middle board are connected to the 10 network interfaces on the routing board; the 18 second accelerator card plug-in modules on the upper-layer accelerator card node are connected to the mcio interface on the motherboard on the lower-layer CPU computing node through the mcio interface. The PCIe signal is used, and then two network interfaces are exchanged and aggregated through two switching modules, and connected to the second midplane through a connector. The two network interfaces on the second midplane are connected to the two network interfaces of the routing board with network cables. All accelerator cards are aggregated to the routing board through 12 network interfaces, and the routing board provides 2 IP addresses to connect to the terminal. Each accelerator card works independently and can provide a maximum of more than 2,000 signal channels, which greatly improves AI computing capabilities, improves the flexibility of use, and is simple to operate and maintain, meeting the growing demand for real-time data and security.

Optionally, the chassis is a 4U double-layer chassis. "U" refers specifically to the thickness of rack-mounted servers in the server field. It is a unit that indicates the external dimensions of the server. The basic unit of thickness is cm. 1U is 4.45cm, and 4U is 17.8cm which is 4 times of 1U. In this embodiment, the size of the chassis can be adjusted according to the actual equipment to be placed.

Optionally, the chassis also includes a chassis upper cover;

The casing upper cover is arranged at the opening of the casing, and is used for sealing the casing. Reduce dust entering the chassis and causing damage to components in the chassis.

It should be declared that the above summary of the invention and specific implementation methods are intended to prove the practical application of the technical solutions provided by the application, and should not be interpreted as limiting the scope of protection of the application. Those skilled in the art may make various modifications, equivalent replacements or improvements within the spirit and principles of the present application. The scope of protection of the present application is subject to the appended claims.

Claims (10)

1. An AI edge server system architecture with high-performance computing power, characterized in that it includes: Chassis, CPU computing node module, accelerator card computing node module, routing board and power supply module; The power supply module is electrically connected to the CPU computing node module, the accelerator card computing node module and the routing board; The CPU computing node module is installed on the lower layer of the chassis, and the CPU computing node module includes a PCIe channel; The accelerator card node module is installed on the upper layer of the chassis, the accelerator card computing node module is provided with a first accelerator card hot-swap module, and the accelerator card inserted on the first accelerator card hot-swap module Connecting to the network, the accelerator card is provided with a switch module, and the first accelerator card hot-swappable module exchanges and converges on the network interface of the accelerator card computing node module through the switch module, and the accelerator card computing node The module is also provided with a second accelerator card plug-in module, the second accelerator card plug-in module is connected to the CPU computing node module through a cable, and the second accelerator card plug-in module is The inserted accelerator card is converged to the network interface of the accelerator card computing node module through the PCIe channel and the switch module, and the network interface of the accelerator card computing node module is connected to the network interface of the routing board. 2. The AI edge server system architecture according to claim 1, wherein the CPU computing node module is provided with a PCIe slot for inserting a GPU card. 3. The AI edge server system architecture according to claim 1, wherein the CPU computing node module further includes a hard disk module for providing storage functions. 4. The AI edge server system architecture according to claim 1, wherein a fan is further provided on the CPU computing node module to dissipate heat for the CPU computing node module. 5. The AI edge server system architecture according to claim 1, wherein the CPU computing node module is provided with a memory for storing data. 6. The AI edge server system architecture according to claim 1, wherein a middle board is installed on the accelerator card computing node module; The network interface of the accelerator card computing node module is connected to the mid-board through a connector, and the network interface of the mid-board is connected to the network cable of the network interface of the routing board. 7. The AI edge server system architecture according to claim 1, wherein an OCP3.0 module is set on the CPU computing node module. 8. The AI edge server system architecture according to claim 1, wherein the second accelerator card plug-in module includes 18 accelerator card modules supporting PCIe. 9. The AI edge server system architecture according to any one of claims 1 to 8, wherein the chassis is a 4U double-layer chassis. 10. The AI edge server system architecture according to claim 9, wherein the chassis further comprises a chassis top cover; The casing upper cover is arranged at the opening of the casing, and is used for sealing the casing.

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