CN115249502A - NOR flash memory array and data writing method, reading method and erasing method thereof - Google Patents
NOR flash memory array and data writing method, reading method and erasing method thereof Download PDFInfo
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract
In the NOR flash memory array provided by the invention, each memory cell comprises a source line selection tube and n memory tubes which are sequentially connected in series, the source electrode of the source line selection tube is used as the total source electrode end of the memory cell, the source line selection tube and the n memory tubes in each memory cell are arranged along the column direction, and the source line selection tubes in the memory cells on the same row are arranged along the row direction; each bit line is connected with the total drain terminal of each memory cell on the same column; each common source line is connected with the total source pole end of each memory cell on the same row; each word line is connected with the grids of the storage tubes which are connected in series at the same position in each storage unit on the same row; each source line selection line is connected with the grid of the source line selection tube in each storage unit on the same row. In this way, n memory cells can share one source line selection pipe, which is beneficial to improving the storage density of the NOR flash memory array. The invention also provides a data writing method, a data reading method and a data erasing method of the NOR flash memory array.
Description
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a NOR flash memory array, a data writing method, a data reading method, and a data erasing method.
Background
Flash memory (flash memory) is a Nonvolatile semiconductor memory chip that retains stored data information even when power is turned off. In addition, the flash memory has the advantages of small volume, low power consumption and being not easy to be damaged by physics, thereby being widely applied.
In a conventional NOR flash memory array, for example, a 1T (1 Transistor), a 2T (2 Transistor) or a Split Gate (Split Gate) NOR flash memory array (memory array), a plurality of memory cells (cells) on a same column are all connected to a same Bit line, and the memory cells connected to the same Bit line are connected in parallel, so that when a Word line (Word line) is selected, a read operation can be performed on each memory Cell connected to the Word line, thereby achieving a high read rate.
Fig. 1 is a schematic diagram of a conventional 2TNOR flash memory array. As shown in fig. 1, in the 2TNOR flash memory array, each memory cell 10 includes a memory cell 101 and a source line select cell 102. Specifically, the drain of the storage tube 101 is connected to a Bit Line (BL), the Source is connected to the drain of the Source Line select tube 102, and the Source of the Source Line select tube 102 is connected to a Common Source Line (CSL). In addition, in the flash memory array, gates of the plurality of memory tubes 101 in the same row are connected to the same Word Line (WL), and gates of the plurality of source Line select tubes 102 in the same row are connected to the same source Line select Line (SSL). It can be seen that the individual memory tubes 101 (opposite bit lines) on the same column are connected in a parallel architecture.
However, in the parallel architecture shown in fig. 1, each of the memory tubes 101 in the same column is connected to the same bit line in parallel, so that the connection of the bit lines and the metal traces in the NOR flash memory array occupy a large area, and the storage density of the NOR flash memory array is reduced. In addition, in the NOR flash memory array, each storage tube 101 is provided with an independent source line selection tube 102, so that the area occupied by the storage unit 10 is large, the storage density of the NOR flash memory array is reduced, and the cost of unit storage capacity is increased.
Disclosure of Invention
The invention provides a NOR flash memory array, which can improve the storage density of the NOR flash memory array and reduce the cost of unit storage capacity. The invention further provides a data writing method, a data reading method and a data erasing method of the NOR flash memory array.
To achieve the above object, the present invention provides a NOR flash memory array. The NOR flash memory array comprises:
the memory comprises a plurality of memory units arranged in rows and columns, wherein each memory unit comprises a source line selection tube and n memory tubes which are sequentially connected in series and is provided with a total source pole end and a total drain pole end, a source electrode of the source line selection tube is used as the total source pole end of the memory unit, the source line selection tube and the n memory tubes in each memory unit are arranged along the column direction, the source line selection tubes in each memory unit on the same row are arranged along the row direction, and n is more than or equal to 2;
a plurality of bit lines, each of which extends in a column direction and connects the global drain terminals of the memory cells on the same column;
a plurality of common source lines each extending in a row direction and connecting the total source terminals of the memory cells in the same row;
the word lines extend along the row direction and are connected with the gates of the storage tubes which are connected in series at the same position in each storage unit on the same row;
and each source line selection line extends along the row direction and is connected with the grid electrodes of the source line selection tubes in the storage units on the same row.
Optionally, each of the memory cells further includes a bit line select transistor, a source of the bit line select transistor is connected to a drain of the n storage transistors that is not connected to another storage transistor, and a drain of the bit line select transistor is a global drain terminal of the memory cell.
Optionally, the NOR flash memory array further includes a plurality of bit line select lines, each of which extends in the row direction and is connected to gates of bit line select transistors in the memory cells in the same row.
Optionally, the plurality of memory cells arranged in rows and columns are disposed on the same surface of the injection well on the substrate.
Optionally, the data writing, data reading and data erasing operations of the NOR flash memory array all use a page as a unit, all the storage tubes connected to the same word line are located in the same page, and one page corresponds to one word line; the NOR flash memory array can select any page address and carry out data writing, data reading and data erasing on the storage tube corresponding to the page address.
Optionally, in two adjacent storage tubes of the same storage unit, the source of one storage tube is directly connected to the drain of the other storage tube.
Optionally, the injection well is P-type, and the memory cell, the source line select transistor, and the bit line select transistor are all N-type.
Optionally, the injection well is of an N-type, and the memory cell, the source line select transistor, and the bit line select transistor are all of a P-type.
Optionally, in at least some rows of the memory cells, the source line selection tubes of every two rows of the memory cells are adjacent to each other, and the total source terminal is connected to the same common source line.
The present invention also provides a data writing method of the NOR flash memory array, the data writing method comprising:
applying a first negative voltage to the injection well;
for a memory cell where a memory tube to be written is located and a memory cell in the same row as the memory cell where the memory tube to be written is located, applying a voltage which is greater than zero and smaller than a power supply voltage to a corresponding bit line selection line, applying a first negative voltage to a corresponding source line selection line, applying a first negative voltage to a bit line connected to the memory tube to be written, applying an inhibit voltage to a bit line connected to the memory tube not to be written, the inhibit voltage being greater than zero and smaller than or equal to the power supply voltage, applying a second negative voltage to a corresponding common source line, the second negative voltage being greater than the first negative voltage and smaller than zero, applying a first positive voltage to a word line connected to the memory tube to be written, applying a start voltage to a word line connected to the memory tube not to be written, the start voltage being smaller than the first negative voltage and enabling the unselected memory cell to be in a start state;
and applying a first negative voltage to the bit line selection line, the word line and the source line selection line corresponding to other memory cells in a row different from the memory cell in which the memory tube to be written is positioned.
Optionally, the magnitude of the channel current of the storage tube to be written is modulated by adjusting the magnitude of the turn-on voltage.
The invention also provides a data reading method of the NOR flash memory array, which comprises the following steps:
applying zero volts to both the implant well and the common source line;
for a memory cell where a memory tube to be read is located and a memory cell in the same row as the memory cell where the memory tube to be read is located, applying a second positive voltage to the corresponding bit line selection line and the corresponding source line selection line, applying a zero volt voltage to a word line connected to the memory tube to be read, applying a third positive voltage to a word line connected to the memory tube not to be read, so that the memory tube not to be read is in an open state, applying a fourth positive voltage to the bit line connected to the memory tube to be read, and applying a zero volt voltage to the bit line connected to the memory tube not to be read;
and for other memory cells in a row different from the memory cell in which the memory tube to be read is positioned, applying zero voltage to the corresponding bit line selection line, source line selection line and word line.
Optionally, the magnitude of the channel current of the storage tube to be read is modulated by adjusting the magnitude of the third positive voltage.
The invention also provides a data erasing method of the NOR flash memory array, which comprises the following steps: and applying a positive voltage to the injection wells, applying power supply voltage to all the bit line selection lines and the source line selection lines, applying a positive voltage or suspension to the common source line and all the bit lines, applying a negative voltage to the word lines connected with the storage tubes to be erased, and applying a positive voltage to the word lines connected with the storage tubes not to be erased.
The NOR flash memory array comprises a plurality of memory cells arranged in rows and columns, a plurality of bit lines, a plurality of common source lines, a plurality of word lines and a plurality of source line selection lines; each memory cell comprises a source line selection tube and n memory tubes which are sequentially connected in series, and is provided with a total source pole end and a total drain pole end, wherein a source electrode of the source line selection tube is used as the total source pole end of the memory cell, the source line selection tube and the n memory tubes in each memory cell are arranged along the column direction, the source line selection tubes in each memory cell on the same row are arranged along the row direction, and n is more than or equal to 2; each bit line extends along the column direction and is connected with the total drain end of each memory cell on the same column; each common source line extends along the row direction and is connected with the total source terminal of each memory cell on the same row; each word line extends along the row direction and is connected with the grid electrodes of the storage tubes which are connected in series and have the same position in each storage unit on the same row; each source line selection line extends along the row direction and is connected with the grid of a source line selection tube in each memory cell on the same row. That is to say, in the NOR flash memory array of the present invention, n storage tubes of each storage unit are sequentially connected in series, and the connection between the n storage tubes and the bit line can be realized by connecting the total drain terminal of the storage unit with the bit line, without the need of separately connecting each storage tube in the storage unit in parallel to the same bit line, which is helpful for reducing the area occupied by the connection of the bit line and the metal routing in the NOR flash memory array, is helpful for improving the storage density of the NOR flash memory array, and reduces the cost of the unit storage capacity; furthermore, n memory cells in the same memory cell can share the same source line selection tube, so that the number of the source line selection tubes in the NOR flash memory array is reduced, the occupied area of the source line selection tubes in the NOR flash memory array is reduced, and the storage density of the NOR flash memory array is improved.
The NOR flash memory array data writing method, the NOR flash memory array data reading method and the NOR flash memory array data erasing method can realize data writing, data reading and data erasing to the NOR flash memory array.
Drawings
Fig. 1 is a schematic diagram of a conventional 2TNOR flash memory array.
FIG. 2 is a block diagram of a NOR flash memory array according to one embodiment of the present invention.
FIG. 3 is a layout diagram of a NOR flash memory array according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating voltage application during data writing of a NOR flash memory array according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating voltage application during data reading of a NOR flash memory array according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating voltage application during page erase for a NOR flash memory array according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating voltage application during block erase for a NOR flash memory array according to an embodiment of the present invention.
Detailed Description
The NOR flash memory array and the data writing method, the data reading method and the data erasing method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to increase the storage density of the NOR flash memory array and reduce the cost of the cell storage capacity, the present embodiment provides a NOR flash memory array.
FIG. 2 is a block diagram of a NOR flash memory array according to an embodiment of the present invention. FIG. 3 is a layout diagram of a NOR flash memory array according to an embodiment of the present invention. As shown in fig. 2 and 3, the NOR Flash memory array is a Sub-tandem NOR Flash memory array (SSNOR). The NOR flash memory array includes a plurality of memory cells 20 (Cell String), a plurality of Bit Lines (BL), a plurality of Common Source Lines (CSL), a plurality of Word Lines (WL), and a plurality of source line select lines (SSL) arranged in rows and columns.
Specifically, each memory cell 20 includes a source line selection tube 202 and n memory tubes 201 connected in series in sequence, and has a total source terminal and a total drain terminal, a source of the source line selection tube 202 is used as the total source terminal of the memory cell 20, the source line selection tube 202 and the n memory tubes 201 in each memory cell 20 are arranged along a column direction, the source line selection tubes 202 in each memory cell 20 in the same row are arranged along a row direction, and n is greater than or equal to 2.
In more detail, in two adjacent storage tubes 201 of the same storage unit 20, the source of one storage tube 201 is directly connected to the drain of the other storage tube 201, and a contact hole is not required to be arranged in the middle, so that n storage tubes 201 are connected in series, which helps to reduce the area occupied by the contact hole and improve the storage density of the NOR flash memory array.
In the memory cell 20, the drain of the storage tube 201 located at one end and distant from the source line selection tube 202 is connected to a bit line, the source of the storage tube 201 located at the other end and close to the source line selection tube 202 is connected to the drain of the source line selection tube 202, and the source of the source line selection tube 202 is connected to a Common Source Line (CSL).
In this embodiment, for the memory cells 20 in the same row, the arrangement order of the n memory tubes 201 and the source line selection tube 202 in the column direction is the same. As shown in fig. 2, the n memory cells 201 and the source line selection cell 202 in the memory cell in the first row are all arranged in the order of the first memory cell, the second memory cell, … …, the nth memory cell, and the source line selection cell 202.
In the NOR flash memory array, each of the bit lines extends in a column direction and connects the global drain terminals of the individual memory cells 20 on the same column. By way of example, as shown in FIG. 2, the total drain terminals of the memory cells 20 of the first column are each connected to a first bit line BL 00; the total drain terminals of the memory cells 20 in the second column are all connected with a second bit line BL01; the total drain terminals of the memory cells 20 in the mth column are each connected to an mth bit line BL (m).
Each of the common source lines extends in the row direction and connects to the total source terminal of each memory cell 20 in the same row, that is, each common source line connects to the source of the source line select transistor 202 of each memory cell 20 in the same row. Each of the source line select lines extends in the row direction and connects the gates of the source line select transistors 202 in the respective memory cells 20 in the same row.
Each word line extends along the row direction and connects the gates of the storage transistors 201 in the same row in the memory cells 20 at the same serial position, that is, the source selection transistors 202 and the n storage transistors 201 in the memory cells 20 in the same row are arranged in rows and columns, and the serial positions of the source selection transistors 202 are the same. For example, as shown in fig. 2, for the memory cells 20 in the first row, the gates of the memory cells 201 in the first row are all connected to a first word line WL00, the gates of the memory cells 201 in the second row are all connected to a second word line WL01, … …, the gates of the memory cells 201 in the n-1 th row are all connected to an n-1 th word line WL (n-1), and the gates of the memory cells 201 in the n-1 th row are all connected to an n-th word line WL (n).
As shown in fig. 2, in this embodiment, each memory cell 20 may further include a bit line select transistor 203, a source of the bit line select transistor 203 is connected to a drain of the n storage transistors 201 that is not connected to other storage transistors 201, and a drain of the bit line select transistor 203 is a total drain terminal of the memory cell 20. The NOR flash memory array may further include a plurality of bit Line Selected lines (BSLs), each extending in a row direction and connecting gates of the bit Line select transistors 203 in the respective memory cells on the same row.
Specifically, the drain of the storage tube 201, which is located at one end of the memory cell 20 and is far away from the source line select tube 202, may be connected to the source of the bit line select tube 203, and the drain of the bit line select tube 203 may be connected to the bit line; for the memory cells 20 in the same row, all the bit line select transistors 203 may be arranged in sequence along the row direction and the gates of the bit line select transistors 203 are connected to the same bit line select line. Each memory cell 20 includes a bit line select transistor 203, which can reduce the bit line load and the leakage current of the memory cell 201 when reading data from the NOR flash memory array, increase the reading speed, increase the sensing Window (Sense Window) for data reading, and allow more memory cells 20 to be connected to the same bit line.
In another embodiment, the memory cell 20 may not include the bit line select transistor 203, and the drain of the memory cell 201 located at one end of the memory cell 20 and far from the source line select transistor 202 may be used as the drain of the memory cell 20 and directly connected to a bit line, so as to save the occupied area of the bit line select transistor 203, so as to provide more memory cells 201, which is beneficial to improving the storage density of the NOR flash memory array.
In this embodiment, the memory cells 20 arranged in rows and columns may be disposed on the same surface of the injection well on the substrate. The implant well may be formed on the substrate by an ion implantation process. The injection trap can be of an N type or a P type.
The memory cell 20 including the bit line select transistor 203 will be described as an example.
In the NOR flash memory array, in at least some rows of the memory cells 20, the source line select tubes 202 of every two rows of the memory cells 20 may be adjacent, and the total source terminal may be connected to the same common source line.
As an example, every two adjacent rows of the memory cells 20 may be taken as a group, and for two rows of the memory cells 20 of the same group, an arrangement order of the n memory cells 201 and the source line selection tubes 202 in the memory cells 20 of one row in the column direction may be opposite to an arrangement order of the n memory cells 201 and the source line selection tubes 202 in the memory cells 20 of the other row in the column direction. As shown in fig. 2 and 3, the memory cells in the first and second rows are a group, and the transistors in the memory cells 20 in the first row are arranged in the column direction in the order of bit line select transistor 203, first memory transistor, second memory transistor, … …, nth memory transistor, and source line select transistor 202; the transistors in the memory cell 20 in the second row are arranged in the column direction in the order of the source line selection transistor 202, the nth memory transistor, the (n-1) th memory transistor, … …, the second memory transistor, and the first memory transistor. But not limited thereto, in other embodiments, the arrangement order of the transistors in all the memory cells 20 may be the same.
Referring to fig. 2 and 3, in the present embodiment, the storage tube 201, the source line select tube 202 and the bit line select tube 203 are formed on active regions of an implantation well, adjacent active regions are isolated by an isolation structure, and the depth of the isolation structure is less than the depth of the implantation well. The bit line select transistors 203 in the memory cells 20 in every two adjacent rows are arranged adjacently, and the drains of the bit line select transistors 203 are connected to the bit lines through contact holes (CT). The source line selection tubes 202 in each two adjacent rows of memory cells 20 are arranged adjacently, and the source electrodes of the source line selection tubes 202 are connected to a common source line through contact holes (CT).
In this embodiment, the injection well may be of a P-type, and the storage tube 201, the source line selection tube 202, and the bit line selection tube 203 may all be of an N-type. The source line selection tube 202 and the bit line selection tube 203 can be both N-type field effect transistors, and the storage tube 201 can be an N-type flash memory. In other embodiments, the injection well may be of an N-type, and the storage tube 201, the source line select tube 202, and the bit line select tube 203 may all be of a P-type.
The NOR flash memory array of the present embodiment includes a plurality of memory cells 20 arranged in rows and columns, a plurality of bit lines, a plurality of common source lines, a plurality of word lines, and a plurality of source line selection lines; each memory cell 20 comprises a source line selection tube 202 and n memory tubes 201 which are sequentially connected in series, and has a total source pole end and a total drain pole end, wherein a source electrode of the source line selection tube 202 is used as the total source pole end of the memory cell 20, the source line selection tube 202 and the n memory tubes 201 in each memory cell 20 are arranged along a column direction, the source line selection tubes 202 in each memory cell 20 in the same row are arranged along a row direction, and n is greater than or equal to 2; each of the bit lines extends in a column direction and connects the global drain terminals of the individual memory cells 20 on the same column; each of the common source lines extends in a row direction and connects the total source terminals of the respective memory cells 20 on the same row; each word line extends along the row direction and is connected with the gates of the storage tubes 201 which are connected in series and have the same position in each storage unit 20 on the same row; each of the source line select lines extends in the row direction and connects the gates of the source line select transistors 202 in the respective memory cells 20 in the same row. That is to say, in the NOR flash memory array, the n storage tubes 201 of each storage unit 20 are sequentially connected in series, and the connection between the n storage tubes 201 and the bit lines can be realized by connecting the total drain end of the storage unit 20 with the bit lines, without the need that each storage tube 201 in the storage unit 20 is separately connected in parallel to the same bit line, which is beneficial to reducing the area occupied by the connection of the bit lines and the metal routing in the NOR flash memory array, and is beneficial to improving the storage density of the NOR flash memory array and reducing the cost of the unit storage capacity; furthermore, n memory cells 201 in the same memory cell 20 may share the same source line select transistor 202, which is beneficial to reducing the number of source line select transistors 202 in the NOR flash memory array, reducing the occupied area of the source line select transistors 202 in the NOR flash memory array, and further beneficial to improving the storage density of the NOR flash memory array. Preferably, under the same design rule (design rule), the NOR flash memory array of the embodiment can save 10% to 50% of area.
The NOR flash memory array of this embodiment can perform data writing, data reading, and data erasing operations in a Page (Page) unit, where all the memory cells 201 connected to the same word line are located in the same Page, and one Page corresponds to one word line; the NOR flash memory array can select any page address and carry out data writing, data reading and data erasing on the storage tube corresponding to the page address. Specifically, with a data writing method, a data reading method, and a data erasing method of the NOR flash memory array described below, a page address can be randomly selected and data thereof can be written, read, and erased.
Hereinafter, a data writing method, a data reading method, and a data erasing method of the NOR flash memory array according to the present embodiment will be described by taking an example in which the injection well is a P-type, and the memory cell 201, the source line select cell 202, and the bit line select cell 203 are all N-type.
The present embodiment further provides a data writing method for the NOR flash memory array, and data can be written into any one of the memory pipes 201 in the NOR flash memory array by using the data writing method.
The data writing method of the NOR flash memory array comprises the following steps:
applying a first negative voltage to the injection well;
for a memory cell where a memory tube to be written is located and a memory cell in the same row as the memory cell where the memory tube to be written is located, applying a Voltage which is greater than zero and less than a power supply Voltage to a corresponding bit line selection line (BSL), so that the corresponding bit line selection tube 203 is in an ON (ON) state, applying a first negative Voltage to a corresponding source line selection line (SSL), so that the corresponding source line selection tube 202 is in an off state, applying a first negative Voltage to a Bit Line (BL) connected to the memory tube 201 to be written, applying an Inhibit Voltage (Inhibit Voltage) to a bit line connected to the memory tube 201 not to be written, the Inhibit Voltage being greater than zero and less than or equal to the power supply Voltage (VCC), applying a second negative Voltage to a corresponding Common Source Line (CSL), the second negative Voltage being greater than the first negative Voltage and less than zero, applying a first positive Voltage to a Word Line (WL) connected to the memory tube 201 to be written, applying an ON Voltage to the word line connected to the memory tube 201 not to be written, the open Voltage being less than the first positive Voltage and making the memory tube not to be written in an ON state;
for other memory cells in a row different from the memory cell in which the memory cell to be written is located, the first negative voltage is applied to the corresponding bit line selection line, the corresponding word line and the corresponding source line selection line, so that the corresponding bit line selection tube 203, the corresponding memory tube 201 and the corresponding source line selection tube 202 are all in an off state.
Optionally, the magnitude of the channel current flowing through the storage tube to be written is modulated by adjusting the magnitude of the turn-on voltage. That is, the N storage tubes 201 in the same memory cell 20 may be control tubes, and the magnitude of the channel current of the storage tube 201 to be written in the same memory cell 20 may be modulated by adjusting the magnitude of the turn-on voltage applied to the word line connected to the storage tube 201 not to be written (i.e., adjusting the gate voltage of the storage tube 201 not to be written).
It should be noted that, with the data writing method, the gate to channel of the storage tube 201 to be written is a forward voltage with a magnitude of (first positive voltage — first negative voltage), so data can be written into the storage tube 201 to be written while the data of the storage tube 201 not to be written remains unchanged.
Fig. 4 shows the voltage application in the data writing of the NOR flash memory array. As shown in fig. 4, for example, when the second storage tube 201 of the first row and column of the memory cells 20 needs to be written, a first negative voltage Vneg1 is applied to the injection well (well), i.e., vwell = Vneg1.
For the memory cells 20 in the first row, a voltage greater than zero and less than the V power supply voltage (i.e., VBSL =0V to Vcc) is applied to the corresponding bit line select line, so that the bit line select transistors 203 in the first row are in an on state; applying a first negative voltage Vneg1 (i.e., vssl = Vneg 1) to the source line select line of the first row so that the source line select tubes 202 of the first row are in an off state; a first negative voltage Vneg1 is applied to a first bit line BL00 connected with a storage tube 201 needing writing, and an inhibition voltage Vinh is applied to a bit line connected with a storage tube 201 not needing writing; applying a second negative voltage Vneg2 on the corresponding common source line (i.e. Vcsl = Vneg 2); the second word line WL01 is applied with a first positive voltage Vpos1, and the other word lines (e.g., WL00, WL (n-1), WL (n), etc.) are applied with a turn-on voltage Vpass, so that the memory cell 201 which does not need to be written is in a turn-on state.
For the memory cells 20 in the second row, the first negative voltage Vneg1 is applied to the corresponding bit line select line, word line and source line select line, so that the corresponding bit line select transistor 203, memory transistor 201 and source line select transistor 202 are all in the off state.
It should be noted that, when a voltage is applied according to the voltage application case shown in fig. 4, it can be understood that writing of the second memory cell 201 (the memory cell within the dashed line frame in fig. 4) "1" of the memory cell 20 in the first row and the first column is realized, and writing of the other memory cells connected to the second word line WL01 is not realized; it is also understood that the memory transistor 201 in the dashed box in fig. 4 implements writing of "1", and the other memory transistor connected to the second word line WL01 implements writing of "0". That is, the voltage application case shown in fig. 4 can realize the writing of the second word line WL01 to the page. In addition, the voltages on BL01, … … and/or BL (m) are adjusted, so that the other storage tube connected with the second word line WL01 can realize 1 writing.
In the data writing process of the NOR flash memory array, in the memory cell 20 where the memory cell 201 to be written is located, the on-voltage needs to be applied to the word line to which the memory cell 201 not to be written is connected, so that the memory cell 201 not to be written is kept in an on state, and the voltage applied to the corresponding bit line can be transmitted to each memory cell 201 in the same memory cell 20. Since there are different levels of voltage difference between the gate and the channel of the non-write-required storage tube 201, in order to reduce disturbance (Disturb) of stored data, the turn-on voltage applied to the word line to which the non-write-required storage tube 201 is connected should be as low as possible in a case where the non-write-required storage tube 201 is turned on, for example, the turn-on voltage may be equal to or slightly greater than the sum of the threshold voltage of the storage tube 201 and the first negative voltage.
The present embodiment further provides a data reading method of the NOR flash memory array, which can read data from any one of the memory tubes 201 in the NOR flash memory array.
The data reading method of the NOR flash memory array comprises the following steps:
applying zero volts to both the implant well and the Common Source Line (CSL);
for the memory cell where the memory tube to be read is located and the memory cells in the same row as the memory cell where the memory tube to be read is located, a second positive voltage is applied to the corresponding bit line selection line (BSL) and the corresponding source line selection line (SSL), so that the corresponding bit line selection tube 203 and the corresponding source line selection tube 202 are both in an on state, a zero-volt voltage is applied to the Word Line (WL) connected with the memory tube 201 to be read, and a third positive voltage is applied to the word line connected with the memory tube 201 not to be read, so that the memory tube 201 not to be read is in the on state to transmit the voltage on the corresponding bit line; a fourth positive voltage (read voltage) is applied to the bit line connected with the storage tube 201 to be read, and a zero volt voltage is applied to the bit line connected with the storage tube 201 which does not need to be read;
for other memory cells in a row different from the memory cell in which the memory cell to be read is located, zero volt voltage is applied to the corresponding bit line selection line, source line selection line and word line, so that the corresponding bit line selection tube 203, source line selection tube 202 and memory tube 201 are all in an off state.
Optionally, the magnitude of the channel current flowing through the storage tube to be read is modulated by adjusting the magnitude of the third positive voltage. That is, the N storage tubes 201 in the same memory cell 20 may be control tubes, and the magnitude of the channel current of the storage tube 201 to be read in the same memory cell 20 may be modulated by adjusting the magnitude of the third positive voltage applied to the word line connected to the storage tube 201 not to be read (i.e., adjusting the gate voltage of the storage tube 201 not to be read).
Fig. 5 shows the voltage application of the NOR flash memory array when data reading is performed. As an example, as shown in fig. 5, for example, when the second memory tube 201 of the memory cell 20 in the first row and the first column needs to be read, zero volts (i.e., vwell =0v, vcsl =0 v) is applied to both the injection well and the common source line.
For the memory cells 20 in the first row, a second positive voltage Vsel (i.e. VBSL = Vsel, vssl = Vsel) is applied to the bit line select line and the source line select line of the first row, so that the bit line select gate 203 and the source line select gate 202 of the first row are both in an on state; a zero-volt voltage is applied to the second word line WL01 connected to the storage tube 201 to be read, and a third positive voltage Vread _ unsel is applied to the word lines (such as WL00, WL (n-1) and WL (n)) connected to the storage tube 201 not to be read, so that the storage tube 201 not to be read is in an on state to transmit the voltage on the first bit line BL 00; the fourth positive voltage Vread _ BL is applied to the first bit line BL00 connected to the storage transistor 201 to be read, and zero volts is applied to bit lines (for example, BL01, … …, BL (m)), to which the storage transistor 201 to be read is not connected.
For the memory cell 20 in the second row, zero volts is applied to the corresponding bit line select line, source line select line and word line, so that the corresponding bit line select pipe 203, source line select pipe 202 and memory cell 201 are all in the off state.
Note that, by adjusting the voltage applied to BL01, … …, and/or BL (m), data stored in another memory pipe to which the second word line WL01 is connected can be read.
During data reading of the NOR flash memory array, the second positive voltage Vsel is greater than the threshold voltages of the source line select transistor 202 and the bit line select transistor 203, so that the corresponding source line select transistor 203 and the corresponding bit line select transistor 203 are in an on state. The third positive voltage Vread _ unsel needs to be smaller than the first positive voltage of the memory tube 201 during normal data writing. In order to improve the accuracy of data reading, the fourth positive voltage Vread _ bl should be as small as possible in a case where data can be read.
When data in a certain storage tube 201 needs to be read, a zero-volt voltage is applied to a word line connected to the storage tube 201 that needs to be read, a certain voltage (a third voltage Vread _ unsel) is applied to a word line connected to the storage tube 201 that does not need to be read in the same memory cell 20, so that a Drain (Drain) and a Source (Source) of the storage tube 201 that does not need to be read are conducted, the storage tube 201 that needs to be read is in a conducting or turning-off state and depends on charges stored on a storage medium layer of the storage tube 201 that needs to be read, and the conduction or turning-off of the storage tube 201 that needs to be read realizes the reading of data "0" or "1" of the storage tube 201 that needs to be read.
The embodiment also provides a data erasing method of the NOR flash memory array. The data erasing method comprises the following steps: applying a positive voltage to the injection well, and applying a power supply voltage to all the bit line select lines (BSL) and the source line select lines (SSL), so that all the bit line select transistors 203 and the source line select transistors 202 are in an Off (Off) state; positive voltage or suspension (Floating) is applied to all the Common Source Lines (CSL) and all the Bit Lines (BL), negative voltage is applied to the Word Line (WL) connected to the memory tube 201 to be erased, and positive voltage is applied to the word line connected to the memory tube 201 not to be erased, so that the gate-to-channel of the memory tube 201 to be erased is a negative pressure difference, and thus, data of the memory tube 201 to be erased can be erased, and data of the memory tube 201 not to be erased can be kept unchanged.
Specifically, the Page Erase (Page Erase) and Block Erase (Block Erase) of the NOR flash memory array can be implemented by using the data Erase method of the NOR flash memory array of the present embodiment. The data Erase (Erase Operation) of the NOR flash memory array uses a Page (Page) as a unit, all the storage tubes 201 in the same row connected to the same word line are located in the same Page, and one Page corresponds to one word line.
Fig. 6 shows the voltage application of the NOR flash memory array when performing page erase. When performing page erase by using the data erase method of the NOR flash memory array, as shown in fig. 6, taking erasing data of a page corresponding to the second word line WL01 in the memory cell 20 in the first row as an example, a positive voltage Vpos (Vwell = Vpos) is applied to the injection well, and a power supply voltage Vcc (i.e., a chip power supply voltage) is applied to all the bit line select lines (BSL) and the source line select lines (SSL), so that all the bit line select transistors 203 and the source line select transistors 202 are in an OFF (OFF) state; a positive voltage V is applied to the Common Source Line (CSL) and all the bit lines (i.e., the first bit line BL00 to the mth bit line BL (m)) pos Or suspended, a negative voltage is applied to the second word line WL01Vneg, all other word lines are applied with a positive voltage Vpos, so that the gate-to-channel of the memory cell 201 connected to the second word line WL01 is a negative pressure difference with a magnitude of (Vneg-Vpos), and thus data of all the memory cells 201 connected to the second word line WL01 can be erased, and data of the memory cells 201 connected to other word lines can be kept unchanged.
Fig. 7 shows the voltage application of the NOR flash memory array when performing block erase. As shown in fig. 7, when the NOR flash memory array is block-erased, a positive voltage Vpos is applied to the injection well, a power supply voltage Vcc is applied to all the bit line select lines (BSL) and the source line select lines (SSL), a positive voltage Vpos or a floating voltage is applied to the Common Source Line (CSL) and all the Bit Lines (BL), and a negative voltage Vneg is applied to all the Word Lines (WL).
In this embodiment, when data writing, data reading, and data erasing are performed on the NOR flash memory array, a voltage may be applied to the word line by the flash memory controller.
The data writing method, the data reading method, and the data erasing method of the NOR flash memory array are described above by taking "the injection well is N-type, and the memory cell 201, the source line select cell 202, and the bit line select cell 203 are all P-type" as an example. When the injection well is N-type and the storage tube 201, the source line selection tube 202 and the bit line selection tube 203 are all P-type, the data writing method, the data reading method and the data erasing method of the NOR flash memory array are similar, and are not described herein again.
Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The terms "comprises," "comprising," "including," "has," "having," and any variations thereof, as referred to herein, are intended to cover a non-exclusive inclusion. Reference herein to "a plurality" means greater than or equal to two. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. Reference herein to the terms "first," "second," and the like, are merely distinguishing between similar items and not necessarily referring to a particular ordering for the items. The terms "connected" and "coupled" when used herein, unless otherwise indicated, include both direct and indirect connections (couplings). The terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," and the like as referred to herein refer to an orientation or positional relationship indicated in the drawings for convenience in describing the application and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and should not be construed as limiting the application.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (14)
1. A NOR flash memory array, comprising:
the memory comprises a plurality of memory units arranged in rows and columns, wherein each memory unit comprises a source line selection tube and n memory tubes which are sequentially connected in series and is provided with a total source pole end and a total drain pole end, a source electrode of the source line selection tube is used as the total source pole end of the memory unit, the source line selection tube and the n memory tubes in each memory unit are arranged along the column direction, the source line selection tubes in each memory unit on the same row are arranged along the row direction, and n is more than or equal to 2;
a plurality of bit lines, each of which extends in a column direction and connects the total drain terminals of the memory cells on the same column;
the common source lines extend along the row direction and are connected with the total source terminal of each memory unit on the same row;
the word lines extend along the row direction and are connected with the gates of the storage tubes which are connected in series at the same position in each storage unit on the same row;
and each source line selection line extends along the row direction and is connected with the grid electrodes of the source line selection tubes in the storage units on the same row.
2. The NOR flash memory array of claim 1 wherein each of the memory cells further comprises a bit line select transistor having a source connected to a drain of the n memory cells not connected to any other memory cell, the drain of the bit line select transistor being a global drain terminal of the memory cell.
3. The NOR flash memory array of claim 2 further comprising:
and each bit line selection line extends along the row direction and is connected with the grid electrodes of the bit line selection tubes in the memory units on the same row.
4. The NOR flash memory array of claim 3 wherein the plurality of memory cells arranged in rows and columns are disposed on a same surface of the injection well on the substrate.
5. The NOR flash memory array of claim 1 wherein the data writing, data reading and data erasing operations of the NOR flash memory array are performed in units of pages, and all memory transistors connected to a same word line are located in a same page, one page corresponding to one of the word lines; the NOR flash memory array can select any page address and carry out data writing, data reading and data erasing on the storage tube corresponding to the page address.
6. The NOR flash memory array of claim 1 wherein the source of one of the two storage tubes adjacent to the same memory cell is directly connected to the drain of the other of the two storage tubes.
7. The NOR flash memory array of claim 1 wherein the injection well is P-type and the memory cells, the source line select transistors, and the bit line select transistors are all N-type.
8. The NOR flash memory array of claim 1 wherein the injection well is N-type and the memory cells, the source line select transistors, and the bit line select transistors are all P-type.
9. The NOR flash memory array of claim 1 wherein source line select gates of every two rows of the memory cells in at least some of the rows of the memory cells are adjacent and a global source terminal connects to the same common source line.
10. A data writing method of the NOR flash memory array of claim 4, comprising:
applying a first negative voltage to the injection well;
for a memory cell where a memory tube to be written is located and a memory cell in the same row as the memory cell where the memory tube to be written is located, applying a voltage which is greater than zero and smaller than a power supply voltage to a corresponding bit line selection line, applying a first negative voltage to a corresponding source line selection line, applying a first negative voltage to a bit line connected to the memory tube to be written, applying an inhibit voltage to a bit line connected to the memory tube not to be written, the inhibit voltage being greater than zero and smaller than or equal to the power supply voltage, applying a second negative voltage to a corresponding common source line, the second negative voltage being greater than the first negative voltage and smaller than zero, applying a first positive voltage to a word line connected to the memory tube to be written, applying a start voltage to a word line connected to the memory tube not to be written, the start voltage being smaller than the first negative voltage and enabling the unselected memory cell to be in a start state;
and applying a first negative voltage to the bit line selection line, the word line and the source line selection line corresponding to other memory cells in a row different from the memory cell in which the memory tube to be written is positioned.
11. The data writing method of claim 10, wherein the magnitude of the channel current flowing through the storage tube to be written is modulated by adjusting the magnitude of the turn-on voltage.
12. A method for reading data from a NOR flash memory array as claimed in claim 4, comprising:
applying zero volts to both the implant well and the common source line;
for a memory cell where a memory tube to be read is located and a memory cell in the same row as the memory cell where the memory tube to be read is located, applying a second positive voltage to the corresponding bit line selection line and the corresponding source line selection line, applying a zero volt voltage to a word line connected to the memory tube to be read, applying a third positive voltage to a word line connected to the memory tube not to be read, so that the memory tube not to be read is in an open state, applying a fourth positive voltage to the bit line connected to the memory tube to be read, and applying a zero volt voltage to the bit line connected to the memory tube not to be read;
and applying zero voltage to other memory cells in a row different from the row of the memory cell in which the memory tube to be read is positioned on the corresponding bit line selection line, source line selection line and word line.
13. The data reading method of claim 12, wherein the magnitude of the channel current of the storage tube to be read is modulated by adjusting the magnitude of the third positive voltage.
14. A method of erasing data of the NOR flash memory array of claim 4, comprising: and applying positive voltage to the injection trap, applying power supply voltage to all the bit line selection lines and the source line selection lines, applying positive voltage or suspension to the common source line and all the bit lines, applying negative voltage to the word line connected with the storage tube to be erased, and applying positive voltage to the word line connected with the storage tube not to be erased.
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