CN115242242A - Circuit for time-to-digital converter, corresponding method and laser radar - Google Patents

Abstract

The invention provides a circuit for a time-to-digital converter, comprising: the counting unit is configured to start counting the synchronous clock signals after receiving the starting signal and output coarse counting information according to the first readout signal; a synchronization unit configured to output the first readout signal to the counter and output a time residual signal of the first readout signal and the stop signal to a signal conversion unit according to a stop signal and the synchronization clock signal; and the signal conversion unit is configured to receive the time residual signal and the multi-phase clock signal, and quantize the time residual signal based on the phase state of the multi-phase clock signal to obtain fine count information. The circuit designed by the invention can realize wider time measurement range and higher precision, is not limited by the process, and greatly reduces the chip area, static power consumption and inconsistency during circuit design.

Description

Circuit for time-to-digital converter, corresponding method and laser radar

Technical Field

The present disclosure relates to the field of photodetection, and more particularly to a circuit for a time-to-digital converter and a corresponding method, such as a method of measuring time by a circuit and a lidar.

Background

In a laser radar imaging system, a system restores distance information of a measured object according to a Time-to-Digital Converter (TDC) quantization result, the TDC serves as a core module in a laser radar imaging scheme, the performance of the TDC directly influences the imaging performance of the laser radar system, generally, in order to detect farther distance, the system requires the TDC to have a very wide range, in order to present a clear image, the TDC is required to have very high precision, a contradiction exists between high precision and wide range, the high-precision TDC is often difficult to realize the wide range, and the high precision of the TDC with the same wide range is also difficult to realize.

For a high-precision TDC, particularly when the precision of the TDC is higher than the gate delay of the process, the TDC design is limited because, if the TDC is to realize the precision with the resolution of t, two digital signals with the interval of t need to exist inside the circuit, and the circuit inside the TDC also needs to be able to correctly distinguish and process the two signals, and if the minimum gate delay time of the process is greater than t, the TDC architecture based on the unit precision of the gate delay cannot realize the quantization precision with the minimum resolution of t; meanwhile, in order to obtain an output result correctly, the setup holding time of the flip-flop is also satisfied, which also has strong dependence on the using process. These two points are the difficulties encountered by high precision TDCs in non-advanced processes.

In lidar applications, the TDC directly detects the time information of the output pulse signal of the detector. A plurality of TDC are required to be measured simultaneously in the application of the laser radar using the array type and the area array type detectors, so that the precision and the dynamic range are removed, the power consumption, the chip area and the consistency can become additional consideration factors for designing the TDC, and the traditional TDC cannot realize the three points simultaneously.

In a laser radar system, because received signals are random and are asynchronous signals, and are directly quantized into digital signals which cannot be processed by a digital system, the process that the TDC simultaneously realizes asynchronous-to-synchronous conversion relates to how to process the conversion process and how to avoid the metastable state and simultaneously realize the continuous measurement of short dead time, which is one of the difficulties of the high-precision TDC.

The corresponding TDC structures are different aiming at different application scenes, and the mainstream high-precision wide-range TDC adopts a mode of combining coarse counting and fine counting, wherein the coarse counting is used for realizing the wide range, and the fine counting is used for realizing the high precision. A typical TDC structure is shown in fig. 14, in which an oscillator formed by a nand gate and an inverter starts oscillation when a rising edge of a Start signal arrives, a Counter (Counter) is used to record the number of rising edges of an output of the oscillator, the Counter stops and keeps counting when a rising edge of a Stop signal arrives, the Stop signal reads phase information of the oscillator at this time, a loop of the oscillator is opened and stops oscillation, and a decoder decodes the phase information of the oscillator, so that a fine count value is obtained, wherein a count value of the Counter is a coarse count, a maximum value is a TDC full-scale range, the phase information of the oscillator is a fine count value, and an adjacent phase difference is TDC accuracy.

In order to ensure the accuracy of the TDC precision, when external conditions such as temperature and power supply voltage change, the weight represented by each bit of the TDC quantization result is not changed, so the oscillation period of the oscillator needs periodic background calibration to ensure the quantization step accuracy.

If the oscillator for TDC is open-Loop and is not in an analog PLL (Phase Locked Loop) or DLL (Delay-Locked Loop) Loop, the low-frequency noise of the oscillator will not be filtered out, and the low-frequency noise of the oscillator will be large. Specifically, errors of single oscillation periods of the oscillator are accumulated, and when the measured time interval is long, the accumulated errors become large, for example, the clock period of the TDC coarse count is 1ns, and the oscillator generates an error of 10ps per period, so if the measured time interval is 1 μ s, the accumulated errors reach 10ns, and when the measured time is longer, the errors of the TDC are larger, which is obviously unacceptable for a TDC with high precision, which is based on the defect of the open-loop oscillator TDC. The structure has no synchronous clock, only the stop signal triggers a Voltage-Controlled Oscillator (VCO), and an output clock of the VCO cannot provide a synchronous working clock for a subsequent digital circuit.

This is disadvantageous for the PLL to adjust the oscillator frequency by controlling the voltage, since the delay of the inverter is affected by the supply voltage and temperature. Moreover, the tap spacing of the actual oscillator quantization is determined by the delay unit instead of the inverter, and the delay of the delay unit is larger relative to the inverter, which is more disadvantageous for the design of the high-precision TDC, for example, under the 180nm CMOS process, the minimum delay of the delay unit may be 100ps in the worst case, the temperature offset is ± 20ps, the TDC precision is limited, and how to break through the minimum gate delay limit and provide a stable quantization step becomes the key for designing the TDC.

When the measured time interval is long, the oscillator continuously accumulates low-frequency noise, and finally the error based on the open-loop oscillator TDC is large, and the PLL-locked clock-based TDC can eliminate the influence of the oscillator low-frequency noise, and a schematic diagram thereof is shown in fig. 15. The PLL multiplies the externally provided reference clock to a target frequency and serves as a reference clock for the counter. The clock of the TDC counter adopts a PLL locked clock instead of a clock of an open-loop oscillator, so that after the PLL is locked, a PLL internal feedback loop can filter low-frequency noise of a VCO in the loop, errors cannot be accumulated in a coarse count value of the counter, and the problem of coarse count noise of the TDC based on the open-loop oscillator is solved.

However, the starting phase of the VCO with this architecture is unknown, so even if a synchronization circuit Syn (Synchronizer) is provided, it cannot be guaranteed that the quantization output of the fine count is synchronized with the coarse count. Meanwhile, if the consistency of a plurality of groups of VCOs is poor in the application of the array TDC, the precision change of fine counting can reach 20% even under the same control voltage, which is very unfavorable for a high-precision measurement mode; the initial state of each VCO is unknown, the phase relation is not determined, different fixed deviations can be introduced, the VCO cannot be accurately synchronized, and the testing precision is influenced.

The statements in this background section merely represent techniques known to the public and are not, of course, representative of the prior art.

Disclosure of Invention

In view of at least one of the drawbacks of the prior art, the present invention proposes a circuit usable in a time-to-digital converter, comprising:

the counting unit is configured to start counting the synchronous clock signals after receiving the starting signal and output coarse counting information according to the first readout signal;

a synchronization unit configured to output the first readout signal to the counting unit and output a time residual signal of the first readout signal and the stop signal to a signal conversion unit according to a stop signal and the synchronization clock signal; and

the signal conversion unit is configured to receive the time residual signal and the multi-phase clock signal, and quantize the time residual signal based on a phase state of the multi-phase clock signal to obtain fine count information.

According to an aspect of the invention, wherein the signal conversion unit is configured to quantize the temporal residual signal based on phase states of the multi-phase clock signals to obtain first count information corresponding to rising edges of the temporal residual signal and second count information corresponding to falling edges of the temporal residual signal; determining the fine count information based on the first count information and the second count information.

According to an aspect of the invention, wherein the length of the time residual signal is larger than the period of the multi-phase clock signal.

According to an aspect of the present invention, the apparatus further comprises a multi-phase clock generating unit, the multi-phase clock generating unit receives a reference clock signal and outputs a multiplied synchronous clock signal and a multi-phase clock signal, the counting unit, the synchronizing unit and the signal converting unit receive the synchronous clock signal from the multi-phase clock generating unit, and the signal converting unit receives the multi-phase clock signal from the multi-phase clock generating unit, wherein the synchronous clock signal and the multi-phase clock signal have the same frequency.

According to an aspect of the invention, the multi-phase clock generation unit comprises a multi-stage interpolatively coupled differential inverter unit, based on which a minimum phase time difference and a period of the multi-phase clock signal can be determined.

According to an aspect of the present invention, wherein the differential inverter unit includes four kinds of phase delay units, the four kinds of delay units include inverters whose number is configured to be 4 by weight.

According to an aspect of the present invention, further comprising a time decoder determining time difference information between the start signal and the stop signal through the coarse count information and the fine count information based on a period of the multi-phase clock signal and the minimum phase time difference.

According to an aspect of the present invention, the counting unit includes a synchronous counter configured to start counting the synchronous clock signal when the start signal makes a transition, read counting the synchronous clock signal when the first readout signal makes a transition, and output coarse count information.

According to an aspect of the invention, wherein the start signal is configured to maintain a fixed phase difference from the synchronous clock signal.

According to an aspect of the present invention, wherein the signal conversion unit includes a signal generator, a plurality of sample-and-hold circuits, a first sub-decoder, and a second sub-decoder, wherein,

a signal generator configured to receive the time residual signal and generate a sampling switch control signal, a second readout signal, and a third readout signal;

a sample-and-hold circuit configured to receive the multiphase clock signal and the sampling switch control signal, and output first phase information corresponding to a second readout signal, and second phase information corresponding to a third readout signal;

a first sub-decoder configured to receive the second readout signal and decode the first phase information to output the first count information; and

a second sub-decoder configured to receive the third readout signal and decode the second phase information to output the second count information.

According to an aspect of the invention, wherein the signal generator generates the sampling switch control signal based on a rising edge and a falling edge of the temporal residual signal, and a second readout signal corresponding to the rising edge and a third readout signal corresponding to the falling edge.

According to an aspect of the invention, wherein the sample-and-hold circuit comprises: a sampling switch, a first D flip-flop, and a second D flip-flop, wherein,

the sampling switch is configured to receive the sampling switch control signal and control the connection or disconnection of the multi-phase clock signal to the first D trigger and the second D trigger;

the first D flip-flop receives the multi-phase clock signal when the sampling switch is connected and outputs the first phase information at the rising edge of the second reading signal; and

and the second D trigger receives the multi-phase clock signal when the sampling switch is connected and outputs the second phase information at the rising edge of the third reading signal.

According to an aspect of the invention, the sample-and-hold circuit further comprises an amplifier coupled to the input of the sampling switch, configured to receive the multi-phase clock signal and isolate sampling glitches.

According to an aspect of the invention, the hold time of the sampling switch control signal satisfies the time limit of the first D flip-flop and the second D flip-flop establishing the time window, the hold time of the second readout signal satisfies the time limit of the hold time window of the first D flip-flop, and the hold time of the third readout signal satisfies the time limit of the hold time window of the second D flip-flop.

According to an aspect of the invention, the synchronization unit comprises:

a third D flip-flop configured to receive the synchronous clock signal and the stop signal and output a first readout signal;

a NOT gate configured to receive the stop signal and output the signal after inversion;

a first exclusive nor gate coupled to the third D flip-flop and the not gate, configured to receive the first readout signal and an inverted signal of the stop signal and output a time residual signal;

a fourth D flip-flop coupled to the third D flip-flop, configured to receive the synchronous clock signal and the first readout signal and output; and

a second XOR gate coupled to the fourth D flip-flop and the third D flip-flop, configured to receive the first readout signal and an output signal of the fourth D flip-flop, and output a clear signal to the third D flip-flop, for resetting the third D flip-flop to restore the synchronization unit to an initial state.

According to an aspect of the invention, the rising edge of the temporal residual signal is aligned with the rising edge of the stop signal, the falling edge thereof is aligned with the rising edge of the synchronous clock signal, and the falling edge of the first readout signal is aligned with the rising edge of the synchronous clock signal.

According to an aspect of the invention, the counting unit constitutes a coarse counting module, the synchronization unit and the signal conversion unit constitute a fine counting module, wherein the circuit may comprise a plurality of fine counting modules, for each fine counting module:

respectively receiving respective stop signals to output first count information and second count information corresponding to the stop signals, and,

and outputting a corresponding first reading signal to the rough counting module, so that the rough counting module reads out rough counting information corresponding to the first reading signal according to the starting signal obtained before.

According to an aspect of the present invention, the counting unit further includes a plurality of D flip-flops coupled to the synchronous counter, configured to receive the respective first readout signals and output corresponding coarse count information, respectively.

The present invention also provides a laser radar comprising:

a transmitting unit configured to emit a detection laser beam for detecting a target object;

a receiving unit configured to receive an echo reflected by the detection laser beam on a target object and convert the echo into an electric signal; and

a circuit as described above coupled to the transmit unit and the receive unit to determine a time of flight of the echo; wherein, when the transmitting unit transmits the detection laser beam, a start signal is sent to the circuit, and when the receiving unit receives an echo signal, a stop signal is sent to the circuit.

The invention also provides a method for measuring time through a circuit, which comprises the following steps:

s101: when the counting unit receives the initial signal, the synchronous clock signal is counted;

s102: receiving a stop signal and the synchronous clock signal through a synchronization unit, generating a first readout signal and outputting the first readout signal to the counting unit, and outputting a time residual signal of the first readout signal relative to the stop signal;

s103: when the counting unit receives the first reading signal, coarse counting information is output; and

s104: and receiving the time residual signal and the multi-phase clock signal through a signal conversion unit, quantizing the time residual signal based on the phase state of the multi-phase clock signal, and outputting fine counting information.

According to an aspect of the present invention, wherein the step S101 further comprises: starting counting the synchronous clock signal by the counting unit when the start signal transits; the step S103 further includes: outputting, by the counting unit, the coarse count information to the synchronous clock signal when a transition occurs in the first readout signal.

According to an aspect of the present invention, wherein the step S104 further comprises: the signal conversion unit quantizes the time residual signal based on a phase state of the multi-phase clock signal to obtain first count information corresponding to a rising edge of the time residual signal and second count information corresponding to a falling edge of the time residual signal; determining the fine count information based on the first count information and the second count information; wherein,

the length of the time residual signal is greater than the period of the multi-phase clock signal;

the time residual signal has a rising edge aligned with a rising edge of the stop signal, a falling edge aligned with a rising edge of the synchronous clock signal, and a falling edge of the first readout signal aligned with a rising edge of the synchronous clock signal.

According to one aspect of the invention, the method further comprises:

the signal conversion unit receives the multi-phase clock signal from a multi-phase clock generation unit, and the start signal is configured to maintain a fixed phase difference with the synchronous clock signal; the multi-phase clock generation unit comprises a plurality of ring oscillators connected in parallel and configured according to weight, and the minimum phase time difference is determined based on the weight configuration and the parallel series.

According to one aspect of the invention, the method further comprises:

s105: the time decoder determines time difference information between the start signal and the stop signal from the coarse count information and the fine count information based on the period of the multi-phase clock signal and the minimum phase time difference.

According to an aspect of the invention, wherein said steps S101-103 are performed in synchronization with step S104.

According to an aspect of the invention, wherein the method is implemented by a circuit as described above.

The circuit and the method designed by the invention have the following advantages:

1) Because the time-to-digital converter TDC adopts a mode of combining coarse counting and fine counting, a wider test range can be realized, higher precision can be realized, the problem that the traditional TDC directly has compromise in precision and range is solved, and the limitation of a using process is avoided.

2) The fine counting of the TDC utilizes a multiphase clock to process the fine counting time, the multiphase state is stored in an analog sampling mode, and then the quantization is carried out through a trigger. Thus, the precision of the TDC can be free from the limitation of the gate delay and the window of the holding time established by the D-type flip-flop DFF (D-type flip-flop), thereby realizing high precision. The TDC is mostly a synchronous system with a digital circuit as a basic unit, and is fully synchronized under a stable PLL output, and has high tolerance to temperature drift and process variation.

3) Because the rough counting is realized by sampling the state value of the synchronous counter, the fine counting is realized by sampling the multiphase state value in a synchronous period, and therefore, a multiphase clock and a counter module generated by PLL are in a Start enabling state, when designing TDC, a plurality of signal conversion units can share the multiphase clock and the counter, only sampling and digital circuits with small areas are left, the area of a chip is greatly reduced, static power consumption and inconsistency are greatly reduced, and the method is suitable for laser radar using array and area array detectors.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure. In the drawings:

FIG. 1 illustrates a block diagram of a circuit that may be used in a time-to-digital converter in accordance with one embodiment of the present invention;

FIG. 2 shows a main timing diagram of the circuit of one embodiment of the present invention;

FIG. 3 illustrates a synchronization unit schematic of one embodiment of the present invention;

FIG. 4 shows a block diagram of a signal conversion unit according to an embodiment of the invention;

FIG. 5 shows a schematic diagram of a signal conversion unit of one embodiment of the present invention;

FIG. 6 shows a sample and hold circuit schematic of one embodiment of the invention;

FIG. 7 shows a timing diagram of a signal conversion unit according to an embodiment of the invention;

fig. 8a shows a schematic diagram of a multi-phase clock generation unit of an embodiment of the invention;

fig. 8b shows a timing diagram of the multi-phase clock generation unit of an embodiment of the present invention;

FIG. 9 shows a circuit schematic of a multi-phase clock generation unit of one embodiment of the present invention;

FIG. 10 shows a circuit schematic of a differential inverter cell of one embodiment of the present invention

FIG. 11 illustrates a circuit block diagram of one embodiment of the present invention that may be used in a time to digital converter;

FIG. 12 shows a lidar schematic diagram of an embodiment of the invention;

FIG. 13 shows a flow diagram of a method of measuring time by a circuit, in accordance with one embodiment of the present invention;

figure 14 shows a conventional TDC schematic;

figure 15 shows a TDC principle diagram based on a voltage controlled oscillator.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection, either mechanically, electrically, or in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

The invention designs a circuit for a time-to-digital converter TDC, which realizes high precision and wide range by adopting a mode of combining coarse counting and fine counting, wherein the coarse counting is realized by a high-speed synchronous counter and can realize wide dynamic range and synchronous output, the fine counting quantizes asynchronous time residual after synchronization by using a multiphase clock method, can realize step length less than gate-level circuit delay, and simultaneously processes a multiphase state by using a sampling and holding method to realize sampling without the limitation of a trigger establishing and holding time window, so that the TDC precision does not depend on the process advancement any more. Furthermore, the signal conversion unit based on the multi-phase clock can simultaneously support the simultaneous measurement of a plurality of detectors, the 'dead time' of each signal conversion unit is very small, and the continuous measurement can be realized. The circuit for the time-to-digital converter and the method for measuring time by the circuit can realize a multi-path TDC scheme with low power consumption, high consistency and low temperature drift.

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Fig. 1 shows a circuit block diagram of a time-to-digital converter according to an embodiment of the present invention, and a circuit 10 includes a counting unit 11, a synchronization unit 12, and a signal conversion unit 13.

Specifically, the counting unit 11 is configured to Start synchronizing the clock signal T after receiving the Start signal Start _pll Pulse counting is performed, and when the first Read signal Read is received, coarse count information N _ c is output. Specifically, the counting unit 11 clears and starts counting when a rising edge of a Start signal Start comes, the Start signal Start being an enable signal of the circuit 10 and also a reset signal of the counting unit 11. The counting unit 11 may obtain the synchronous clock signal T between the Start signal Start and the first Read signal Read _pll The pulse count value of (c). Preferably, the Start signal Start and the synchronous clock signal T _pll A fixed phase difference is maintained to avoid the problem of metastability. Metastable state means when the signal is onWhen the rising edge of the clock comes, the internal node of the trigger does not establish a definite state due to the insufficient establishment and retention time of the signal, and the output of the trigger is in an indefinite state.

The synchronization unit 12 is configured to synchronize the clock signal T with the Stop signal Stop _pll The first Read signal Read is output to the counting unit 11, and the time residual signal Δ T of the first Read signal Read and the Stop signal Stop is output to the signal converting unit 13. Specifically, the synchronization unit 12 outputs the first Read signal Read to the counting unit 11 to cause the counting unit 11 to Read out the obtained coarse count information N _ c; also, the synchronization unit 12 outputs the time residual signal Δ T of the first Read signal Read with respect to the Stop signal Stop to the signal conversion unit 13, so that the signal conversion unit 13 outputs information related to the fine count information N _ f, which will be described in detail below.

The signal converting unit 13 is configured to receive the temporal residual signal Δ T and quantize the temporal residual signal Δ T to obtain fine count information N _ f. Specifically, the signal conversion unit 13 receives the time residual signal Δ T output by the synchronization unit 12, and outputs first count information N _ l corresponding to a rising edge of the time residual signal Δ T and second count information N _ T corresponding to a falling edge of the time residual signal Δ T; the fine count information N _ f corresponding to the duration of the time residual signal Δ T is determined based on the first count information N _ l and the second count information N _ T. Expressed by the formula: n _ f = N _ t-N _ l.

According to a preferred embodiment of the present invention, the circuit 10 further comprises a multi-phase clock generation unit 14, as shown in fig. 1, the multi-phase clock generation unit 14 receives an externally input reference clock signal T _ref And outputs a multiplied synchronous clock signal T _pll And a multiphase clock signal phi<n-1:0>And outputs the synchronous clock signal T to the counting unit 11, the synchronizing unit 12 and the signal converting unit 13 _pll Synchronizing clock signal T _pll As a time reference for the coarse count information N _ c of the circuit 10 and a synchronous clock of the circuit 10, while providing an accurate, high precision and low noise global clock for the entire TDC system and subsequent digital processing modules. At the same time, the multi-phase clock generating unit 14 also sends signalsThe signal conversion unit 13 outputs a multi-phase clock signal phi<n-1:0>The signal conversion unit 13 receives the multi-phase clock signal phi<n-1:0>Multi-phase clock signal phi over the duration of the time-based residual signal Δ T<n-1:0>The phase state of (a) is changed, and fine count information N _ f corresponding to the time residual signal Δ T is obtained.

Multiphase clock signal phi<n-1:0>And synchronizing clock signal T _pll Having the same clock period, except for a multi-phase clock signal phi<n-1:0>To include n regularly varying phase clock signals, in particular multi-phase clock signals phi<n-1:0>A phase difference is periodically and uniformly inserted into the clock signal to generate n clock signals with regularly changed phase, phi<0>、phi<1>、phi<2>……phi<n-1>Where n represents the number of phase signals. The time difference value between every two adjacent phases is the minimum phase time difference t _1sb Minimum phase time difference t _1sb Is a time reference step of the signal conversion unit 13 for quantizing the fine count information N _ f. The coarse count information N _ c has a time reference step size of a synchronous clock signal T _pll And the time reference step size of the fine count information N _ f is one T _pll The larger the value of N, the larger the number of phases, and the smaller the time resolution, so the time reference step size of the fine count information N _ f has finer time granularity and better timing performance than the time reference step size of the coarse count information N _ c. And, using multi-phase clock signals phi<n-1:0>The time reference step size for realizing the fine counting is not only small in clock jitter and noise, but also can be smaller than the step size of the delay of the gate-level circuit.

According to a preferred embodiment of the invention, the circuit 10 further comprises a time decoder 15, as shown in fig. 1, the time decoder 15 being based on the multi-phase clock signal phi<n-1:0>Period of (d) and minimum phase time difference t _1sb The time difference information ToF between the Start signal Start and the Stop signal Stop is determined by the coarse count information N _ c and the fine count information N _ f. The fine count information N _ f and the time difference information ToF are expressed by the formula:

N_f＝N_t-N_l＝ΔT/t _lsb (1)

ToF＝N_c x T _pll –N_f x t _lsb (2)

according to a preferred embodiment of the invention, the length of the time residual signal Δ T is larger than the multi-phase clock signal phi<n-1:0>I.e. greater than the period of the synchronous clock signal T _pll I.e. the time residual signal Δ T is at least larger than the time reference step of the coarse count information N _ c, to ensure that the signal conversion unit 13 processing the time residual signal Δ T can work properly, or to ensure the accuracy of the fine count information N _ f.

In summary, the circuit 10 realizes a wide range of time measurement by the counting unit 11, that is, the counting unit 11 constitutes a coarse counting module. The circuit 10 achieves a high accuracy of the time measurement by means of the synchronization unit 12, the signal conversion unit 13 and the multi-phase clock unit 14, i.e. the synchronization unit 12, the signal conversion unit 13 and the multi-phase clock unit 14 constitute a fine counting module. The time decoder 15 receives the coarse count information N _ c and the fine count information N _ f, and finally outputs the measured time difference information ToF. The timing relationship of the signals of the circuit 10 and the implementation principle of the units will be further described below.

FIG. 2 shows a main timing diagram of circuit 10 of one embodiment of the present invention, in which reference clock signal T _ref For example, an external crystal oscillator (or alternatively, the circuit 10 may also include a crystal oscillator), and since the frequency stability of the crystal oscillator is good, the reference clock pulse signal T with higher stability can be obtained by properly designing the phase-locked loop PLL _ref The performance of the circuit 10 for a time-to-digital converter TDC can also be guaranteed. In addition, since a higher frequency signal is generally required for the system clock, the reference clock pulse signal T from the external crystal needs to be supplied to the multiphase clock generating unit 14 _ref Frequency-doubled to higher frequency, outputting a synchronous clock signal T _pll To the counting unit 11 to meet the requirement of the system clock; at the same time, the frequency-multiplied synchronous clock signal T _pll As the time reference step of the coarse count information, it can be obtained (with respect to the reference clock signal T) _ref In terms of) thinnerAnd the particles are removed, so that the timing performance is better.

According to an embodiment of the present invention, the counting unit 11 should be a synchronous counter, otherwise the coarse counting information N _ c is erroneous due to the large output offset (skew) of the asynchronous counter. The maximum range of the counting unit 11 is the longest time interval from the Start signal Start to the Stop signal Stop that the TDC can quantize. The counting unit 11 is configured to count the synchronous clock signal T when the Start signal Start transitions (e.g. rising edge) _pll Counting is started and the count value of the counting unit 11 is Read when a transition (e.g., a rising edge) occurs in the first Read signal Read. According to a preferred embodiment of the invention, the Start signal Start is arranged to synchronize the clock signal T _pll A fixed phase difference is maintained to avoid metastability problems.

The counting clock of the counting unit 11 is the synchronous clock signal T after the frequency multiplication and locking of the multi-phase clock generating unit 14 _pll After the multi-phase clock generating unit 14 is locked, the internal feedback loop thereof filters the low-frequency noise of the Voltage Controlled Oscillator (VCO) in the loop, and the coarse counting information N _ c of the counting unit 11 does not accumulate the delay error, so that the problem of the open-loop oscillator-based TDC in the prior art is solved, and the wide range of the TDC is realized.

According to an embodiment of the present invention, the Stop signal Stop is an echo signal pulse received by the detector, and the synchronization unit 12 is triggered when a rising edge of the Stop signal Stop arrives. Triggered synchronizing unit 12 outputs and synchronizes clock signal T _pll The aligned first Read signal Read and the time residual signal Δ T for fine counting. The Stop signal Stop passes through the synchronization unit 12, and the Stop signal Stop and the synchronous clock signal T can be avoided or reduced _pll The problem of meta-stability caused by asynchronization ensures the accuracy of the coarse count information N _ c, and the time residual signal Δ T is at least larger than 1 coarse count time reference step, i.e. a synchronous clock signal T _pll The fine count unit for processing the time residual signal delta T can work normally. Specifically, as shown in FIG. 2, the Stop signal Stop and the synchronous clock signal T _pll Maintaining a fixed phase difference, first readingOutput signal Read and synchronous clock signal T _pll Is aligned (as shown by the long dashed line in fig. 2), the time duration from the time point of the transition of the Stop signal Stop (as shown by the short dashed line in fig. 2) to the time point of the readout of the counting unit 11 (as shown by the first long dashed line in fig. 2) is the value of the time residual signal Δ T.

According to an embodiment of the present invention, the circuit of the synchronization unit 12 is shown in fig. 3, and includes a third D flip-flop 121, an not gate 122, a first exclusive nor gate 123, a fourth D flip-flop 124, and a second exclusive nor gate 125.

Wherein, each device connection relation is as follows: the signal input terminal D of the third D flip-flop 121 is connected to the Stop signal Stop, and the clock input terminal C is connected to the synchronous clock signal T _pll A positive output terminal Q outputting the first readout signal and being connected to the signal input terminal D of the fourth D flip-flop 124, an input terminal of the first xor gate 123 and an input terminal of the second xor gate 125, respectively; reverse output terminal Q _b The Stop signal Stop is outputted to the clock input terminal C of the fourth D flip-flop 124, and is outputted to the other input terminal of the first xor gate 123 after passing through the inverter 122, and the first xor gate 123 outputs the time residual signal Δ T; the positive output terminal Q of the fourth D flip-flop 124 is connected to another input terminal of the second exclusive nor gate 125, and the Clear signal Clear is output from the second exclusive nor gate 125.

Wherein, the signal transmission process is as follows: the synchronization unit 12 receives a synchronization clock signal T _pll And a Stop signal Stop and outputs a first Read signal Read; the not gate 122 receives the Stop signal Stop and outputs the Stop signal Stop after inversion; the first xor gate 123 receives the first Read signal Read and an inverted signal of the Stop signal Stop and outputs a time residual signal Δ T; the fourth D flip-flop 124 receives the inverted synchronous clock signal T _pll And the first Read signal Read and output; the second xor gate 125 receives the first Read signal Read and the output signal of the fourth D flip-flop 124, and outputs a Clear signal Clear to the third D flip-flop 121 for resetting the third D flip-flop 121 and thus restoring the synchronizing unit 12 to an initial state.

Further described from the signal timing, stop signal Stop and synchronization time, in conjunction with fig. 2 and 3Clock signal T _pll After synchronization, the first Read signal Read is output, the rising edge of which is in accordance with the synchronous clock signal T _pll And (6) synchronizing. The first Read signal Read and the inverted signal of the Stop signal Stop are processed by an exclusive nor operation to output a time residual signal delta T, the rising edge of the time residual signal delta T is aligned with the rising edge of the Stop signal Stop, the falling edge of the time residual signal delta T is aligned with the synchronous clock signal T _pll Is aligned with the rising edge of the first Read signal Read, the falling edge of the first Read signal Read is aligned with the synchronous clock signal T _pll Are aligned. The time residual signal delta T is subjected to fine counting quantization by the signal conversion unit 13 to obtain fine counting information; the first Read signal Read will Read the output of the counting unit 11 at the current time as the rough count information measured by the Stop signal Stop. Then, the first Read signal Read and the synchronous clock signal T _pll And performing exclusive OR operation on the synchronized output signal and the first Read signal Read, and outputting a Clear signal Clear for clearing the state of the internal node of the current measurement. After the first Read signal Read and the time residual signal Δ T are generated, a Clear signal Clear is output through the fourth D flip-flop 124 and the second xor gate 125 for resetting the third D flip-flop 121, i.e., restoring the synchronization unit 12 to the initial state, and then waiting for the next Stop signal Stop from the detector. The output signal of the D flip-flop is not only related to the input signal but also related to the original output signal, so that it is reset by the Clear signal Clear, and its memory function is cleared to ensure the accuracy of the next measurement.

According to an embodiment of the present invention, the signal conversion unit 13, as shown in fig. 4, includes a signal generator 131, a plurality of sample-and-hold circuits 132, a first sub-decoder 133, and a second sub-decoder 134.

Wherein the signal generator 131 is configured to receive the time residual signal Δ T and generate a sampling switch control signal Sample, a second Read signal Read _ I, and a third Read signal Read _ T; the plurality of Sample-and-hold circuits 132 are configured to receive the multiphase clock signal phi < n-1:0> and the sampling switch control signal Sample, and output first phase information sl < I > corresponding to the second Read signal Read _ I, where I is used to represent the Read ith phase state code, and sl < I > corresponds to the n-bit temperature code included in the phase state code; and second phase information st < j > corresponding to the third Read signal Read _ t, wherein j is used for representing the Read j-th phase state code, and st < j > corresponds to the temperature code of n bits contained in the phase state code.

Fig. 5 shows a schematic diagram of a signal conversion unit according to an embodiment of the present invention, and preferably, the signal conversion unit 13 further includes a D flip-flop 135 and a D flip-flop 136. With reference to fig. 2, further described from the signal timing sequence, the sampling switch control signal sample and two internal Read signals, i.e., the second Read signal Read _ l and the third Read signal Read _ T, are generated according to the rising edge and the falling edge of the time residual signal Δ T for reading the multiphase clock signal phi at the current time<n-1:0>Corresponding phase state sl<i>And st<j>Converted into binary codes tdc _ l by the first sub-decoder 133 and the second sub-decoder 134, respectively<m-1:0>And tdc _ t<m-1:0>Where m is a binary bit width of a fine count, and then passes through a D flip-flop 135 and a D flip-flop 136, respectively, to synchronize the clock signal T _pll And (4) sampling the rising edge, and synchronously outputting the first counting information N _ l and the second counting information N _ t. Where m is the bit width of the decoder output signal, i.e., the fine count bit width. And finally processed by a time decoder 15. Refer to equations (1) and (2) described above. The signal conversion unit 13 is completely composed of a digital circuit, and has a small area and low static power consumption.

Fig. 6 shows a schematic diagram of a sample-and-hold circuit of an embodiment of the present invention, and the sample-and-hold circuit 132 includes a sampling switch 1321, a first D flip-flop 1322, and a second D flip-flop 1323.

The sampling switch 1321 is configured to receive a sampling switch control signal Sample, and control the connection or disconnection of the multiphase clock signal phi < n-1:0> to the first D flip-flop 1322 and the second D flip-flop 1323; the first D flip-flop 1322 receives the multi-phase clock signal phi < n-1:0> when the sampling switch 1321 is turned on, and outputs first phase information sl < i > at a rising edge of the second Read signal Read _ l; the second D flip-flop 1323 receives the multi-phase clock signal phi < n-1:0> when the sampling switch 1321 is turned on, and outputs second phase information st < j > at the rising edge of the third Read signal Read _ t.

According to an embodiment of the present invention, the sample-and-hold circuit 132 further comprises an amplifier 1324, the amplifier 1324 is coupled to the input terminal of the sampling switch 1321, and is configured to receive the multi-phase clock signal phi < n-1:0> and isolate the sampling interference, for example, prevent the signal in the sample-and-hold circuit from being transmitted to the outside of the circuit, etc.

In summary, the n sample-and-hold circuits 132 simultaneously receive the multi-phase clock signals phi < n-1:0>, and then output the first phase information sl < i > corresponding to the rising edge of the time residual signal and the second phase information st < j > corresponding to the falling edge.

Fig. 7 shows a timing diagram of the signal conversion unit according to an embodiment of the present invention, which is further described from the signal timing in conjunction with fig. 5 and 6, according to a preferred embodiment of the present invention, the signal generator 131 generates the sampling switch control signal Sample based on the rising edge and the falling edge of the time residual signal Δ T, and the second Read signal Read _ I corresponding to the rising edge and the third Read signal Read _ T corresponding to the falling edge. The sample and hold circuit 132 holds for a period of time after sampling the sample switch control signal sample to satisfy the setup time window limit of the D flip-flop, and also holds for a period of time after the internal read rising edge arrives to satisfy the hold time window limit of the D flip-flop. Specifically, the holding time of the sampling switch control signal Sample satisfies the time limit of the setup time window of the first D flip-flop 1322 and the second D flip-flop 1323, the holding time of the second Read signal Read _ l satisfies the time limit of the holding time window of the first D flip-flop 1322, and the holding time of the third Read signal Read _ t satisfies the time limit of the holding time window of the second D flip-flop 1323.

As shown in FIG. 7, the falling edge of the time residual signal Δ T is synchronized with the clock signal T _pll The rising edges being synchronized so that the second phase information st is obtained<j>And first phase information sl<i>Thereafter, by synchronizing clock signals T _pll First count information N _ l and second count information N are read out for at least one cycle of timeT, finally by a synchronous clock signal T _pll And sending out the rising edge to finish synchronization. Specifically, the first count information N _ l is Read at the time of transition of the second Read signal Read _ l (as indicated by a dotted line corresponding to a rising edge of the second Read signal Read _ l in fig. 7), the second count information N _ T is Read at the time of transition of the third Read signal Read _ T (as indicated by a dotted line corresponding to a rising edge of the third Read signal Read _ T in fig. 7), and the second count information N _ T is Read at the time of next synchronization clock signal T _pll The synchronous output is passed to subsequent circuitry, e.g., sample and hold circuitry 132, for processing when the rising edge of (c) arrives.

The fine count information N _ f quantized output and the time residual Δ T can be expressed by the following formula:

N_f＝N_ft-N_fl＝ΔT/t _lsb 。

the circuit principle of the counting unit 11, the synchronizing unit 12 and the signal converting unit 13 is described above, each unit receiving the synchronizing clock signal T _pll The signal conversion unit 13 also receives a multi-phase clock signal phi<n-1:0>. Synchronizing a clock signal T _pll And a multiphase clock signal phi<n-1:0>Are all generated by a multi-phase clock generation unit 14, the multi-phase clock generation unit 14 is a main module of high-precision TDC fine count information, between two clock signals of adjacent phases, e.g. phi<0>And phi<1>The minimum phase time difference is the minimum step length t of the signal conversion unit 13 _lsb A measurement time step smaller than the minimum gate delay can be generated by the coupled connection of the multi-phase ring oscillator. Each phase is decoded to binary system through a binary decoder, and the binary digit is the fine counting bit width. Wherein phi is<n>The signal being a synchronous clock signal T of the multi-phase clock generation unit 14 _PLL And then to the counting unit 11 and the synchronization unit 12. Specifically, the first phase information sl<i>After passing through the first sub-decoder 133 and the D flip-flop 135, outputting binary first count information N _ l, that is, a binary value of the phase state of the first count information N _ l corresponding to the current time (the time of the transition of the second Read signal Read _ I); second phase information st<j>After passing through the second sub-decoder 134 and the D flip-flop 136, the binary second count information N _ t is outputted, i.e., the second count information N _ t is outputtedThe two count information N _ t corresponds to a binary value of the phase state at the current time (the time when the third Read signal Read _ t transits).

In particular, the multi-phase clock generation unit 14 is based on the principle of outputting different phase shifted versions of the same clock frequency, including a multi-stage interpolatively coupled differential inverter unit. In other words, a plurality of differential inverter units are connected end-to-end in input and output to form a multi-phase clock generating unit 14, and the minimum phase time difference t can be determined based on the interpolation series of the differential inverter units, i.e. the number of differential inverter units _1sb And a multiphase clock signal phi<n-1:0>I.e. the synchronous clock signal T _pll The period of (c).

Fig. 8a shows a schematic diagram of a multi-phase clock generation unit of an embodiment of the invention, the multi-phase clock generation unit 14 comprising a 4-stage interpolatively coupled differential inverter unit 141:141-1, 141-2, 141-3 and 141-4. Each differential inverter cell 141 includes a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal, and an inverting output terminal. The phase difference of the non-inverting output terminal + of two adjacent differential inverter units 141 is 45 °, the phase difference of the non-inverting input terminal and the inverting input terminal of each differential inverter unit 141 is 180 °, the phase difference of the non-inverting input terminal and the non-inverting output terminal is 45 °, and the phase difference of the inverting input terminal and the inverting output terminal is 45 °. Finally, the multi-PHASE clock generation unit 14 outputs 8 clock signals with the same period and different PHASEs, PHASE _0, PHASE _45 … … PHASE _315, as shown in fig. 8b, that is, the multi-PHASE clock signal phi output by the multi-PHASE clock generation unit 14<7:0>(n =8 for 8 phases). Within one clock cycle, comprising 8 PHASE changes, the interval between two adjacent PHASE changes is one eighth of the clock cycle, for example, the time interval between PHASE _0 and PHASE _45 (as shown by the long dashed line and the dotted line in fig. 8 b), i.e. the minimum PHASE time difference t _1sb . The total delay of the 4-stage interpolatively coupled differential inverter units 141 is approximately equal to the multi-phase clock signal phi<n-1:0>The period of (c).

Fig. 9 shows a circuit schematic of a multi-phase clock generation unit of another embodiment of the present invention, the multi-phase clock generation unit 14 comprises a 7-stage interpolatively coupled differential inverter unit 141:141-1, 141-2 … … and 141-7. Each differential inverter unit 141 includes three non-inverting inputs, three inverting inputs, a non-inverting output, and an inverting output. Finally, the multiphase clock generation unit 14 outputs 14 clock signals with the same period and different phases, phi <0>, phi <1>, phi <2> … … phi <13>.

According to a preferred embodiment of the present invention, the differential inverter unit 141 may include a plurality of delay units of different phases, and the delay units of the respective phases may have different weight configurations.

For example, as shown in fig. 10, the differential inverter unit 141 includes delay units 1411 of four phases: 1411-1, 1411-2, 1411-3, and 1411-4. Among them, the delay unit 1411 illustrated in fig. 10 is a schematic block, and does not mean that it is implemented by only one inverter. In practice, the delay unit 1411 of each phase may include one or more inverters (not shown). Preferably, the number of inverters included in each delay unit 1411 is k in proportion to the weight configuration<3>:k<2>:k<1>:k<0>1<0>Comprising an inverter; the weight of the second delay unit 1411-2 is k<1>Comprising an inverter; the third delay cell 1411-3 has a weight of k<2>Comprising two inverters; the fourth delay cell 1411-4 has a weight of k<3>And includes four inverters. The inverting input and inverting output are configured the same as the non-inverting input and non-inverting output. The minimum phase time difference t may be determined based on the weight configuration of the inverters and the interpolation series of the differential inverter unit 141 _1sb And a multiphase clock signal phi<n-1:0>The period of (c).

Those skilled in the art will appreciate that the number of inverters included in the delay unit 1411 is only required to satisfy the weight ratio condition, and is not limited to the above example. For example, also k <3>: k <2>: k <1>: k <0> = 4. And will not be described in detail herein.

Specifically, as shown in fig. 10, the multi-phase clock generation unit 14 is composed of a 7-stage differential inverter unit 141, and can provide 14 phases, which are decoded to a standard binary after passing through the signal conversion unit 13. The input of the first sub-decoder 133 and the second sub-decoder 134 is the phase state value phi <13> (corresponding to N = 14), the output is a binary value of 4 bits (i.e., m =4, which is the bit width of the fine count information N _ f, i.e., the bit width of the first count information N _ l and the second count information N _ T), and the difference between the first count information N _ l and the second count information N _ T of the binary value constitutes the fine count information N _ f, thereby obtaining the value of the time residual signal Δ T. Expressed by the formula:

N_f＝N_t-N_l＝ΔT/t _lsb

as shown in table 1, when the interpolation stage number of the differential inverter unit 141 is 7 stages, 14 phase signals (phi <0>, phi <1>, phi <2> … … phi <13 >) can be generated, wherein 7 phase signals (for example, phi <0>, phi <1> … … phi <6 >) are inverted signals of the other 7 phase signals (for example, phi <7>, phi <8> … … phi <13 >). Therefore, only the phase state values phi <6:0> corresponding to 7 of the 14 phase signals output after being sampled by the sample-and-hold circuit 132 are listed in table 1, and the phase state values phi <13> (substantially, the inverses of the phase state values phi <6:0 >) corresponding to the other 7 inversed signals are omitted.

The 14 phase signals have 14 phase state codes, for example, the phase code corresponding to code =1 is 0000001, the decoded output binary value is 0000, the phase code corresponding to code =2 is 00000011, the decoded output binary value is 0001, and so on, the phase code corresponding to code =14 is 00000000, and the decoded output binary value is 1101.

TABLE 1

phi<0>	phi<1>	phi<2>	phi<3>	phi<4>	phi<5>	phi<6>	code	tdc<3:0>
									1	0	0	0	0	0	0	1	0000
1	1	0	0	0	0	0	2	0001
									1	1	1	0	0	0	0	3	0010
1	1	1	1	0	0	0	4	0011
									1	1	1	1	1	0	0	5	0100
1	1	1	1	1	1	0	6	0101
									1	1	1	1	1	1	1	7	0110
0	1	1	1	1	1	1	8	0111
									0	0	1	1	1	1	1	9	1000
0	0	0	1	1	1	1	10	1001
									0	0	0	0	1	1	1	11	1010
0	0	0	0	0	1	1	12	1011
									0	0	0	0	0	0	1	13	1100
0	0	0	0	0	0	0	14	1101

Time intervals of adjacent phases, i.e. minimum phase time difference t _1sb The interpolation order and the clock period of the differential inverter unit 141 are related, for example, when a 7-stage 14-phase ring oscillator is used, the clock period is 2ns, and the minimum phase time difference t _1sb Is 2ns/14 ≈ 140ps, and under the current process, the actual circuit setup is slightly larger than 140ps, for example 150ps. The minimum phase time difference that can be provided under a 180nm CMOS process is, for example, 40ps in relation to its clock period.

As shown in the above table, for example, if the phase code output corresponding to the rising edge of the second Read signal Read _ l is 3, the first count information N _ l is 0010, the phase code output corresponding to the rising edge of the third Read signal Read _ T is 6, the second count information N _ T is 0101, and the minimum phase time difference is 150ps, the time residual Δ T is:

ΔT＝(N_t-N_l)*t _lsb ＝3*150ps＝450ps。

the value 3 is the difference between the two phase code codes and is actually calculated directly in the time decoder 15 from the binary values of the first count information N _ l and the second count information N _ t.

In summary, the multi-phase clock generation unit 14 is described with reference to two embodiments, and those skilled in the art will understand that the present invention does not limit the number and cascade relationship of the differential inverter units 141 included in the multi-phase clock generation unit 14, and that it is within the scope of the present invention as long as the multi-phase clock signals can be generated.

Fig. 11 shows a circuit block diagram of an embodiment of the invention, the circuit 20 comprising a coarse counting block 21, a plurality of fine counting blocks 22 and a multi-phase clock generation unit 14. The counting unit 11 forms a coarse counting module 21, and a synchronization unit 12 and a signal conversion unit 13 form a fine counting module 22. For each of the fine count modules 22: respectively receiving the stop signals stop to output the first count information N _ l and the second count information N _ t corresponding to the stop signals stop, and outputting the corresponding first read signal read to the coarse counting module 21, so that the coarse counting module 21 reads the coarse count information N _ c corresponding to the first read signal read according to the start signal start obtained before.

Specifically, the fine count module 22-1 receives the stop signal stop ₁ Output and stop signal stop ₁ Corresponding first count information nl ₁ And second count information nt ₁ And outputs a corresponding first readout signal r to the coarse counting module 21 ₁ So that the coarse counting module 21 can read out the first readout signal r according to the start signal start obtained before ₁ Corresponding coarse count information N _ c1; the fine counting module 22-2 receives the stop signal stop ₂ Output and stop signal stop ₂ Corresponding first count information nl ₂ And second count information nt ₂ And outputs a corresponding first read signal r to the coarse count block 21 ₂ So that the coarse counting module 21 can read out the first readout signal r according to the start signal start obtained before ₂ Corresponding coarse count information N _ c2; by analogy, the fine count module 22-n receives the stop signal stop _n Output and stop signal stop _n Corresponding first counting information nl _n And second count information nt _n And outputs a corresponding first read signal r to the coarse count block 21 _n So that the coarse counting module 21 can read out the first readout signal r according to the start signal start obtained before _n Corresponding coarse count information N _ cn;

the counting unit 11 includes a synchronous counter 111, and according to a preferred embodiment of the present invention, the counting unit 11 further includes a plurality of D flip-flops 112, and the plurality of D flip-flops 112 are coupled to the synchronous counter 111 and configured to respectively receive the corresponding first readout signals read and output corresponding coarse count information N _ c. Specifically, the synchronous counter 111 receives a start signal start, and the D flip-flop 112-1 receives a first readout signal r ₁ Outputting corresponding rough counting information N _ c1; d flip-flop 112-2 receives first readout signal r ₂ Outputting the corresponding coarseCount information N _ c2; by analogy, the D flip-flop 112-n receives the first readout signal r _n And outputs the corresponding coarse count information N _ cn.

The multiphase clock signals phi < n-1:0> are generated by a ring oscillator inside the multiphase clock generation unit 14. The multi-phase clock generating unit 14, the coarse counting module 21 and the plurality of fine counting modules 22 constitute a circuit 20, and the circuit 20 may be integrated into one chip. The multi-phase clock signals phi < n-1:0> are transmitted to each fine counting module 22 close to each external detector in the chip, so that the time reference step length of all the fine counting modules 22 is guaranteed not to drift along with temperature and process deviation, the problem of inconsistency of the TDCs at different positions is fundamentally solved, and the simultaneous measurement of a plurality of TDCs can be supported.

For the area array type detector and the array type detector, as shown in fig. 11, the multi-path detector only needs to copy the synchronization unit 12 and the signal conversion unit 13, because the multi-phase clock generation unit 14 can be shared, the circuit area and the power consumption are much smaller than those of the multi-group multi-phase clock generation unit 14, because most of the multi-path detectors are digital circuits, the static power consumption of the solution of the multi-path detector is very low, and the quantization consistency of Stop signals Stop of different detectors is very good. For example, in a 180nm CMOS process, the sum of the two holding times is greater than 500ps, i.e. the duration of the high level of the sampling switch control signal sample, and the high levels of the second Read signal Read _ l and the third Read signal Read _ T are also maintained for a period of time, resulting in a "dead time" of less than 2ns for the whole sampling system, but because the duration of the time residual signal Δ T at the output of the synchronization unit 12 is greater than the duration of the synchronization clock signal T _pll 1 cycle, so it does not affect the next quantization of the system, as shown in fig. 7.

In summary, the circuit designed by the invention can realize wide range and high precision, and is suitable for the TDC system in the array type laser radar or the area array type laser radar, wherein the wide range is realized by the counting unit 11, and the high precision is realized by the synchronization unit 12, the signal conversion unit 13 and the multi-phase clock generation unit 14.

The present invention also provides a lidar, as shown in fig. 12, the lidar 30 including:

a transmitting unit 31, the transmitting unit 31 being configured to transmit a detection laser beam for detecting a target object;

a receiving unit 32, wherein the receiving unit 32 is configured to receive the echo reflected by the detection laser beam on the target object and convert the echo into an electrical signal; and

the circuit 10 as described above, the circuit 10 being coupled to the transmitting unit 31 and the receiving unit 32 to determine the time of flight of the echo; wherein, when the transmitting unit 31 transmits a detection laser beam, a Start signal Start is sent to the circuit 10, and when the receiving unit 32 receives an echo signal, a Stop signal Stop is sent to the circuit 10.

The present invention also provides a method for measuring time by a circuit, as shown in fig. 13, the method 100 includes:

in step S101: when the counting unit 11 receives the Start signal Start, it starts to synchronize the clock signal T _pll Counting is carried out;

in step S102: receiving the Stop signal Stop and said synchronous clock signal T by the synchronization unit 12 _pll Generating a first Read signal Read and outputting it to the counting unit 11, and outputting a time residual signal Δ T of the first Read signal Read with respect to the Stop signal Stop;

in step S103: when the counting unit 11 receives the first Read signal Read, it outputs coarse counting information N _ c; and

in step S104: the time residual signal delta T and the multi-phase clock signal phi < N-1:0> are received through the signal conversion unit 13, the time residual signal delta T is quantized based on the phase state of the multi-phase clock signal phi < N-1:0>, and fine count information N _ f is output.

According to a preferred embodiment of the present invention, wherein said step S101 further comprises: by means of the counting unit 11, the synchronous clock signal T is counted when the Start signal Start makes a transition _pll Starting counting; the step S103 further includes: the counting unit 11 sends the first Read signal ReadFor the synchronous clock signal T at the time of transition _pll And outputting the rough counting information N _ c.

According to a preferred embodiment of the present invention, wherein the step S104 further comprises: the signal conversion unit 13 quantizes the temporal residual signal Δ based on the phase state of the multi-phase clock signal phi < N-1:0> to obtain first count information N _ l corresponding to a rising edge of the temporal residual signal Δ T and second count information N _ T corresponding to a falling edge of the temporal residual signal Δ; determining the fine count information N _ f based on the first count information N _ l and second count information N _ t; wherein,

the length of the time residual signal DeltaT is greater than the period of the multi-phase clock signal phi < n-1:0 >;

the rising edge of the time residual signal Δ T is aligned with the rising edge of the Stop signal Stop, the falling edge of which is aligned with the synchronous clock signal T _pll Is aligned with the falling edge of the first Read signal Read and the synchronous clock signal T _pll Are aligned.

According to a preferred embodiment of the present invention, further comprising:

the signal conversion unit 13 receives the multi-phase clock signal phi from the multi-phase clock generation unit 14<n-1:0>The Start signal Start is configured to synchronize the clock signal T _pll Maintaining a fixed phase difference; the multi-phase clock generation unit 14 comprises a plurality of ring oscillators connected in parallel in a weight configuration, a minimum phase time difference being determined based on the weight configuration and the number of parallel stages.

According to a preferred embodiment of the present invention, further comprising:

s105: the time decoder 15 determines time difference information between the Start signal Start and the Stop signal Stop through the coarse count information N _ c and the fine count information N _ f based on the period of the multi-phase clock signal phi < N-1:0> and the minimum phase time difference.

According to a preferred embodiment of the present invention, wherein said steps S101-103 are performed synchronously with step S104.

According to a preferred embodiment of the present invention, the method 100 is implemented by the circuit 10 as described above.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (26)

1. A circuit usable with a time-to-digital converter, comprising:

the counting unit is configured to start counting the synchronous clock signals after receiving the starting signal and output coarse counting information according to the first readout signal;

a synchronization unit configured to output the first readout signal to the counting unit and output a time residual signal of the first readout signal and the stop signal to a signal conversion unit according to a stop signal and the synchronization clock signal; and

the signal conversion unit is configured to receive the time residual signal and the multi-phase clock signal, and quantize the time residual signal based on a phase state of the multi-phase clock signal to obtain fine count information.

2. The circuit of claim 1, wherein the signal conversion unit is configured to quantize the temporal residual signal based on phase states of the multi-phase clock signals to obtain first count information corresponding to rising edges of the temporal residual signal and second count information corresponding to falling edges of the temporal residual signal; determining the fine count information based on the first count information and the second count information.

3. The circuit of claim 1, wherein the length of the temporal residual signal is greater than the period of the multi-phase clock signal.

4. The circuit of claim 1, further comprising a multi-phase clock generation unit that receives a reference clock signal and outputs a multiplied synchronous clock signal and a multi-phase clock signal, the counting unit, the synchronization unit, and the signal conversion unit receiving the synchronous clock signal from the multi-phase clock generation unit while the signal conversion unit receives the multi-phase clock signal from the multi-phase clock generation unit, wherein the synchronous clock signal and the multi-phase clock signal have the same frequency.

5. The circuit of claim 4, the multi-phase clock generation unit comprising a multi-stage interpolatively coupled differential inverter unit, a minimum phase time difference and a period of the multi-phase clock signal being determinable based on an interpolation stage number.

6. The circuit of claim 5, wherein the differential inverter unit comprises four phases of delay units, the four delay units comprising a number of inverters configured by a weight of 4.

7. The circuit of claim 5, further comprising a time decoder that determines time difference information between the start signal and the stop signal from the coarse count information and the fine count information based on a period of the multi-phase clock signal and the minimum phase time difference.

8. The circuit of claim 1, the counting unit comprising a synchronous counter configured to start counting the synchronous clock signal upon a transition of the start signal, read counting the synchronous clock signal upon a transition of the first readout signal, and output coarse count information.

9. The circuit of claim 1, wherein the start signal is configured to maintain a fixed phase difference from the synchronous clock signal.

10. The circuit of claim 2, wherein the signal conversion unit comprises a signal generator, a plurality of sample-and-hold circuits, a first sub-decoder, and a second sub-decoder, wherein,

a signal generator configured to receive the time residual signal and generate a sampling switch control signal, a second readout signal, and a third readout signal;

a sample-and-hold circuit configured to receive the multiphase clock signal and the sampling switch control signal, and output first phase information corresponding to a second readout signal, and second phase information corresponding to a third readout signal;

a first sub-decoder configured to receive the second readout signal and decode the first phase information to output the first count information; and

a second sub-decoder configured to receive the third readout signal and decode the second phase information to output the second count information.

11. The circuit of claim 10, wherein the signal generator generates the sampling switch control signal based on rising and falling edges of the temporal residual signal, and a second sense signal corresponding to the rising edge and a third sense signal corresponding to the falling edge.

12. The circuit of claim 10, wherein the sample and hold circuit comprises: a sampling switch, a first D flip-flop, and a second D flip-flop, wherein,

the sampling switch is configured to receive the sampling switch control signal and control the connection or disconnection of the multi-phase clock signal to the first D trigger and the second D trigger;

the first D flip-flop receives the multi-phase clock signal when the sampling switch is connected and outputs the first phase information at the rising edge of the second reading signal; and

and the second D trigger receives the multi-phase clock signal when the sampling switch is connected and outputs the second phase information at the rising edge of the third reading signal.

13. The circuit of claim 12, the sample and hold circuit further comprising an amplifier coupled to the input of the sampling switch configured to receive the multi-phase clock signal and isolate sampling glitches.

14. The circuit of claim 10, the hold time of the sampling switch control signal satisfying the time limit of the first and second D flip-flops to establish the time window, the hold time of the second read signal satisfying the time limit of the first D flip-flop hold time window, the hold time of the third read signal satisfying the time limit of the second D flip-flop hold time window.

15. The circuit of claim 1, the synchronization unit comprising:

a third D flip-flop configured to receive the synchronous clock signal and the stop signal and output a first readout signal;

a NOT gate configured to receive the stop signal and output the signal after inversion;

a first exclusive nor gate coupled to the third D flip-flop and the not gate, configured to receive the first readout signal and an inverted signal of the stop signal and output a time residual signal;

a fourth D flip-flop coupled to the third D flip-flop, configured to receive and output the synchronous clock signal and the first readout signal; and

a second exclusive nor gate coupled to the fourth D flip-flop and the third D flip-flop, configured to receive the first readout signal and an output signal of the fourth D flip-flop, and output a clear signal to the third D flip-flop, for resetting the third D flip-flop to restore the synchronization unit to an initial state.

16. The circuit of claim 15, the time residual signal having a rising edge aligned with a rising edge of the stop signal and a falling edge aligned with a rising edge of the synchronous clock signal, the first readout signal having a falling edge aligned with a rising edge of the synchronous clock signal.

17. A circuit according to any of claims 1-16, the counting unit constituting a coarse counting module, the synchronization unit and the signal conversion unit constituting a fine counting module, wherein the circuit may comprise a plurality of fine counting modules, for each fine counting module:

respectively receiving respective stop signals to output first count information and second count information corresponding to the stop signals, and,

and outputting a corresponding first reading signal to the rough counting module, so that the rough counting module reads out rough counting information corresponding to the first reading signal according to the starting signal obtained before.

18. The circuit of claim 17, the counting unit further comprising a plurality of D flip-flops coupled to the synchronous counter and configured to receive respective corresponding first readout signals and output corresponding coarse count information.

19. A lidar comprising:

a transmitting unit configured to emit a detection laser beam for detecting a target object;

a receiving unit configured to receive an echo reflected by the detection laser beam on a target object and convert the echo into an electric signal; and

the circuit of any one of claims 1-18, coupled to the transmit unit and the receive unit to determine a time of flight of the echo; wherein, when the transmitting unit transmits the detection laser beam, a start signal is sent to the circuit, and when the receiving unit receives an echo signal, a stop signal is sent to the circuit.

20. A method of measuring time by a circuit, comprising:

s101: when the counting unit receives the initial signal, the synchronous clock signal is counted;

s102: receiving a stop signal and the synchronous clock signal through a synchronization unit, generating a first readout signal and outputting the first readout signal to the counting unit, and outputting a time residual signal of the first readout signal relative to the stop signal;

s103: when the counting unit receives the first reading signal, coarse counting information is output; and

s104: and receiving the time residual signal and the multi-phase clock signal through a signal conversion unit, quantizing the time residual signal based on the phase state of the multi-phase clock signal, and outputting fine counting information.

21. The method of claim 20, wherein the step S101 further comprises: starting counting the synchronous clock signal by the counting unit when the start signal transits; the step S103 further includes: outputting, by the counting unit, the coarse count information to the synchronous clock signal when a transition occurs in the first readout signal.

22. The method of claim 20, wherein the step S104 further comprises: the signal conversion unit quantizes the time residual signal based on phase states of the multi-phase clock signals to obtain first count information corresponding to rising edges of the time residual signal and second count information corresponding to falling edges of the time residual signal; determining the fine count information based on the first count information and the second count information; wherein,

the length of the time residual signal is greater than the period of the multi-phase clock signal;

the time residual signal has a rising edge aligned with a rising edge of the stop signal, a falling edge aligned with a rising edge of the synchronous clock signal, and a falling edge of the first readout signal aligned with a rising edge of the synchronous clock signal.

23. The method of claim 20, further comprising:

the signal conversion unit receives the multi-phase clock signal from a multi-phase clock generation unit, and the start signal is configured to maintain a fixed phase difference with the synchronous clock signal; the multi-phase clock generation unit comprises a plurality of ring oscillators connected in parallel and configured according to weight, and the minimum phase time difference is determined based on the weight configuration and the parallel series.

24. The method of claim 23, further comprising:

s105: the time decoder determines time difference information between the start signal and the stop signal from the coarse count information and the fine count information based on the period of the multi-phase clock signal and the minimum phase time difference.

25. The method of claim 20, wherein the steps S101-103 are performed in synchronization with step S104.

26. The method of any one of claims 20-25, wherein the method is implemented by a circuit of any one of claims 1-18.

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