CN115241179A - Chip package structure - Google Patents

Abstract

The application discloses chip packaging structure, it includes: a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit; at least one chip set, the chip set including a control chip and a device chip; wherein the control chip and the device chip are flip-chip bonded, and the control chip or the device chip is flip-chip bonded to the connection side; or the control chip and the device chip are in flip-chip bonding with the connecting side without using wire bonding in the prior art, so that the whole thickness of the chip packaging structure is only determined by the thicknesses of the substrate, the control chip and the device chip, and the whole thickness of the chip packaging structure is reduced.

Description

Chip package structure

technical field

The present application relates to the field of chip packaging, and in particular, to a chip packaging structure.

Background technique

In the existing chip packaging structure, the chip is bonded to the lead frame. Both the chip and the lead frame have a large number of conductive contacts. The conductive contacts on the chip are wire-bonded with the corresponding conductive contacts on the lead frame, and then pass the electrical signal transmission path preset on the lead frame to the outside of the chip package to complete the process from the outside of the chip package to the inside of the chip package. direct electrical signal transmission.

Wire bonding is to use gold wire (or copper wire, aluminum wire) to connect the conductive contacts of the chip and the lead frame. When hitting the wire, first let the gold wire form a gold ball at the bottom. Then the gold balls are pressed onto the contacts of the chip, and then soldered to the contacts by applying pressure or changing the temperature, which forms a dot on the contacts, and then the gold wire is pulled up and moved to the Bonding is done above the lead frame.

Since the gold wire is arranged in a bent state between the chip and the lead frame, and is bent above the chip, the thickness of the chip structure after packaging is the distance between the bottom surface of the lead frame and the highest point of the gold wire, which leads to packaging The thickness of the latter chip is thicker, which is not conducive to the thinning of the chip.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present application is to provide a chip packaging structure, which can make the thickness of the packaged chip smaller.

In order to solve the above-mentioned technical problems, the technical scheme adopted in this application is:

A chip packaging structure, comprising:

a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit;

at least one chipset, the chipset includes a control chip and a device chip;

Wherein, the control chip and the device chip are flip-chip welded, and the control chip or the device chip is flip-chip welded to the connection side;

Alternatively, both the control chip and the device chip are flip-chip welded to the connection side.

According to an embodiment of the present application, a blocking protrusion adjacent to the chip set is protruded on the connection side.

According to an embodiment of the present application, the blocking protrusions are symmetrically arranged on the connection side, the chip set is disposed between the blocking protrusions, and between the blocking protrusions and the chip set with gaps.

According to an embodiment of the present application, the blocking protrusion is configured as a frame surrounding the chip set.

According to an embodiment of the present application, the substrate further includes a side end surface connected to the connection side, and the stop protrusion is flush with the side end surface at an outer surface away from the chip set.

According to an embodiment of the present application, the thickness of the blocking protrusion is not less than half of the minimum thickness in the chip set.

According to an embodiment of the present application, the substrate is further provided with a hole portion, and the hole portion is configured as a blind hole opened on the connection side, or the hole portion is configured to penetrate through the connection side and the connection side. Vias on the conductive side.

According to an embodiment of the present application, the control chip or the device chip facing the connection side in each of the chip sets is accommodated in the hole portion.

According to an embodiment of the present application, the control chip is flip-chip bonded to the connection side, the device chip is flip-chip bonded to the side of the control chip facing the connection side, and the device chip is accommodated at the connection side. inside the hole.

According to an embodiment of the present application, the control chip is flip-chip bonded to the connection side, and the device chip is flip-chip bonded to a side of the control chip away from the connection side.

The beneficial effects of the present application are: the chip package structure provided by the present application, the control chip and the device chip in the chip set are flip-chip welded, and the control chip or the device chip is flip-chip welded with the connection side; or, both the control chip and the device chip are connected to Side flip-chip bonding without using wire bonding in the prior art, so that the wires in the prior art can be eliminated, so that the overall thickness of the chip package structure is only determined by the thickness of the substrate, the control chip, and the device chip, thereby compressing The overall thickness of the chip package structure is adjusted to comply with the development trend of thin and light chips.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, under the premise of no creative work, other drawings can also be obtained from these drawings, wherein:

FIG. 1 is a schematic structural diagram of a first embodiment of a chip packaging structure provided by the present application;

FIG. 2 is a schematic structural diagram of a second embodiment of the chip packaging structure provided by the present application;

3 is a schematic structural diagram of a third embodiment of the chip packaging structure provided by the present application;

4 is a schematic structural diagram of a fourth embodiment of the chip packaging structure provided by the present application;

5 is a schematic structural diagram of a fifth embodiment of the chip packaging structure provided by the present application;

FIG. 6 is a schematic bottom view of the chip package structure of FIG. 5 .

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

CMOS is the abbreviation of Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor), which refers to a technology used in the manufacture of large-scale integrated circuit chips or chips made by this technology.

MEMS is the abbreviation of Micro-Electro-Mechanical System (Micro-Electro-Mechanical System), also known as micro-electromechanical system, micro-system, micro-machine, etc.

Please refer to FIGS. 1 to 4 . FIG. 1 is a schematic structural diagram of a first embodiment of the chip packaging structure provided by the present application; FIGS. 2 to 4 are specific embodiments of the chip packaging structure provided by the present application. In one aspect of the present application, a chip package structure 100 is provided. The chip package structure 100 includes a substrate 10 and at least one chip set 11 disposed on the substrate 10 . There may be multiple chipsets 11, which can be selected according to actual needs.

The substrate 10 has a connection side 10a and a conductive side 10b for connecting the chip package structure 100 with an electrical signal to an external circuit. The conductive side 10b and the connection side 10a are arranged opposite to each other at an interval. Of course, the conductive side 10b and the connection side 10a can also be arranged adjacent to each other. The connection side 10a is used for connecting with the chipset 11 . It can be understood that the substrate 10 can be used to carry the chipset 11, and can be a PCB board or a silicon substrate, which is not specifically limited herein.

The chip set 11 includes a control chip 12 (CMOS chip) and a device chip 13 (MEMS chip), wherein the control chip 12 and the device chip 13 are flip-chip bonded, and the control chip 12 is flip-chip bonded to the connection side 10a.

It should be noted that, in the chip package structure 100 provided in the present application, the device chip 13 and the connection side 10a may also be flip-chip welded; or, the control chip 12 and the device chip 13 may be flip-chip welded to the connection side 10a. 2 to 6 only show some embodiments of the chip package structure 100 provided by the present application, specifically, only some embodiments of flip-chip welding of the control chip 12 and the connection side 10a, the purpose of which is to control the The chip 12 and the connection side 10a are flip-chip welded as an example, so as to intuitively describe the specific structure of the chip package structure 100 provided in this application in this case. These drawings should not be taken as limiting the scope of the protection of this application.

It can be understood that when a chip set 11 includes a plurality of device chips 13 and a control chip 12 to be welded, in one embodiment, the plurality of device chips 13 may be stacked and welded to form an integrated device chip set; The control chips 12 are stacked and welded together to form a control chip group; then the outermost device chip 13 of the device chip group and the outermost control chip 12 of the control chip group are flip-chip welded. In another embodiment, a plurality of device chips 13 and control chips 12 may also be tiled.

Therefore, the control chip 12 and the device chip 13 in the chip package structure 100 of the present application are flip-chip welded, and the device chip 13 and/or the control chip 12 and the substrate 10 are also flip-chip welded, so that the device chip 13 and/or the substrate 10 are also flip-chip welded. Or the control chip 12 is soldered on the connection side 10a and connected with the substrate 10 by electrical signals. Therefore, the device chip 13 and/or the control chip 12 can be electrically connected to the external circuit through the electrical signal connection between the conductive side 10b of the substrate 10 and the external circuit. Therefore, the device chip 13 and/or the control chip 12 and the substrate 10 in the chip package structure 100 of the present application only need to be flip-chip bonded without using wire bonding in the prior art, so that the prior art can be eliminated so that the overall thickness of the chip package structure 100 is only determined by the thicknesses of the substrate 10 , the control chip 12 , and the device chip 13 , thereby compressing the overall thickness of the chip package structure 100 to conform to the trend of thinning chips.

Referring to FIG. 1 , in the first embodiment, the chip package structure 100 includes a chip set 11 , and the chip set 11 includes a control chip 12 and a device chip 13 . The control chip 12 is flip-chip bonded to the connection side 10 a of the substrate 10 . The device chip 13 is flip-chip bonded to the control chip 12, and is bonded to the side away from the connection side 10a. Flip-chip bonding can realize electrical signal connection and mechanical connection between the connectors through the connection of the solder joints 14 . The two sides of the control chip 12 are the device chip 13 and the substrate 10 respectively, which can avoid the substrate 10 from imposing various restrictions on the device chip 13, reduce the difficulty of optimizing the size and structure of the device chip 13, and improve its optimization space.

The substrate 10 further includes a side end face 10c connected to the connection side 10a, and the side end face 10c is used to define the size of the connection side 10a. In order to better protect the chip, when the chip set 11 is flip-chip welded on the connection side 10a of the substrate 10, the side end of the chip set 11 does not exceed the space defined by the plane where the side end face 10c is located, and can further compress the chip package structure 100 laterally. size, improving its optimization space.

It should be noted that the side end of the chipset 11 does not exceed the space defined by the plane where the side end face 10c is located, which mainly includes the following situations:

The projection of the control chip 12 on the device chip 13 covers the device chip 13, and the projection of the control chip 12 on the connection side 10a is in the connection side 10a. That is, the circumference of the control chip 12 is less than or equal to the circumference of the connection side 10 a , and the circumference of the device chip 13 is less than or equal to the circumference of the device chip 13 . For example, the periphery of the control chip 12 is wider than the device chip 13 , and the control chip 12 is flush with the side end surface 10 c of the substrate 10 .

The projection of the control chip 12 on the device chip 13 is in the device chip 13, and the projection of the device chip 13 on the connection side 10a is in the connection side 10a. That is, the circumference of the device chip 13 is smaller than the circumference of the connection side 10 a , and the circumference of the control chip 12 is smaller than the circumference of the control chip 12 .

It can be understood that, in other embodiments, the chip package structure 100 provided by the present application, when the device chip 13 is flip-chip welded to the connection side 10a; or, when the control chip 12 and the device chip 13 are both flip-chip welded to the connection side 10a; The chip set 11 and the substrate 10 also have various dimensional relationships as described above.

Specifically, in some specific embodiments, as shown in FIG. 1 , the substrate 10 is further provided with a hole portion 10d. More specifically, the hole portion 10d is a through hole, that is, the hole portion 10d not only penetrates through the connection side 10a, but also A conductive side 10b arranged opposite to the connection side 10a is penetrated. The hole portion 10 d is configured as a through hole, and can serve the purpose of heat dissipation of the chip set 11 .

In order to prevent the leakage of the solder from the hole portion 10d to the conductive side 10b when the control chip 12 and/or the device chip 13 are soldered to the substrate 10 and cause a short circuit problem, the hole portion 10d can also be configured as a blind hole, that is, a hole portion 10d extends through the connection side 10a and toward the conductive side 10b, but does not penetrate the conductive side 10b. Preferably, the position of the hole portion 10d is directly corresponding to the device chip 13, and the arrangement of the hole portion 10d does not hinder the flip-chip bonding between the chip and the connection side 10a.

It can be understood that, in other embodiments, in the chip package structure 100 provided by the present application, when the device chip 13 is flip-chip welded to the connection side 10a; or, the control chip 12 and the device chip 13 are both flip-chip welded to the connection side 10a; or , when a plurality of chip sets 11 are flip-chip soldered on the connection side 10a; in order to dissipate heat, the substrate 10 may also be provided with holes 10d of the same structure as described above corresponding to the chips.

Referring to FIG. 2 , FIG. 2 is a schematic structural diagram of a second embodiment of the chip packaging structure 100 provided by the present application. In order to further protect the chip set 11 flip-chip soldered on the connection side 10a of the substrate 10 from being impacted, the chip package structure 100 provided by the present application, in addition to the structure in the first embodiment, in the second embodiment, also Other protective structures provided on the substrate 10 are included.

Specifically, the substrate 10 further includes a stopper protrusion 15 protruding on the connection side 10a. In one structure, the stopper protrusion 15 is disposed along a symmetrical position on the connection side 10a, and surrounds the chipset 11 therein. There is a gap between the blocking protrusion 15 and the side end of the chip set 11 to facilitate the connection of the chip set 11 and the connection side 10a. The blocking protrusions 15 surrounding the chip set 11 can prevent other components from impacting the chip, and prevent harmful materials from entering from the side. In addition, when the chip set 11 is flip-chip soldered to the connection side 10 a of the substrate 10 , the solder will accumulate after encountering the stopper protrusion 15 , so that the problem of virtual soldering can also be avoided.

Specifically, in some specific embodiments, the stop protrusions 15 are provided along the symmetrical positions on the connection side 10a, which may be a pair of symmetrical stop protrusions 15, or multiple pairs of symmetrical stop protrusions. A plurality of pairs of stop protrusions 15 surround the side edge of the connecting side 10a. A pair of blocking protrusions 15 and a plurality of pairs of blocking protrusions 15 can be arranged at intervals to form a non-closed annular structure.

In some other specific embodiments, the blocking protrusion 15 can also form a frame connected end to end, and the frame surrounds the side of the connecting side 10a. The setting of the blocking protrusions 15 can be specifically selected according to the actual situation, and the frame can be in the shape of a rectangle, a circle, an ellipse, etc., which is not specifically limited here.

In some more specific embodiments, the outer surface of the blocking protrusion 15 and the side end surface 10c away from the chip set 11 are located on the same plane. That is, the outer side surface of the blocking protrusion 15 is flush with the side end surface 10 c of the base plate 10 .

As shown in FIG. 2 , the control chip 12 is flip-chip bonded to the connection side 10 a of the substrate 10 . The device chip 13 is flip-chip bonded to the control chip 12, and is bonded to the side away from the connection side 10a. Flip-chip bonding can realize electrical signal connection and mechanical connection between the connectors through the connection of the solder joints 14 . The blocking protrusion 15 is configured as a rectangular frame, and the blocking protrusion 15 is protruded from the connection side 10 a and surrounds the control chip 12 . A gap is left between the outer side surface of the control chip 12 and the inner side surface of the blocking protrusion 15 so that the control chip 12 can dissipate heat. The outer side surface of the stopper protrusion 15 is flush with the side end surface 10 c of the base plate 10 .

The blocking protrusions 15 play a role in protecting the control chip 12 , preventing harmful materials from contacting the control chip 12 from the side, or the harmful materials colliding with the control chip 12 . In addition, when the control chip 12 is soldered to the connection side 10 a of the substrate 10 , the solder will accumulate after encountering the stopper protrusion 15 , so that the problem of virtual soldering can be avoided.

It can be understood that, in order to better achieve the protective effect of the blocking protrusions 15 , the blocking protrusions 15 need to have a certain thickness in the protruding direction, specifically, for example, the thickness of the blocking protrusions 15 Not less than half of the minimum thickness in the chip set 11, or not less than half of the thickness of the chip flip-chip bonded to the connection side 10a. For example, the chip set 11 includes a control chip 12 and a device chip 13 that are flip-chip bonded to each other, and the control chip 12 is flip-chip bonded to the connection side 10 a .

It can be understood that, in other embodiments, the chip package structure 100 provided by the present application is when the device chip 13 is flip-chip welded to the connection side 10a; or, the control chip 12 and the device chip 13 are both flip-chip welded to the connection side 10a. At this time, the thickness of the blocking protrusions 15 in the protruding direction is not less than half of the device chip 13, preferably, the thickness of the device chip 13 is equal to that of the device chip 13; or the thickness of the blocking protrusions 15 in the protruding direction At least not less than the average thickness of the tiled chips, preferably equal to the maximum thickness of the tiled chips. It should be noted that, when the connection side 10a is provided with the stopper protrusion 15, there is a certain gap between the outer side surface of the chip directly flip-chip welded with the connection side 10a and the stopper protrusion 15, and the stacking chip has a certain gap. The size is related to the thickness of the stopper projection 15 . For example, in FIG. 2 , the blocking protrusions 15 and the control chip 12 have the same thickness, and the circumference of the device chip 13 may be smaller than the circumference of the control chip 12 or greater than or equal to the circumference of the control chip 12 .

3-5, in the third embodiment, the control chip 12 is flip-chip welded to the connection side 10a, the device chip 13 is flip-chip welded to the control chip 12, and the device chip 13 is flip-chip welded to the control chip 12 facing the substrate 10 side. That is, the substrate 10 and the device chip 13 are co-located on the same side of the control chip 12 . Besides, the chip package structure 100 in the third embodiment provided by the present application is the same as the chip package structure 100 in the first embodiment described above.

In order to further reduce the thickness of the chip package structure 100 . In the third embodiment, the device chip 13 is accommodated in the hole portion 10d. Specifically, the device chip 13 is placed in the hole portion 10d, and there is a gap between the outer side surface of the device chip 13 and the inner side surface of the hole portion 10d, and the device chip 13 accommodated in the hole portion 10d does not exceed the plane defined by the conductive side 10b. .

Therefore, the overall thickness of the chip package structure 100 can only be determined by the thickness of the substrate 10 and the thickness of the control chip 12 , that is, the overall thickness of the chip package structure 100 is the sum of the thickness of the substrate 10 and the thickness of the control chip 12 , Thus, the overall thickness of the chip package structure 100 is further compressed. In addition, since the substrate 10 and the device chip 13 are co-located on the same side of the control chip 12 , flip-chip welding can be performed on one side of the control chip 12 , which can effectively reduce the processing difficulty of the control chip 12 and avoid the use of the control chip 12 The complex process of double-sided electrical conduction reduces the manufacturing cost of the control chip 12 at the same time.

It can be understood that, in other embodiments, in the chip package structure 100 provided by the present application, when the device chip 13 is flip-chip welded with the connection side 10a; at this time, the control chip 12 can be accommodated in the hole 10d; or according to the hole 10d Each chip group 11 can accommodate a plurality of chips in the hole portion 10d with a depth of . That is, after the chip for connection in each chip set 11 is connected to the connection side 10a, the control chip 12 and/or the device chip 13 disposed on the side of the connection chip and facing the substrate 10 can be accommodated in the hole portion 10d, Thus, the overall thickness of the chip package structure 100 is further reduced.

Please refer to FIG. 4 and FIG. 5 in combination. The difference between the fourth embodiment and the third embodiment is that a stop protrusion 15 is protruded on the connecting side 10a. The arrangement of the stop protrusion 15 is the same as that of the second embodiment. In this way, the protection of the chips in the chip set 11 by the blocking protrusions 15 can be achieved, and the accommodating function of the holes 10d can be achieved to further reduce the thickness of the chip package structure 100, and the holes 10d can be used for heat dissipation.

It can be understood that, in other embodiments, in the chip package structure 100 provided by the present application, when the device chip 13 is flip-chip welded to the connection side 10a; or, the control chip 12 and the device chip 13 are both flip-chip welded to the connection side 10a; Alternatively, when a plurality of chip sets 11 are flip-chip welded on the connection side 10a; the substrate 10 can also be provided with the same structure as described above to correspond to the chips, and the features and advantages of flip-chip bonding, the stopper protrusion 15 and the hole 10d can be combined comprehensively. In order to improve the chip package structure 100 .

Please refer to FIG. 5 , in the fifth embodiment, the difference from the fourth embodiment is that the hole 10d can be configured as a blind hole opened on the connection side 10a, that is, the hole 10d penetrates through the connection side 10a and conducts electricity. Side 10b extends but does not penetrate conductive side 10b. In this way, there is isolation between the hole 10d and the conductive side 10b, which can effectively avoid the problem of short circuit caused by leakage of solder from the hole 10d to the conductive side 10b when the control chip 12 and/or the device chip 13 are soldered to the substrate 10 .

It can be understood that, in other embodiments, in the chip package structure 100 provided by the present application, when the device chip 13 is flip-chip welded to the connection side 10a; or, the control chip 12 and the device chip 13 are both flip-chip welded to the connection side 10a; Alternatively, when a plurality of chip sets 11 are flip-chip welded on the connection side 10a; the substrate 10 may also be provided with the same structure as described above to correspond to the chips.

Referring to FIG. 6 , in some specific embodiments, the substrate 10 is configured as a silicon substrate, and the connection side 10a is provided with a first contact portion (not shown in the figure), and the first contact portion is connected to the chip through the flip-chip bonding pads 14 Group 11 is electrically connected. The conductive side 10b is provided with a second contact portion 10e, and the second contact portion 10e is electrically connected to an external circuit. The first contact portion is electrically signal-connected to the second contact portion 10e.

The electrical signal connection between the first contact portion and the second contact portion 10e may be realized by means of TSV (Through Silicon Via, TSV). In this way, the first contact portion and the second contact portion 10e are respectively the two connection ends of the TSV, thereby shortening the electrical connection distance from the outside of the substrate 10 to the chip set 11 and reducing the extra parasitic capacitance and feedback resistance introduced by the electrical connection of the package. and other circuit characteristics, reducing the difficulty of circuit system optimization.

It can be understood that, multiple TSV structures can be correspondingly set according to actual requirements. As shown in FIG. 6 , four TSV structures are arranged in an array.

In some embodiments, the device chip 13 described above may have a MEMS resonator and a first electrode for receiving a resonator drive signal from the control chip 12 and a second electrode for outputting a resonator sensing signal to the control chip 12 . The resonator drive signal is used to drive the MEMS resonator into mechanical resonant motion, and the resonator sense signal is indicative of the mechanical resonant motion.

The control chip 12 described above may include a circuit for receiving the resonator sensing signal from the device chip 13 and generating the resonator driving signal based on the resonator sensing signal.

The control chip 12 may also include circuitry for generating a clock signal based on the resonator sensing signal and compensating the clock signal according to the temperature sensitivity of the MEMS resonator. Wherein, the circuit for compensating the clock signal according to the temperature sensitivity of the MEMS resonator includes a temperature sensor.

In another aspect of the present application, an electronic product is provided. The electronic product includes the chip packaging structure 100 of any of the above embodiments, and the chip packaging structure 100 will not be repeated here.

The terms "first", "second" and "third" in this application are only used for descriptive purposes and should not be understood as indicating the number of indicated technical features. Thus, a feature defined as "first", "second", "third" may expressly or implicitly include at least one of that feature. All directional indications (such as up, down, left, right, front, rear...) in the embodiments of the present application are only used to explain the relative positional relationship between components under a certain posture (as shown in the accompanying drawings). , motion situation, etc., if the specific posture changes, the directional indication also changes accordingly. Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

The above are only the embodiments of the present application, and are not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (10)

1. A chip package structure, comprising:

a substrate having a connection side and a conductive side for electrically connecting the chip package structure with an external circuit;

at least one chipset comprising a control chip and a device chip;

wherein the control chip and the device chip are flip-chip bonded, and the control chip or the device chip is flip-chip bonded to the connection side;

or the control chip and the device chip are in flip chip bonding with the connecting side.

2. The chip package structure according to claim 1, wherein the connection side is provided with a stopper protrusion adjacent to the chip set.

3. The chip package structure according to claim 2, wherein the stop protrusions are symmetrically disposed on the connection side, the chip set is disposed between the stop protrusions, and a gap is formed between the stop protrusions and the chip set.

4. The chip packaging structure according to claim 2, wherein; the stop protrusion is configured as a bezel that surrounds the chip set.

5. The chip package structure according to claim 2, wherein the substrate further includes a side end surface connected to the connection side, and the stopper projection is flush with the side end surface at an outer side surface away from the chip group.

6. The chip package structure according to claim 2, wherein the thickness of the stop protrusion is not less than half of the minimum thickness of the chip set.

7. Chip package according to any one of claims 1 to 6, characterized in that the substrate is further provided with a hole portion configured as a blind hole opening at the connection side or as a through hole passing through the connection side and the electrically conductive side.

8. The chip package structure according to claim 7, wherein the control chip or the device chip facing the connection side in each of the chip groups is accommodated in the hole portion.

9. The chip package structure according to claim 7, wherein the control chip is flip-chip bonded to the connection side, the device chip is flip-chip bonded to a side of the control chip facing the connection side, and the device chip is received in the hole portion.

10. The chip package structure according to any one of claims 1 to 6, wherein the control chip is flip-chip bonded to the connection side, and the device chip is flip-chip bonded to a side of the control chip away from the connection side.

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