CN115241131A - Optimal integration method for edge stress in multi-layer gate analog CMOS process and low voltage coefficient polycrystalline capacitor - Google Patents

Abstract

The invention discloses a multi-layer gate analog CMOS process edge stress optimization integration method and a low voltage coefficient polycrystalline capacitor. The method steps include: 1) forming an N-type well in the low-voltage coefficient integrated double polycrystalline capacitor region, and forming an N-type well in the area outside the N-type well Self-aligned P-type well; 2) depositing the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor; 3) depositing the first dielectric layer of the double polycrystalline capacitor, and realizing the edge protection layer of the lower electrode of the double polycrystalline capacitor production; 4) depositing the capacitor dielectric layer, and completing the production of the capacitor dielectric layer structure; the low voltage coefficient polycrystalline capacitor includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a field oxide layer, Sacrificial oxide layer, gate oxide layer, polycrystalline film layer, silicon dioxide dielectric layer, capacitor dielectric layer, low dielectric constant filling film layer, metal interconnection film layer, protective dielectric passivation layer outside the top metal bonding area; The patent improves the edge effect of dual poly capacitors and reduces the mechanical stress of integrated dual poly capacitors.

Description

Multilayer gate analog CMOS process edge stress optimized integration method and low voltage coefficient Crystal capacitor

technical field

The invention relates to the field of semiconductor integrated circuits, in particular to a method for optimizing and integrating edge stress of a multi-layer gate analog CMOS process and a low-voltage coefficient polycrystalline capacitor.

Background technique

In the field of semiconductor device manufacturing, analog CMOS integrated circuits are gradually developing towards high-speed and high-precision. The direct integration of dual polysilicon capacitors into the circuit is the development trend of equipment lightweight and miniaturization.

In particular, analog CMOS integrated circuits that are used for high-precision detection such as weather forecasting, ocean exploration, and polar scientific research and have complex working environments are required to be compatible with high and low voltage power supply voltage, high speed, high precision, low drift, low offset and other circuit performance. Development in the ultimate direction. These requirements put forward higher requirements for the organic combination of circuit design and process manufacturing art and science. Low voltage coefficient integrated double polycrystalline capacitors are widely used in the precise matching of charge redistribution ADCs and DACs that have strict requirements on voltage modulation effects due to their superior process compatibility. in the capacitor.

On the other hand, in analog CMOS integrated circuits containing low-voltage coefficient dual polycapacitors, the stress mismatch and electric field concentration caused by the fringing effect of the integrated polycapacitor significantly affect the grain regrowth in the polycrystalline thin layer, and the Impurity redistribution, grain depletion, and grain boundary size and shape have important effects on the electrical stability and long-term reliability of low-voltage coefficient integrated dual-poly capacitors.

Therefore, the use of effective process technology optimization can integrate the high mechanical stress caused by the edge effect of the low voltage coefficient double polycrystalline capacitor, and the local electric field concentration is to improve the high precision, high linear stability and long-term reliability of the analog integrated circuit. Important work in the direction of high speed, high precision and miniaturization.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a multi-layer gate simulation CMOS process edge stress optimization integration method, comprising the following steps:

1) Form an N-type well of the low-voltage coefficient integrated double polycrystalline capacitor region on the P-type substrate, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) Deposit a P1 angstrom-thick lower electrode polycrystalline film of the low-voltage coefficient integrated double-polycrystalline capacitor on the field oxide layer above the N-type well in the integrated low-voltage-coefficient double-polycrystalline capacitor region, and complete the N-type optical film. engraving and doping; wherein, the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor is used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) depositing the first layer of dielectric of the double polycrystalline capacitor with a thickness of d1 angstrom, and using the exposure etching process to realize the production of the edge protection layer of the lower electrode of the double polycrystalline capacitor;

6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and using an exposure etching process to complete the fabrication of the capacitor dielectric layer structure;

7) Complete the conventional process before simulating CMOS integrated circuit gate polycrystalline deposition;

8) depositing a P2 angstrom-thick MOS transistor gate polycrystalline film layer, and completing the MOS transistor gate polycrystalline doping;

9) The subsequent conventional process of the normal analog CMOS integrated circuit is completed.

Further, the method for depositing the P1 angstrom polycrystalline film layer, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low pressure chemical vapor deposition method.

Further, the dielectric coefficient of the first layer of the double polycrystalline capacitor is denoted as ε1, and the dielectric coefficient of the capacitor dielectric layer is denoted as ε2. ε1 and ε2 are constants.

Further, in step 1), before forming the N-type well, a layer of P-type epitaxy is grown on the P-type substrate, then the N-type well is formed on the P-type epitaxy, and the self-aligned P-type is formed in the area outside the N-type well trap.

Further, the subsequent conventional processes of the normal analog CMOS integrated circuit include source-drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

Further, conventional processes prior to gate polysilicon deposition of analog CMOS integrated circuits include sacrificial oxidation, channel implantation, exposure and etching, and gate oxide oxidation.

Further, the thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is less than or equal to 850°C, and the main process time is less than or equal to 30 minutes.

Further, in step 3), a polycrystalline film layer and an edge protection film layer on the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor are also deposited.

Further, the polycrystalline film layer and edge protection film layer on the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor adopt the same structure as the gate polycrystalline side protection structure of the MOS transistor in the normal analog CMOS integrated circuit process.

A low-voltage coefficient polycrystalline capacitor fabricated by using the multi-layer gate analog CMOS process edge stress optimization integration method includes a P-type substrate or a P-type epitaxial layer, and an N-type well, a self-aligned P-type well, a field oxide layer, Sacrificial oxide layer, gate oxide layer, polycrystalline film layer, silicon dioxide dielectric layer, capacitor dielectric layer, low dielectric constant filling film layer, metal interconnection film layer, protective dielectric passivation layer outside the top metal bonding area;

the P-type substrate or the P-type epitaxial layer is located at the bottom;

The well region is located on the surface of the P-type substrate or the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

The field oxide layer, the sacrificial oxide layer and the gate oxide layer cover different regions of the well respectively;

The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

the low-k filling film layer fills the region between the metal interconnect film layers;

The metal interconnection film layer includes a silicon-metal interconnection film layer, a polysilicon-metal interconnection film layer, a field oxygen-metal interconnection film layer, and a multi-layer metal interconnection region;

The outer protective dielectric passivation layer in the top metal bonding region covers the top metal layer region in the multi-layer metal interconnection region.

Further, it also includes a silicon oxynitride dielectric layer;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

The technical effect of the present invention is unquestionable. The present invention significantly improves the dual polycrystalline capacitors through a modular and precise matching low voltage coefficient polycrystalline capacitor edge effect and high stress optimized manufacturing method integrated with the multi-layer gate high and low voltage compatible analog CMOS process. The edge effect reduces the mechanical stress of the integrated dual polycrystalline capacitors, eases the electric field concentration in the edge region of the dual polycrystalline capacitors, and improves the high and low voltage compatible analog CMOS integrated circuits. The electrical performance of the voltage modulation of the dual polycrystalline capacitors is stable. performance and process consistency.

The invention adopts a modular and precise matching low-voltage coefficient polycrystalline capacitor edge effect and high stress optimized manufacturing method integrated with a multi-layer gate high and low voltage compatible analog CMOS process, and improves the regrowth of crystal grains in the polycrystalline thin layer and the regrowth of impurities in the crystal grains. The uniformity of distribution effectively improves the low-voltage coefficient integrated double polycrystalline capacitors in the high and low voltage compatible analog CMOS integrated circuits for complex and high-precision detection of weather forecasting, ocean exploration, polar scientific research and other working environments.

The invention adopts a modularized and precise matching low-voltage coefficient polycrystalline capacitor edge effect and high stress optimized manufacturing method integrated with a multi-layer gate high and low voltage compatible analog CMOS process, which improves the polycrystalline capacitor plate polycrystalline thin layer under the action of electrical stress. Grain depletion and grain boundary size and shape effectively improve the long-term reliability of low-voltage coefficient integrated dual polycrystalline capacitor products in analog integrated circuits.

Through the optimized manufacturing method of the invention and the multi-layer gate high and low voltage compatible analog CMOS process, the edge effect and high stress of the low-voltage coefficient polycrystalline capacitor are precisely matched, and the mismatch degree of the integrated double polycrystalline capacitor can be reduced from ±0.1% It can be applied to high-precision A/D and D/A converters with a resolution of more than 14 bits, improving process compatibility and device integration density, and enhancing product market competitiveness.

Description of drawings

Figure 1 is a cross-sectional view of the growth shielding oxide layer after the completion of epitaxial growth, well implantation, annealing, field oxidation and other conventional analog CMOS integrated circuit processes;

2 is a cross-sectional view of the polycrystalline film layer of the lower plate of the double polycrystalline capacitor after deposition and doping;

3 is a cross-sectional view of the edge protection film layer of the polycrystalline film layer of the lower electrode plate of the polycrystalline capacitor after the thick and thin double gate oxide oxidation process is completed;

4 is a sectional view of the structure of the polycrystalline capacitor capacitor dielectric layer deposition and exposure etching structure completed;

Fig. 5 is a partial enlarged cross-sectional view and SEM analysis diagram of the structure after the subsequent wet etching and oxidation processes are completed without using the edge optimization technical solution;

FIG. 6 is an enlarged cross-sectional view and a SEM analysis diagram of the structure after the subsequent wet etching and oxidation processes are completed by using the edge optimization technical solution;

7 is a schematic diagram of the 3D structure after the polycrystalline film layer deposition and doping on the upper plate of the polycrystalline capacitor is completed, and after exposure and etching;

FIG. 8 is a schematic structural diagram of a low voltage coefficient double polycrystalline capacitor after completing the two-layer metal interconnection process;

9 is a schematic structural diagram of a low-voltage coefficient integrated dual polycrystalline capacitor in the high-low-voltage compatible analog CMOS integrated circuit process of Embodiment 1;

In the figure: LOCOS field oxide layer region 11, P-type MOS lightly doped source-drain implantation region 12, N-type well implantation region 13, low-voltage MOS thin gate oxide layer region 14, gate polycrystalline layer region 15, sidewall protection area 16. P-type MOS source and drain implantation region 17, polycrystalline layer I18, oxygen-nitrogen dielectric layer 19, self-aligned P-type well region 20, N-type MOS source and drain implantation region 21, high-voltage MOS thick gate oxide layer region 22, gate Polycrystalline top layer nitroxide dielectric protection layer region 23, 100 crystal orientation P-type substrate/epitaxial layer 24, silicon/polysilicon-metal 1 interlayer contact hole tungsten plug structure region 101, silicon/polysilicon/field oxygen-metal 1 interlayer ILD dielectric planarization layer 102 , multi-layer inter-metal IMD dielectric planarization layer 103 , first-layer metal film region 104 , multi-layer inter-metal via hole tungsten plug structure region 105 , and top metal layer region 106 .

Detailed ways

The present invention will be further described below in conjunction with the examples, but it should not be understood that the scope of the above-mentioned subject matter of the present invention is limited to the following examples. Without departing from the above-mentioned technical idea of the present invention, various substitutions and changes can be made according to common technical knowledge and conventional means in the field, which shall be included in the protection scope of the present invention.

Example 1:

Referring to FIG. 1 to FIG. 9 , the integrated method for optimizing the edge stress of a multi-layer gate analog CMOS process includes the following steps:

1) Form an N-type well in the P-type substrate or P-type epitaxial layer with a low voltage coefficient integrated double polycrystalline capacitor region, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) Deposit a P1 angstrom-thick lower electrode polycrystalline film of the low-voltage coefficient integrated double-polysilicon capacitor on the field oxide layer above the N-type well in the low-voltage coefficient integrated double-polysilicon capacitor region, and complete the N-type lithography Injecting doping; wherein, the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor is used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) depositing the first layer of dielectric of the double polycrystalline capacitor with a thickness of d1 angstrom, and using the exposure etching process to realize the production of the edge protection layer of the lower electrode of the double polycrystalline capacitor;

6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and using an exposure etching process to complete the fabrication of the capacitor dielectric layer structure;

7) Complete the conventional process before simulating CMOS integrated circuit gate polycrystalline deposition;

8) depositing a P2 angstrom-thick MOS transistor gate polycrystalline film layer, and completing the MOS transistor gate polycrystalline doping;

9) The subsequent conventional process of the normal analog CMOS integrated circuit is completed.

The method for depositing the P1 angstrom polycrystalline film layer, the first dielectric layer of the double polycrystalline capacitor, and the gate polycrystalline film layer of the MOS transistor includes a low pressure chemical vapor deposition method.

The dielectric constant of the first layer of the double polycrystalline capacitor is denoted as ε1, and the dielectric coefficient of the capacitor dielectric layer is denoted as ε2.

ε1 and ε2 are constants.

The subsequent conventional processes of a normal analog CMOS integrated circuit include source-drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, and metal interconnection.

Conventional processes prior to gate polysilicon deposition in analog CMOS integrated circuits include sacrificial oxidation, channel implantation, exposure and etching, and gate oxide oxidation.

The thermal oxidation process conditions include: the main process temperature of the thermal oxidation process is less than or equal to 850°C, and the main process time is less than or equal to 30min.

In step 3), a polycrystalline film layer and an edge protection film layer on the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor are also deposited.

The polycrystalline film layer and edge protection film layer on the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor adopt the same structure as the gate polycrystalline side protection structure of the MOS transistor in the normal analog CMOS integrated circuit process.

The low-voltage coefficient polycrystalline capacitor fabricated by using the multi-layer gate simulation CMOS process edge stress optimization integration method includes a P-type substrate or a P-type epitaxial layer, as well as an N-type well 13, a self-aligned P-type well 20, a field oxide Layer 11, Sacrificial Oxide Layer, Gate Oxide Layer 14, Polycrystalline Film Layer 15, Silicon Dielectric Layer, Capacitor Dielectric Layer, Low-K Filling Film Layer, Metal Interconnect Film Layer, Top Metal Bonding Area External Protection Dielectric Passivation layer, silicon oxynitride dielectric layer 19;

the P-type substrate or the P-type epitaxial layer is located at the bottom;

The well region is located on the surface of the P-type substrate or the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

The field oxide layer, the sacrificial oxide layer and the gate oxide layer cover different regions of the well respectively;

The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

the low-k filling film layer fills the region between the metal interconnect film layers;

The metal interconnection film layer includes a silicon-metal interconnection film layer, a polysilicon-metal interconnection film layer, a field oxygen-metal interconnection film layer, and a multi-layer metal interconnection region;

The outer protective dielectric passivation layer in the top metal bonding region covers the top metal layer region in the multi-layer metal interconnection region.

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

Example 2:

An integrated method for optimizing the edge stress of a multi-layer gate analog CMOS process, including the following steps:

1) Form an N-type well of the low-voltage coefficient integrated double polycrystalline capacitor region on the P-type substrate, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) Deposit a P1 angstrom-thick lower electrode polycrystalline film of the low-voltage coefficient integrated double-polysilicon capacitor on the field oxide layer above the N-type well in the low-voltage coefficient integrated double-polysilicon capacitor region, and complete the N-type lithography Injecting doping; wherein, the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor is used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) depositing the first layer of dielectric of the double polycrystalline capacitor with a thickness of d1 angstrom, and using the exposure etching process to realize the production of the edge protection layer of the lower electrode of the double polycrystalline capacitor;

6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and using an exposure etching process to complete the fabrication of the capacitor dielectric layer structure;

7) Complete the conventional process before simulating CMOS integrated circuit gate polycrystalline deposition;

8) depositing a P2 angstrom-thick MOS transistor gate polycrystalline film layer, and completing the MOS transistor gate polycrystalline doping;

9) The subsequent conventional process of the normal analog CMOS integrated circuit is completed.

Example 3:

An integrated method for optimizing the edge stress of a multi-layer gate analog CMOS process, including the following steps:

1) Form an N-type well in the P-type epitaxial layer with a low voltage coefficient integrated double polycrystalline capacitor region, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) Deposit a P1 angstrom-thick lower electrode polycrystalline film of the low-voltage coefficient integrated double-polysilicon capacitor on the field oxide layer above the N-type well in the low-voltage coefficient integrated double-polysilicon capacitor region, and complete the N-type lithography Injecting doping; wherein, the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor is used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) depositing the first layer of dielectric of the double polycrystalline capacitor with a thickness of d1 angstrom, and using the exposure etching process to realize the production of the edge protection layer of the lower electrode of the double polycrystalline capacitor;

6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and using an exposure etching process to complete the fabrication of the capacitor dielectric layer structure;

7) Complete the conventional process before simulating CMOS integrated circuit gate polycrystalline deposition;

8) depositing a P2 angstrom-thick MOS transistor gate polycrystalline film layer, and completing the MOS transistor gate polycrystalline doping;

9) The subsequent conventional process of the normal analog CMOS integrated circuit is completed.

Example 4:

An integrated method for optimizing the edge stress of a multi-layer gate analog CMOS process, including the following steps:

1) Form an N-type well in the P-type substrate or P-type epitaxial layer with a low voltage coefficient integrated double polycrystalline capacitor region, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) Deposit a P1 angstrom-thick lower electrode polycrystalline film of the low-voltage coefficient integrated double-polysilicon capacitor on the field oxide layer above the N-type well in the low-voltage coefficient integrated double-polysilicon capacitor region, and complete the N-type lithography Injecting doping; wherein, the polycrystalline film layer of the lower electrode of the low voltage coefficient integrated double polycrystalline capacitor is used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) depositing the first layer of dielectric of the double polycrystalline capacitor with a thickness of d1 angstrom, and using the exposure etching process to realize the production of the edge protection layer of the lower electrode of the double polycrystalline capacitor;

6) depositing a capacitor dielectric layer with a thickness of d2 angstroms, and using an exposure etching process to complete the fabrication of the capacitor dielectric layer structure;

7) Complete the conventional process before simulating CMOS integrated circuit gate polycrystalline deposition;

8) depositing a P2 angstrom-thick MOS transistor gate polycrystalline film layer, and completing the MOS transistor gate polycrystalline doping;

9) The subsequent conventional process of the normal analog CMOS integrated circuit is completed.

Example 5:

A method for optimizing and integrating edge stress in a multi-layer gate simulating CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein, a P1 angstrom polycrystalline film layer, a first dielectric layer of a double polycrystalline capacitor, and a MOS transistor gate polycrystalline film are deposited. The method of layering includes low pressure chemical vapor deposition.

Example 6:

The method for optimizing the integration of edge stress in a multi-layer gate analog CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein the dielectric coefficient of the first layer of the dual polycrystalline capacitor is recorded as ε1, and the dielectric coefficient of the capacitor dielectric layer is recorded as ε2.

Example 7:

A method for optimizing and integrating edge stress in a multi-layer gate analog CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein the subsequent conventional processes of a normal analog CMOS integrated circuit include source-drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization , contact hole etching, metal interconnection.

Example 8:

A method for optimizing and integrating edge stress in a multi-layer gate analog CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein, the conventional process before the polycrystalline deposition of the analog CMOS integrated circuit gate includes sacrificial oxidation, channel adjustment implantation, exposure and etching, gate oxide oxidation.

Example 9:

A method for optimizing and integrating edge stress in a multi-layer gate analog CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein the thermal oxygen process conditions include: the main process temperature of the thermal oxidation process is ≤ 850°C, and the main process time is ≤ 30min.

Example 10:

A method for optimizing and integrating edge stress in a multi-layer gate analog CMOS process, the main content is shown in Embodiment 2, 3 or 4, wherein, in step 3, the polycrystalline film layer and the edge of the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor are also deposited. protective film layer.

Example 11:

A method for optimizing and integrating edge stress in a multi-layer gate analog CMOS process, see Embodiment 2, 3 or 4 for the main content. In the integrated circuit process, the gate polycrystalline side protection structure of the MOS type transistor is provided.

Example 12:

A low-voltage coefficient polycrystalline capacitor fabricated by using the edge stress-optimized integration method of the multilayer gate analog CMOS process described in Embodiments 1-11, including a P-type substrate, an N-type well 13, a self-aligned P-type well 20, and a field oxide layer 11. Sacrificial oxide layer, gate oxide layer 14, polycrystalline film layer 15, silicon dioxide dielectric layer, capacitor dielectric layer, low dielectric constant filling film layer, metal interconnect film layer, top metal bonding area outer protective dielectric passivation chemical layer;

the P-type substrate is located at the bottom;

The well region is located on the surface of the P-type substrate; the well region includes an N-type well and a self-aligned P-type well;

The field oxide layer, the sacrificial oxide layer and the gate oxide layer cover different regions of the well respectively;

The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

the low-k filling film layer fills the region between the metal interconnect film layers;

The metal interconnection film layer includes a silicon-metal interconnection film layer, a polysilicon-metal interconnection film layer, a field oxygen-metal interconnection film layer, and a multi-layer metal interconnection region;

The outer protective dielectric passivation layer in the top metal bonding region covers the top metal layer region in the multi-layer metal interconnection region.

Example 13:

A low voltage coefficient polycrystalline capacitor fabricated by using the edge stress optimization integration method of the multi-layer gate analog CMOS process described in Embodiments 1-11, including a P-type epitaxial layer, an N-type well 13, a self-aligned P-type well 20, and a field oxide layer 11. Sacrificial oxide layer, gate oxide layer 14, polycrystalline film layer 15, silicon dioxide dielectric layer, capacitor dielectric layer, low dielectric constant filling film layer, metal interconnect film layer, top metal bonding area outer protective dielectric passivation chemical layer;

the P-type epitaxial layer is located at the bottom;

The well region is located on the surface of the P-type epitaxial layer; the well region includes an N-type well and a self-aligned P-type well;

The field oxide layer, the sacrificial oxide layer and the gate oxide layer cover different regions of the well respectively;

The polycrystalline film layer of the low voltage coefficient polycrystalline capacitor is located on the upper surface of the field oxide layer above the N-type well;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and capacitor dielectric layers.

the low-k filling film layer fills the region between the metal interconnect film layers;

The metal interconnection film layer includes a silicon-metal interconnection film layer, a polysilicon-metal interconnection film layer, a field oxygen-metal interconnection film layer, and a multi-layer metal interconnection region;

The outer protective dielectric passivation layer in the top metal bonding region covers the top metal layer region in the multi-layer metal interconnection region.

Example 14:

A low-voltage coefficient polycrystalline capacitor fabricated by using the multi-layer gate simulation CMOS process edge stress optimization integration method, the main content is shown in Embodiment 12 or 13, wherein the capacitor further includes a silicon oxynitride dielectric layer 19;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers, and capacitor dielectric layers.

Example 15:

An optimized manufacturing method for edge effect and high stress of a precisely matched low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process, which mainly includes the following steps:

1) An N-type well is formed on the substrate, and a self-aligned P-type well is formed outside the N-type well;

For the high-performance high-precision analog CMOS process, a layer of P-type epitaxy is grown on the P-type substrate according to the circuit performance requirements. An N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed outside the N-type well.

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) A low-pressure chemical vapor deposition method is used to deposit a P1 angstrom polycrystalline film layer on the top of the field oxide layer, and N-type lithography implantation and doping are completed according to the performance of the capacitor. The polycrystalline film layer can be used as the lower plate of the low voltage coefficient integrated double polycrystalline capacitor;

The polycrystalline film layer of the lower plate of the double polycrystalline capacitor is deposited on the field oxide layer above the N-type well, and the effect of doping oxidation enhancement can be used to reduce the influence of parasitic capacitance and substrate noise, and improve the performance of the polycrystalline capacitor device.

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

The main process temperature of thermal oxygen is ≤850℃, and the main process time is ≤30min, which is conducive to process compatibility and reduces the impact on the main process devices of analog CMOS integrated circuits.

The chlorine-containing oxidizing atmosphere is used in the thermal oxygen oxidation process to improve the quality of the oxide layer and reduce the interface defects and interface state traps.

5) The first layer of dielectric (dielectric coefficient is ε1) of d1 angstrom double polycrystalline capacitor is deposited by low pressure chemical vapor deposition method, and the exposure and etching process is used to realize the fabrication of the lower electrode edge protection structure of the double polycrystalline capacitor.

6) According to the parameter performance of the low voltage coefficient integrated dual polycrystalline capacitor, the capacitor dielectric layer is required for deposition, the dielectric coefficient is ε2, and the film thickness is d2 angstroms. And use the exposure and etching process to complete the structure of the capacitor dielectric layer;

The capacitor dielectric layer can choose a high dielectric constant film layer to improve the unit capacitance of the double polycrystalline capacitor.

On the premise of ensuring the performance requirements of the polycrystalline capacitor, the capacitor dielectric film layer can be the same film layer as the dielectric film layer of the edge protection structure of the polycrystalline capacitor in 5), so as to simplify the process steps.

7) An m1 angstrom thick gate oxide layer is formed on the area of the well surface not covered by the field oxide layer; the m1 angstrom thick gate oxide layer is removed in the active region of the low-voltage device, and an m2 angstrom thin gate oxide layer is formed after cleaning is completed ;

After the thick gate oxide layer is formed, processes such as threshold adjustment and implantation of the CMOS device are completed as required. Then, the thick gate oxide layer is removed in the active region of the low-voltage device, and the required thin gate oxide layer is generated after cleaning, which is beneficial to improve the integrity of the gate oxide layer.

Especially for the circuit layout of the integrated dual polycrystalline capacitor array, the polycrystalline film layer of the lower electrode of the polycrystalline capacitor with the edge protection structure significantly improves the stress mismatch and warpage of the polycrystalline film layer shown in Figure 5, and improves the integrated dual polycrystalline film. The matching degree and integration density of polycrystalline capacitors, and the optimized structure are shown in Figure 6.

8) Using low pressure chemical vapor deposition method to deposit P2 Angstrom MOS transistor gate polycrystalline film layer, and complete the MOS transistor gate polycrystalline doping according to the performance requirements of MOS devices;

9) Next, complete the normal simulation CMOS integrated circuit source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, metal interconnection and other processes; Embodiment 16:

An optimized manufacturing method for edge effect and high stress of a precisely matched low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process, the main content is shown in Example 13. , P-well injection push junction, field oxide layer growth and other processes to carry out low-voltage coefficient integrated dual polycrystalline capacitors high-stress edge effect optimization of integrated fabrication, the steps include:

1) The gate polycrystalline film layer of the MOS transistor is used as the polycrystalline film layer of the lower electrode plate of the polycrystalline capacitor, and the edge optimization technical scheme of the polycrystalline electrode plate described in Embodiment 1 is adopted.

If the analog CMOS integrated circuit process adopts the gate polycrystalline sidewall structure, the gate polycrystalline sidewall structure can be optimized for protecting the edge region of the polycrystalline film layer of the lower plate of the polycrystalline capacitor.

2) depositing a polycrystalline film layer on the upper plate of the double polycrystalline capacitor, and completing doping, exposure and etching to form the upper plate structure of the polycrystalline capacitor.

The subsequent steps use the normal analog CMOS integrated circuit process scheme:

Example 17:

An optimized manufacturing method for edge effect and high stress of an accurate matching low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process, the main content is shown in Embodiment 13, wherein, for a high performance and high precision analog CMOS process, according to circuit performance It is required to grow a layer of P-type epitaxy on the P-type substrate. An N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed outside the N-type well. :

The subsequent steps use the normal analog CMOS integrated circuit process scheme:

Example 18:

An optimized manufacturing method for edge effect and high stress of an accurate matching low voltage coefficient dual polycrystalline capacitor integrated with a multi-layer gate high and low voltage compatible analog CMOS process, the main content is shown in Embodiment 13, wherein the silicided source/drain regions and the silicided gate polycrystalline process are used , can obtain lower contact resistance and reduce gate poly depletion effect, and silicide is widely used in the process. Based on the completion of epitaxial growth, N-well injection and push junction, P-well injection and push junction, field oxide layer growth and other processes, the integrated fabrication of low voltage coefficient integrated double polycrystalline capacitors with high stress edge effect optimization is carried out.

The previous process steps are the same as in implementation 1. After the gate poly sidewall structure etchback and source/drain implantation annealing are completed,

1) Ti/TiN sputtering is carried out by metal sputtering process, and then source/drain regions and polysilicon metallization are completed by annealing process.

Sputtering suitable metal thin layers can not only achieve silicidation, but also integrate Schottky diodes in the process;

Using a suitable silicide blocking mask can reduce the voltage modulation effect of polycrystalline capacitors to obtain polycrystalline capacitors with lower voltage coefficients.

2) Remove the sputtered metal thin layer outside the clean silicide area. Then, the metal interconnection is realized by dielectric layer deposition, contact hole exposure etching and metal sputtering.

The subsequent steps use the normal analog CMOS integrated circuit process scheme:

Example 19:

An integrated method for optimizing the edge stress of a multi-layer gate analog CMOS process, including the following steps:

1) Form an N-type well on the P-type substrate, and form a self-aligned P-type well in the area outside the N-type well;

2) A field oxide layer of m angstrom is formed on the surface of the N well and the self-aligned P well;

3) A low-voltage chemical vapor deposition method is used to deposit a P1 angstrom polycrystalline film on the field oxide layer above the N-type well in the low-voltage coefficient integrated double polycrystalline capacitor region, and N-type lithography implantation is completed according to the performance of the capacitor. miscellaneous. The polycrystalline film layer can be used as a lower plate of a low voltage coefficient integrated double polycrystalline capacitor;

4) using thermal oxygen process conditions to grow n angstrom thermal oxide layer;

5) The first layer of dielectric (dielectric coefficient is ε1) of d1 angstrom double polycrystalline capacitor is deposited by low pressure chemical vapor deposition method, and the exposure and etching process is used to realize the fabrication of the lower electrode edge protection structure of the double polycrystalline capacitor.

6) According to the performance of the low voltage coefficient integrated double polycrystalline capacitor, the capacitor dielectric layer is required for deposition, the dielectric coefficient is ε2, and the film thickness is d2 angstroms. And use the exposure and etching process to complete the structure of the capacitor dielectric layer;

7) Complete the normal process steps such as sacrificial oxidation before the gate polycrystalline deposition of the simulated CMOS integrated circuit, channel adjustment implantation, exposure etching, gate oxide oxidation, etc.;

8) Using low pressure chemical vapor deposition method to deposit P2 Angstrom MOS transistor gate polycrystalline film layer, and complete the MOS transistor gate polycrystalline doping according to the performance requirements of MOS devices;

9) Next, complete the normal simulation CMOS integrated circuit source and drain implantation, annealing activation, dielectric layer deposition, reflow filling and planarization, contact hole etching, metal interconnection and other processes;

For high-performance, high-precision analog CMOS processes, a layer of P-type epitaxy is grown on a P-type substrate. Then, an N-type well is formed on the P-type epitaxy, and a self-aligned P-type well is formed in the area outside the N-type well.

The low voltage coefficient integrated double polycrystalline capacitor lower electrode polycrystalline film oxide layer, edge protection layer, and the method of forming the capacitor dielectric layer are as follows:

1) In the thermal oxidation process of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, the main process temperature is less than or equal to 850℃, and the main process time is less than or equal to 30min;

2) In the edge protection layer of the polycrystalline film layer of the lower electrode of the double polycrystalline capacitor, a low-pressure chemical vapor deposition method is used to deposit a dielectric film with a thickness of d1 angstroms and a dielectric coefficient of ε1;

3) In the production of the dielectric layer of the low voltage coefficient double polycrystalline capacitor, according to the performance of the capacitor, a dielectric film with a thickness of d2 angstroms and a dielectric coefficient of ε2 is deposited;

The edge protection film of the polycrystalline film layer on the upper plate of the low-voltage coefficient integrated double polycrystalline capacitor adopts the same structure as the gate polycrystalline side protection structure of the MOS transistor in the normal analog CMOS integrated circuit process.

The low-voltage-coefficient polycrystalline capacitor based on the optimized manufacturing method for the edge effect of the low-voltage-coefficient dual polycrystalline capacitor in a high- and low-voltage compatible analog CMOS process mainly includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, field oxide layer, sacrificial oxide layer, gate oxide layer, polycrystalline thin film layer, silicon dioxide dielectric layer, silicon oxynitride dielectric layer and low-k filling layer, metal interconnect layer, passivation layer ;

the substrate is located at the bottom; the epitaxial layer is located above the substrate layer; the well region is located on the surface of the epitaxial layer;

The field oxide layer, the sacrificial oxide layer and the gate oxide layer cover different regions of the well respectively;

The polycrystalline film layer of the double polycrystalline capacitor is located above the field oxide layer above the N well;

The top surface and sidewalls of the polycrystalline film layer are covered with different silicon dioxide and silicon nitride composite dielectric layers and high dielectric coefficient capacitor dielectric layers.

The low dielectric constant filling film layer fills the region between the silicon-metal 1, polysilicon-metal 1, field oxygen-metal 1 and the multi-layer metal.

Example 20:

Referring to FIG. 9 , the low-voltage-coefficient polycrystalline capacitor fabricated based on the optimized manufacturing method for the edge effect of the low-voltage-coefficient dual polycrystalline capacitor in the high-low voltage compatible analog CMOS process described in Embodiments 1-19 includes the LOCOS field oxide layer region 11 , the P-type MOS Lightly doped source and drain implantation region 12, N-type well implantation region 13, low-voltage MOS thin gate oxide layer region 14, gate polycrystalline layer region 15, sidewall protection area 16, P-type MOS source-drain implantation region 17, polycrystalline Layer I18, oxygen-nitrogen dielectric layer 19, self-aligned P-type well region 20, N-type MOS source-drain implantation region 21, high-voltage MOS thick gate oxide layer region 22, gate polysilicon top nitrogen-oxygen dielectric protection layer region 23, 100 crystal To P-type substrate/epitaxial layer 24, silicon/polysilicon-metal 1 interlayer contact hole tungsten plug structure region 101, silicon/polysilicon/field oxygen-metal 1 interlayer ILD dielectric planarization layer 102, multi-layer inter-metal IMD The dielectric planarization layer 103 , the first metal film layer region 104 , the multi-layer metal interlayer via hole tungsten plug structure region 105 , and the top metal layer region 106 .

Claims (10)

1. The method for optimizing and integrating the edge stress of the multi-layer gate simulation CMOS process is characterized by comprising the following steps of:

1) An N-type well of a low voltage coefficient integrated double polycrystalline capacitor region is formed on a P-type substrate, and a self-aligned P-type well is formed in a region other than the N-type well.

2) Forming m-angstrom field oxide layers on the surfaces of the N well and the self-aligned P well;

3) Depositing a polycrystalline film layer of a lower electrode of the integrated double-polycrystalline capacitor with a low voltage coefficient and with a thickness of P1 angstrom on a field oxide layer above an N-type well in the region of the integrated double-polycrystalline capacitor with a low voltage coefficient, and completing N-type photoetching injection doping; the polycrystalline film layer of the lower electrode of the low-voltage coefficient integrated double polycrystalline capacitor is used as the lower polar plate of the low-voltage coefficient integrated double polycrystalline capacitor;

4) Growing an n-angstrom thermal oxidation layer under the thermal oxidation process condition;

5) Depositing a first layer of medium of the double-polycrystal capacitor with the thickness of d1 angstrom, and realizing the manufacture of a lower electrode edge protective layer of the double-polycrystal capacitor by adopting an exposure etching process; the dielectric coefficient of the first layer of medium of the double polycrystalline capacitor is marked as epsilon 1;

6) Depositing a capacitor dielectric layer with the thickness of d2 angstrom meters, and completing the manufacture of a capacitor dielectric layer structure by adopting an exposure etching process; the dielectric coefficient of the capacitor dielectric layer is marked as epsilon 2;

7) Completing the conventional process before the deposition of the gate polycrystal of the analog CMOS integrated circuit;

8) Depositing a P2 angstrom thick MOS transistor gate polycrystalline film layer and completing the polycrystalline doping of the MOS transistor gate;

9) And finishing the subsequent conventional process of the normal analog CMOS integrated circuit.

2. The method of claim 1, wherein the depositing the P1 angstrom polycrystalline film, the first dielectric layer of the double poly capacitor, and the polycrystalline film of the MOS transistor gate comprises low pressure chemical vapor deposition.

3. The method of claim 1, wherein in step 1), before forming the N-well, a P-type epitaxy is grown on the P-type substrate, then the N-well is formed on the P-type epitaxy, and a self-aligned P-well is formed in a region outside the N-well.

4. The method of claim 1, wherein the normal analog CMOS integrated circuit comprises source-drain implantation, annealing activation, dielectric layer deposition, reflow filling planarization, contact hole etching, and metal interconnection.

5. The method of claim 1, wherein conventional processes prior to gate poly deposition of the analog CMOS integrated circuit include sacrificial oxidation, trench implantation, exposure etching, and gate oxide oxidation.

6. The method of claim 1, wherein the thermal oxidation process conditions comprise: the main process temperature of the thermal oxidation process is less than or equal to 850 ℃, and the main process time is less than or equal to 30min.

7. The method as claimed in claim 1, wherein in step 3), a low voltage coefficient integrated double poly capacitor upper plate poly film layer and an edge protection film layer are deposited.

8. The method of claim 1, wherein the poly-crystalline film layer of the upper plate and the edge protection film layer of the integrated double poly-capacitor with low voltage coefficient are formed by a gate poly-crystalline side protection structure of a MOS transistor in a normal analog CMOS integrated circuit process.

9. The low-voltage coefficient polycrystalline capacitor manufactured by the multilayer gate simulation CMOS process edge stress optimization integration method according to any one of claims 1 to 8, wherein: the field oxide layer, the sacrificial oxide layer, the gate oxide layer, the polycrystalline film layer, the silicon dioxide dielectric layer, the capacitor dielectric layer, the low dielectric coefficient filling film layer, the metal interconnection film layer and the top metal bonding region outer protective dielectric passivation layer;

the P-type substrate or the P-type epitaxial layer is positioned at the bottom;

the well region is positioned on the surface of the P-type substrate or the P-type epitaxial layer; the well region comprises an N-type well and a self-aligned P-type well;

the field oxide layer, the sacrificial oxide layer and the gate oxide layer respectively cover different regions of the well;

the polycrystalline film layer of the low-voltage coefficient polycrystalline capacitor is positioned on the upper surface of the field oxide layer above the N-type well;

the top surface and the side wall of the polycrystalline film layer are covered with different silicon dioxide dielectric layers and different capacitor dielectric layers.

The low dielectric coefficient filling film layer is filled in the region between the metal interconnection film layers;

the metal interconnection film layer comprises a silicon-metal interconnection film layer, a polycrystalline silicon-metal interconnection film layer, a field oxide-metal interconnection film layer and a multilayer metal interconnection area;

and the protective dielectric passivation layer outside the top metal bonding region covers the top metal layer region in the multilayer metal interconnection region.

10. The low voltage coefficient polycrystalline capacitor of claim 9, wherein: the silicon oxynitride dielectric layer is also included;

the top surface and the side wall of the polycrystalline film layer are covered with different silicon dioxide dielectric layers, silicon oxynitride dielectric layers and capacitor dielectric layers.

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