CN115237026A - A kind of DC pulse signal acquisition circuit - Google Patents

Abstract

The application discloses direct current pulse signal acquisition circuit. The device comprises a conversion module, a voltage following module, a comparison module and an FPGA module, wherein the conversion module is provided with a first input end which is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal; the voltage following module is configured to realize impedance matching of the second single-ended signal and a signal at the input end of the comparison module to obtain a third single-ended signal; the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal; the FPGA module is provided with a fifth input end and a sixth input end, the fifth input end and the sixth input end are both configured to receive a fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

Description

A DC pulse signal acquisition circuit

technical field

The present disclosure relates to the field of electrical technology, in particular to a DC pulse signal acquisition circuit.

Background technique

In the field of control, counting sensors are often required to count the effective actions of the actuators. Currently, sensors of the type such as encoders and displacement sensors are generally used for counting sensors, and their output signals are pulse signals. The output pulse signal is collected and processed.

In the past, counting acquisition was usually performed by means of a combination of optocouplers and triggers, high-speed AD conversion circuits, etc. Among them, the combination of optocouplers and triggers achieved isolated acquisition, but for pulse signals with spikes or jitters, there would be photocoupling. The high-speed AD conversion circuit has high-speed AD conversion capability, which can complete the real-time acquisition of the voltage value of the pulse signal, and count after being judged by the logic circuit, but this method takes up a lot of hardware and software processing resources, and the isolation Collection is difficult to achieve. Therefore, in order to meet the needs of a certain type of airborne equipment, complete the effective action of the actuator to count, and comprehensively consider the influence of the external electromagnetic environment, we propose a DC pulse signal acquisition circuit to solve the above problems.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a DC pulse signal acquisition circuit with a simple circuit that can count the effective actions of the actuator.

In a first aspect, the present application provides a DC pulse signal acquisition circuit, including:

a conversion module, the conversion module has a first input terminal, the first input terminal is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second differential pulse signal single-ended signal;

a voltage follower module, the voltage follower module has a second input terminal, the second input terminal is configured to receive the second single-ended signal, and the voltage follower module is configured to implement the second single-ended signal and a comparison module The impedance of the input signal is matched to obtain the third single-ended signal;

a comparison module, the comparison module has a third input terminal and a fourth input terminal, the third input terminal is configured to receive a fourth reference signal, and the fourth input terminal is configured to receive the third single-ended signal , the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal;

FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, both the fifth input terminal and the sixth input terminal are configured to receive the fifth level signal, and the FPGA module is configured with for calculating the number of rising edges and falling edges of the fifth level signal.

According to the technical solutions provided by the embodiments of the present application, the conversion module includes a voltage dividing unit, a first current limiting unit and a differential amplifying unit;

The voltage dividing unit has an input terminal, and the input terminal of the voltage dividing unit is the same as the first input terminal, and is configured to receive a first differential pulse signal; the voltage dividing unit is configured to convert the first differential pulse signal. The pulse signal is subjected to voltage division processing to obtain a first pulse voltage division signal;

The first current limiting unit has an input end, and the input end of the first current limiting unit is configured to receive the first pulse voltage division signal; the first current limiting unit is configured to convert the first pulse The voltage division signal is current-limited, and the first pulse voltage-divided signal after current-limiting is obtained;

The differential amplifying unit has an input end, and the input end of the differential amplifying unit is configured to receive the current-limited first pulse voltage-divided signal; the differential amplifying unit is configured to convert the current-limited first pulse signal. A pulse voltage-divided signal is converted to obtain a second single-ended signal.

According to the technical solutions provided by the embodiments of the present application, the voltage follower module includes a second current limiting unit and a voltage follower unit;

The second current limiting unit has an input end, and the input end of the second current limiting unit is the same as the second input end, and is configured to receive the second single-ended signal; the second current limiting unit is configured used to limit the second single-ended signal to obtain a current-limited second single-ended signal;

The voltage follower unit has an input terminal, and the input terminal of the voltage follower unit is configured to receive the second single-ended signal after the current limit; the voltage follower unit is configured to realize the second current limit signal. The impedance of the single-ended signal and the signal at the input end of the comparison module is matched to obtain a third single-ended signal.

According to the technical solutions provided by the embodiments of the present application, the comparison module includes a third current limiting unit and a comparison unit;

The third current limiting unit has two input ends, which are the third input end and the fourth input end, the third input end is configured to receive a fourth reference signal, and the fourth input end is configured for receiving the third single-ended signal; the third current limiting unit is configured to perform current limiting processing on the third single-ended signal and the fourth reference signal to obtain a third single-ended current-limited signal and the current-limited fourth reference signal;

The comparison unit has two input terminals, and the input terminals of the two comparison units are respectively configured to receive the third single-ended signal and the current-limited fourth reference signal; the comparison unit is configured to Comparing the current-limited fourth reference signal with the current-limited third single-ended signal to obtain a fifth level signal.

According to the technical solutions provided by the embodiments of the present application, the isolation unit further includes: an isolation unit configured to isolate the pulse signal ground GND of the voltage dividing unit from the analog ground AGND of the isolation unit;

a filtering unit, which is configured to filter out the common mode interference of the output signal;

a decoupling unit configured to perform filtering of the connected power supply;

A voltage pull-up unit configured to raise the level and improve the noise tolerance of the signal, as well as enhance immunity to interference.

According to the technical solutions provided in the embodiments of the present application, the voltage dividing unit includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 has a first end and a second end, and the first resistor R1 The first end of the second resistor R2 is configured to receive the first differential pulse signal, the second resistor R2 has a first end and a second end, and the first end and the second end of the second resistor R2 are respectively connected to the first capacitor C1. The first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is configured to be connected to the pulse signal ground GND;

The first current limiting unit includes a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, each of which has a first end and a second end, the first end of the fifth resistor R5 and the second resistor The first end of R2 is connected, the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4 terminal is connected, and the first terminal of the fourth resistor R4 is connected to the second terminal of the second resistor R2;

The differential amplifying unit includes a precision instrumentation amplifier N1, and the precision instrumentation amplifier N1 has 1 pin RG1, 2 pin IN-, 3 pin IN+, 4 pin VS-, 5 pin REF, 6 pin OUTPUT, 7 pin VS+ and 8 pin RG2; the 2-pin IN- is connected to the second end of the fourth capacitor C4, the 3-pin IN+ is connected to the first end of the fourth capacitor C4, the 1-pin RG1 and the 8-pin RG2 Floating setting.

According to the technical solutions provided in the embodiments of the present application, the second current limiting unit includes a sixth resistor R6, which has a first end and a second end, and the first end of the sixth resistor R6 is connected to the 6-pin OUTPUT ;

The voltage follower unit includes an operational amplifier N2A, which has pins 1, 2, 3, 4 and 8; the pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6.

According to the technical solutions provided by the embodiments of the present application, the third current limiting unit includes a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end, and the first end of the seventh resistor R7 is configured For receiving the fourth reference signal, the first end of the eighth resistor R8 is connected to the 1 pin of the operational amplifier N2A;

The comparison unit includes a comparator N3A, which has 2 pins, 3 pins, 4 pins, 5 pins and 12 pins; the 4 pins of the comparator N3A are connected to the second end of the eighth resistor R8, and the comparison Pin 5 of the comparator N3A is connected to the second end of the seventh resistor R7, and pin 2 of the comparator N3A is respectively connected to the fifth input end of the FPGA module.

According to the technical solutions provided by the embodiments of the present application, the isolation unit includes a third resistor R3 having a first end and a second end, the first end of the third resistor R3 and the second end of the second resistor R2 The second end of the third resistor R3 is configured to be connected to the analog ground AGND;

The filtering unit includes a first filtering unit, a second filtering unit and a third filtering unit; the first filtering unit includes a second capacitor C2, the second capacitor C2 has a first end and a second end, the The first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 is configured to be connected to the analog ground AGND; the second filter unit includes a third capacitor C3 , the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is configured Used to connect the analog ground AGND; the third filter unit includes a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 and the seventh resistor The second end of R7 is connected, the second end of the ninth capacitor C9 is connected to the 12 pin of the comparator N3A, and the second end of the ninth capacitor C9 is configured to be connected to the analog ground AGND;

The decoupling unit includes a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit, the first decoupling unit includes a sixth capacitor C6, which It has a first end and a second end, the first end of the sixth capacitor C6 is respectively connected to the 7-pin VS+ and the first external +15V power supply, and the second end of the sixth capacitor C6 is configured to connect the analog ground AGND; the second decoupling unit includes a fifth capacitor C5, which has a first end and a second end, the first end of the fifth capacitor C5 is connected to the 5-pin REF, and the fifth capacitor The first end of C5 is configured to be connected to the analog ground AGND, and the second end of the fifth capacitor C5 is connected to the 4-pin VS- and the first external -15V power supply respectively; the third decoupling unit includes a seventh A capacitor C7 has a first terminal and a second terminal, the first terminal of the seventh capacitor C7 is connected to the second terminal of the sixth resistor R6, and the second terminal of the seventh capacitor C7 is connected to the operation Pin 4 of the amplifier N2A is connected, and the second end of the seventh capacitor C7 is configured to be connected to the analog ground AGND; the fourth decoupling unit includes an eighth capacitor C8, which has a first end and a second end, so The first end of the eighth capacitor C8 is respectively connected to pin 8 of the operational amplifier N2A and the second external +15V power supply, and the second end of the eighth capacitor C8 is configured to be connected to the analog ground AGND; the fifth The decoupling unit includes a tenth capacitor C10, which has a first terminal and a second terminal. The first terminal of the tenth capacitor C10 is respectively connected to the 3-pin of the comparator N3A and the third external +15V power supply. The second end of the tenth capacitor C10 is configured to be connected to the analog ground AGND;

The voltage pulling unit includes a ninth resistor R9, the ninth resistor R9 has a first end and a second end, the first end of the ninth resistor R9 is connected to the 2 pin of the comparator N3A, the The second end of the ninth resistor R9 is connected to an external +3.3V power supply.

To sum up, this technical solution specifically discloses a DC pulse signal acquisition circuit. The present application is designed with a conversion module, the conversion module has a first input terminal, and the first input terminal is configured to receive the first differential pulse signal; conversion The module is configured to convert the first differential pulse signal to obtain a second single-ended signal; the voltage follower module has a second input terminal, and the second input terminal is configured to receive the second single-ended signal, and the voltage follower module It is configured to realize impedance matching between the second single-ended signal and the input terminal signal of the comparison module, and obtain a third single-ended signal; the comparison module, the comparison module has a third input terminal and a fourth input terminal, and the third input terminal is configured to receive the fourth reference signal, the fourth input terminal is configured to receive the third single-ended signal, and the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal; FPGA module, FPGA module It has a fifth input terminal and a sixth input terminal. Both the fifth input terminal and the sixth input terminal are configured to receive a fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

The circuit level of this scheme is simple, the circuit structure requires few components, the calculation of component parameters is simple, and there is no need for cumbersome circuits, which can effectively filter out the abnormal jitter and electromagnetic interference of the pulse signal, and realize the counting of the effective actions of the actuator, especially suitable for For occasions with compact structure space, isolation and anti-electromagnetic interference functions.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is an application schematic diagram of a DC pulse signal acquisition circuit.

FIG. 2 is a schematic diagram of a conversion module of a DC pulse signal acquisition circuit.

FIG. 3 is a schematic diagram of a voltage follower module of a DC pulse signal acquisition circuit.

FIG. 4 is a schematic diagram of a comparison module of a DC pulse signal acquisition circuit.

Detailed ways

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for the convenience of description, only the parts related to the invention are shown in the drawings.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

Example 1

Please refer to a DC pulse signal acquisition circuit provided by the present application shown in FIG. 1, including:

a conversion module, the conversion module has a first input terminal, and the first input terminal is configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal;

A voltage follower module, the voltage follower module has a second input terminal, the second input terminal is configured to receive a second single-ended signal, and the voltage follower module is configured to realize impedance matching between the second single-ended signal and the input terminal signal of the comparison module, and obtain the third single-ended signal;

A comparison module, the comparison module has a third input terminal and a fourth input terminal, the third input terminal is configured to receive a fourth reference signal, the fourth input terminal is configured to receive a third single-ended signal, and the comparison module is configured to The fourth reference signal is compared with the third single-ended signal to obtain the fifth level signal;

FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, the fifth input terminal and the sixth input terminal are both configured to receive the fifth level signal, and the FPGA module is configured to calculate the rising edge of the fifth level signal and the The number of falling edges.

In this embodiment, the conversion module has a first input terminal, the first input terminal is configured to receive the first differential pulse signal, and the first differential pulse signal is the pulse signal Pulse_IN; the conversion module is configured to convert the pulse signal Pulse_IN Perform conversion to obtain a second single-ended signal;

A voltage follower module, the voltage follower module has a second input terminal, the second input terminal is configured to receive a second single-ended signal, the second single-ended signal is a single-ended signal Vout1, and the voltage follower module is configured to realize the single-ended signal Vout1 and Compare the impedance matching of the signal at the input end of the module to obtain a third single-ended signal;

a comparison module, the comparison module has a third input terminal and a fourth input terminal, the third input terminal is configured to receive a fourth reference signal, the fourth reference signal is the reference signal Vref, and the fourth input terminal is configured to receive a third single-ended signal, the third single-ended signal is the single-ended signal Vout2, and the comparison module is configured to compare the reference signal Vref and the single-ended signal Vout2 to obtain a fifth level signal;

FPGA module, the FPGA module has a fifth input terminal and a sixth input terminal, the fifth input terminal and the sixth input terminal are respectively the IO port channels IO1 and IO2 of the FPGA module, and the IO port channels IO1 and IO2 are both configured to receive the fifth input terminal and the sixth input terminal. level signal, the fifth level signal is the TTL level signal IO_Timer, and the FPGA module is configured to calculate the number of rising edges and falling edges of the TTL level signal IO_Timer, thereby completing the DC pulse signal collection and counting functions.

As shown in Figure 2, the conversion module includes a voltage dividing unit, a first current limiting unit and a differential amplifying unit;

The voltage dividing unit has an input end, and the input end of the voltage dividing unit is the same as the first input end, and is configured to receive the pulse signal Pulse_IN; the voltage dividing unit is configured to perform voltage dividing processing on the pulse signal Pulse_IN to obtain the first pulse voltage dividing signal , the first pulse voltage division signal is the signal Vout_P;

The first current limiting unit has an input end, and the input end of the first current limiting unit is configured to receive the differential signal Vout_P; the first current limiting unit is configured to current limit the differential signal Vout_P to obtain a current-limited differential signal Vout_P;

The differential amplifying unit has an input end, and the input end of the differential amplifying unit is configured to receive the current-limited differential signal Vout_P; the differential amplifying unit is configured to convert the current-limited differential signal Vout_P to obtain the single-ended signal Vout1.

As shown in FIG. 3 , the voltage follower module includes a second current limiting unit and a voltage follower unit;

The second current limiting unit has an input end, and the input end of the second current limiting unit is the same as the second input end, and is configured to receive the single-ended signal Vout1; the second current limiting unit is configured to current-limit the single-ended signal Vout1, Obtain the current-limited single-ended signal Vout1;

The voltage follower unit has an input terminal, and the input terminal of the voltage follower unit is configured to receive the current-limited single-ended signal Vout1; the voltage follower unit is configured to realize impedance matching between the current-limited single-ended signal Vout1 and the input terminal signal of the comparison module , the single-ended signal Vout2 is obtained.

As shown in Figure 4, the comparison module includes a third current limiting unit and a comparison unit;

The third current limiting unit has two input terminals, which are a third input terminal and a fourth input terminal. The third input terminal is configured to receive the reference signal Vref, and the fourth input terminal is configured to receive the single-ended signal Vout2; The current unit is configured to perform current limiting processing on the single-ended signal Vout2 and the reference signal Vref to obtain the current-limited single-ended signal Vout2 and the current-limited reference signal Vref;

The comparison unit has two input terminals, and the input terminals of the two comparison units are respectively configured to receive the single-ended signal Vout2 and the current-limited reference signal Vref; the comparison unit is configured to combine the current-limited reference signal Vref and the current-limited reference signal Vref with the current-limited reference signal Vref The single-ended signal Vout2 is compared to obtain the TTL level signal IO_Timer.

As shown in Figure 1-4, it also includes: an isolation unit, configured to isolate the pulse signal ground GND of the voltage dividing unit from the analog ground AGND of the isolation unit;

a filtering unit, which is configured to filter out the common mode interference of the output signal;

a decoupling unit configured to perform filtering of the connected power supply;

A voltage pull-up unit configured to raise the level and improve the noise tolerance of the signal, as well as enhance immunity to interference.

As shown in FIG. 2 , the voltage dividing unit includes a first resistor R1 and a second resistor R2 connected in series in sequence, the first resistor R1 has a first end and a second end, and the first end of the first resistor R1 is configured to receive the pulse signal Pulse_IN, The second resistor R2 has a first end and a second end, the first end and the second end of the second resistor R2 are respectively connected to both ends of the first capacitor C1, and the first end of the second resistor R2 is connected to the first end of the first resistor R1. The two ends are connected, and the second end of the second resistor R2 is configured to be connected to the pulse signal ground GND;

The isolation unit includes a third resistor R3, which has a first end and a second end, the first end of the third resistor R3 is connected to the second end of the second resistor R2, and the second end of the third resistor R3 is configured to connect to the analog ground AGND;

The pulse signal Pulse_IN is divided by the first resistor R1 and the second resistor R2 to control the voltage of the pulse signal Pulse_IN; then the pulse signal ground GND and the analog ground AGND are isolated through the third resistor R3, eliminating the need for an isolation chip and simplifying the Acquisition circuit structure;

Further, the first resistor R1 and the second resistor R2 of the voltage divider are selected according to the amplitude range of the input pulse signal Pulse_IN, mainly considering resistance and power matching. Generally, the voltage of the divided signal Vout_P is smaller than the back-end precision instrument amplifier. The allowable input voltage range of N1, the voltage is calculated as the voltage of the signal Vout_P=R1*the voltage of the pulse signal Pulse_IN

/(R1+R2);

Further, the high pulse amplitude of the pulse signal Pulse_IN ranges from 16V to 32V, and the first resistor R1 and the second resistor R2 are taken as 100KΩ and 20KΩ, respectively, according to the formula: the voltage of the signal Vout_P=R1*The voltage of the pulse signal Pulse_IN/( R1+R2) can be obtained, the signal Vout_P high-level state voltage range is 2.67V ~ 5.33V, which satisfies the requirement that the voltage of the divided signal Vout_P is less than the allowable input voltage range of the back-end precision instrumentation amplifier N1 -15V ~ +15V;

Further, the resistance value of the third resistor R3 is 1MΩ;

The first current limiting unit includes a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, each of which has a first end and a second end, and the first end of the fifth resistor R5 is connected to the first end of the second resistor R2 , the second end of the fifth resistor R5 is connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is connected to the second end of the fourth resistor R4. The second end of the resistor R2 is connected;

The first filter unit includes a second capacitor C2, the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 Configured to connect to the analog ground AGND;

The second filter unit includes a third capacitor C3, the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 Configured to connect to the analog ground AGND;

The signal Vout_P and the pulse signal ground GND are respectively protected by the fifth resistor R5 and the fourth resistor R4 for current limiting protection. The resistance values of the fourth resistor R4 and the fifth resistor R5 are both 10KΩ. The second capacitor C2 and the third capacitor C3 are completed After the voltage division, the common mode filtering of the output signal Vout_P and the pulse signal ground GND is performed, and the fourth capacitor C4 completes the differential mode filtering between the signal Vout_P and the pulse signal ground GND;

Preferably, the resistance value of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is 1nf;

The differential amplifying unit includes precision instrumentation amplifier N1, which has 1 pin RG1, 2 pin IN-, 3 pin IN+, 4 pin VS-, 5 pin REF, 6 pin OUTPUT, 7 pin VS+ and 8 pin RG2; 2 pin IN- is connected to the second end of the fourth capacitor C4, pin 3 IN+ is connected to the first end of the fourth capacitor C4, pin 1 RG1 and pin 8 RG2 are set in the air;

The first decoupling unit includes a sixth capacitor C6, which has a first end and a second end. The first end of the sixth capacitor C6 is respectively connected to pin 7 VS+ and the first external +15V power supply. The terminal configuration is used to connect the analog ground AGND;

The second decoupling unit includes a fifth capacitor C5, which has a first end and a second end, the first end of the fifth capacitor C5 is connected to pin 5 REF, and the first end of the fifth capacitor C5 is configured to connect to the analog ground AGND, the second end of the fifth capacitor C5 is respectively connected to the 4-pin VS- and the first external -15V power supply;

The precision instrumentation amplifier N1 converts the voltage-divided signal Vout_P and the pulse signal ground GND into a single-ended signal Vout1 that shares the ground with the analog ground AGND, and effectively filters out the common-mode interference of the voltage-divided signal Vout_P and the pulse signal ground GND; The fifth capacitor C5 and the sixth capacitor C6 realize the filtering of the first -15V power supply and the first +15V power supply respectively;

Preferably, the resistance values of the fifth capacitor C5 and the sixth capacitor C6 are both 0.1 μF;

Further, since there is no need to amplify the voltage-divided signal Vout_P, there is no need to configure resistors at the 1-pin and 8-pin gain resistor terminals of the precision instrumentation amplifier N1, and the gain resistor terminals remain open-circuited. According to the calculation formula of the gain G of the precision instrumentation amplifier N1, G=49.4KΩ/R gain resistor+1, the gain resistor end is open circuit is equivalent to the R gain resistor tends to infinity, therefore, in this state, the precision instrumentation amplifier N1 gain G≈1, no amplification, it can be considered as Vout1=Vout_P.

As shown in FIG. 3 , the second current limiting unit includes a sixth resistor R6, which has a first end and a second end, and the first end of the sixth resistor R6 is connected to pin 6 OUTPUT;

The third decoupling unit includes a seventh capacitor C7, which has a first terminal and a second terminal, the first terminal of the seventh capacitor C7 is connected to the second terminal of the sixth resistor R6, and the second terminal of the seventh capacitor C7 is connected to the operation The 4-pin of the amplifier N2A is connected, and the second end of the seventh capacitor C7 is configured to be connected to the analog ground AGND;

Further, pin 4 of the operational amplifier N2A is the negative end of the power supply of the operational amplifier N2A, and the resistance value of the sixth resistor R6 is 5.1KΩ;

The single-ended signal Vout1 is limited by the sixth resistor R6 of the second current limiting unit, and the seventh capacitor C7 realizes the filtering of the negative end of the power supply of the operational amplifier N2A;

The voltage follower unit includes an operational amplifier N2A, which has pins 1, 2, 3, 4 and 8; the pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6;

The fourth decoupling unit includes an eighth capacitor C8, which has a first end and a second end. The first end of the eighth capacitor C8 is respectively connected to pin 8 of the operational amplifier N2A and the second external +15V power supply. The eighth capacitor C8 The second end of the configuration is used to connect the analog ground AGND;

Further, pin 8 of the operational amplifier N2A is the power supply positive terminal of the operational amplifier N2A;

The operational amplifier N2A completes the impedance matching of the input single-ended signal Vout1 and the single-ended signal Vout2, reducing the influence of the voltage drop of the acquisition circuit, and the single-ended signal Vout1 does not change. Therefore, Vout2=Vout1, the line loss is negligible; the eighth capacitor C8 realizes the operation The positive terminal of the power supply of the amplifier N2A and the filtering of the second external +15V power supply.

As shown in FIG. 4 , the third current limiting unit includes a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end. The first end of the seventh resistor R7 is configured to receive the reference signal Vref, and the first end of the seventh resistor R7 is configured to receive the reference signal Vref. The first end of the eight resistor R8 is connected to the 1 pin of the operational amplifier N2A;

Further, the resistance values of the seventh resistor R7 and the eighth resistor R8 are 2KΩ;

The single-ended signal Vout2 and the reference signal Vref are respectively sent to the operational amplifier N2A after current limiting protection by the eighth resistor R8 and the seventh resistor R7;

The comparison unit includes a comparator N3A, which has 2 feet, 3 feet, 4 feet, 5 feet and 12 feet; the 4 feet of the comparator N3A is connected with the second end of the eighth resistor R8, and the 5 feet of the comparator N3A The second end of the resistor R7 is connected, and the 2 pins of the comparator N3A are respectively connected to the fifth input end of the FPGA module;

The third filter unit includes a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7, and the second end of the ninth capacitor C9 It is connected to the 12-pin of the comparator N3A, and the second end of the ninth capacitor C9 is configured to be connected to the analog ground AGND;

The fifth decoupling unit includes a tenth capacitor C10, which has a first terminal and a second terminal. The first terminal of the tenth capacitor C10 is respectively connected to the 3-pin of the comparator N3A and the third external +15V power supply. The tenth capacitor C10 The second end of the configuration is used to connect the analog ground AGND;

The voltage pull-up unit includes a ninth resistor R9, the ninth resistor R9 has a first end and a second end, the first end of the ninth resistor R9 is connected to the 2 pin of the comparator N3A, and the second end of the ninth resistor R9 is connected to an external +3.3V power connection;

Further, pin 12 of the comparator N3A is the negative power supply terminal of the comparator N3A, pin 3 of the comparator N3A is the positive power supply terminal of the comparator N3A, and the resistance value of the ninth resistor R is 4.7KΩ;

The current-limited single-ended signal Vout2 and the reference signal Vref are compared by the comparator N3A, and the voltage range of the high-level state of the signal Vout_P is calculated to be 2.67V~5.33V. Since Vout2=Vout_P, the single-ended signal Vout2 is high-level The state voltage range is also 2.67V~5.33V. According to the voltage range of the single-ended signal Vout2, the reference signal Vref=2.5V is taken. When the voltage of the single-ended signal Vout2 output by the voltage follower unit is higher than the input reference signal Vref of the third current limiting unit When the voltage of the comparison unit is low, the TTL level signal IO_Timer output by the comparison unit is low level, otherwise, it is high level, the comparison unit outputs the TTL level signal IO_Timer to the FPGA module for acquisition and counting processing; the ninth capacitor C9 completes the reference signal For the filtering of Vref, the tenth capacitor C10 realizes the filtering of the positive end of the power supply of the comparator N3A; the ninth resistor R9 is a pull-up resistor, which is used to increase the high level value of the output TTL level signal IO_Timer;

Further, the two IO port channels IO1 and IO2 of the FPGA module receive the TTL level signal IO_Timer output by the comparison unit at the same time, complete the collection and counting of the rising edge and the falling edge respectively, and eliminate the frequency range of the input pulse signal Pulse_IN. Abnormal count, complete the pulse signal acquisition function;

Further, the FPGA module can be implemented by the capture function of CPU chips such as MCU and DSP.

As shown in Figures 1-4, specifically, the filtering unit includes a first filtering unit, a second filtering unit and a third filtering unit;

Specifically, the decoupling unit includes a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit.

The above description is only a preferred embodiment of the present application and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above-mentioned technical features, and should also cover the above-mentioned technical features without departing from the inventive concept. Other technical solutions formed by any combination of its equivalent features. For example, a technical solution is formed by replacing the above-mentioned features with the technical features disclosed in this application (but not limited to) with similar functions.

Claims (9)

1. A direct current pulse signal acquisition circuit, comprising:

a conversion module having a first input configured to receive a first differential pulse signal; the conversion module is configured to convert the first differential pulse signal to obtain a second single-ended signal;

the voltage follower module is provided with a second input end, the second input end is configured to receive the second single-ended signal, and the voltage follower module is configured to realize impedance matching between the second single-ended signal and the signal at the input end of the comparison module to obtain a third single-ended signal;

a comparison module, having a third input end and a fourth input end, where the third input end is configured to receive a fourth reference signal, the fourth input end is configured to receive the third single-ended signal, and the comparison module is configured to compare the fourth reference signal with the third single-ended signal to obtain a fifth level signal;

the FPGA module is provided with a fifth input end and a sixth input end, the fifth input end and the sixth input end are both configured to receive the fifth level signal, and the FPGA module is configured to calculate the number of rising edges and falling edges of the fifth level signal.

2. The direct current pulse signal acquisition circuit according to claim 1, wherein: the conversion module comprises a voltage division unit, a first current limiting unit and a differential amplification unit;

the voltage division unit is provided with an input end, the input end of the voltage division unit is the same as the first input end, and the voltage division unit is configured to receive a first differential pulse signal; the voltage division unit is configured to perform voltage division processing on the first differential pulse signal to obtain a first pulse voltage division signal;

the first current limiting unit is provided with an input end, and the input end of the first current limiting unit is configured to receive the first pulse voltage division signal; the first current limiting unit is configured to limit the current of the first pulse voltage division signal to obtain a current-limited first pulse voltage division signal;

the differential amplification unit is provided with an input end, and the input end of the differential amplification unit is configured to receive the first pulse voltage division signal after current limiting; the differential amplification unit is configured to convert the current-limited first pulse voltage division signal to obtain a second single-ended signal.

3. The direct current pulse signal acquisition circuit according to claim 2, wherein: the voltage following module comprises a second current limiting unit and a voltage following unit;

the second current limiting unit has an input terminal, and the input terminal of the second current limiting unit is the same as the second input terminal and is configured to receive the second single-ended signal; the second current limiting unit is configured to perform current limiting processing on the second single-ended signal to obtain a current-limited second single-ended signal;

the voltage following unit is provided with an input end, and the input end of the voltage following unit is configured to receive the current-limited second single-ended signal; and the voltage following unit is configured to implement impedance matching between the current-limited second single-ended signal and a signal at the input end of the comparison module to obtain a third single-ended signal.

4. A dc pulse signal acquisition circuit according to claim 3, wherein: the comparison module comprises a third current limiting unit and a comparison unit;

the third current limiting unit has two input ends, namely the third input end and the fourth input end, the third input end is configured to receive a fourth reference signal, and the fourth input end is configured to receive the third single-ended signal; the third current limiting unit is configured to perform current limiting processing on the third single-ended signal and the fourth reference signal to obtain a current-limited third single-ended signal and a current-limited fourth reference signal;

the comparison unit is provided with two input ends, and the input ends of the two comparison units are respectively configured to receive the third single-ended signal and the current-limited fourth reference signal; the comparison unit is configured to compare the current-limited fourth reference signal with the current-limited third single-ended signal to obtain a fifth level signal.

5. The direct current pulse signal acquisition circuit according to claim 4, wherein: further comprising: an isolation unit configured to isolate a pulse signal ground GND of the voltage division unit from an analog ground AGND of the isolation unit;

a filtering unit configured to filter out common mode interference of the output signal;

a decoupling unit configured to perform filtering of a connected power supply;

and the voltage pulling unit is configured to improve the level and the noise tolerance of the signal, and enhance the anti-interference capability.

6. The direct current pulse signal acquisition circuit according to claim 5, wherein: the voltage division unit comprises a first resistor R1 and a second resistor R2 which are sequentially connected in series, the first resistor R1 is provided with a first end and a second end, the first end of the first resistor R1 is configured to receive the first differential pulse signal, the second resistor R2 is provided with a first end and a second end, the first end and the second end of the second resistor R2 are respectively connected with two ends of a first capacitor C1, the first end of the second resistor R2 is connected with the second end of the first resistor R1, and the second end of the second resistor R2 is configured to be connected with a pulse signal ground GND;

the first current limiting unit comprises a fifth resistor R5, a fourth resistor R4 and a fourth capacitor C4, wherein the fifth resistor R5, the fourth resistor R4 and the fourth capacitor C4 are respectively provided with a first end and a second end, the first end of the fifth resistor R5 is connected with the first end of the second resistor R2, the second end of the fifth resistor R5 is connected with the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is connected with the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is connected with the second end of the second resistor R2;

the differential amplification unit comprises a precision instrument amplifier N1, wherein the precision instrument amplifier N1 is provided with a 1-pin RG1, a 2-pin IN-, a 3-pin IN +, a 4-pin VS-, a 5-pin REF, a 6-pin OUTPUT, a 7-pin VS + and an 8-pin RG2; the 2 pin IN-is connected with the second end of the fourth capacitor C4, the 3 pin IN + is connected with the first end of the fourth capacitor C4, and the 1 pin RG1 and the 8 pin RG2 are arranged IN a floating mode.

7. The direct current pulse signal acquisition circuit according to claim 6, wherein: the second current limiting unit comprises a sixth resistor R6, wherein the sixth resistor R6 is provided with a first end and a second end, and the first end of the sixth resistor R6 is connected with the 6-pin OUTPUT;

the voltage following unit comprises an operational amplifier N2A which is provided with a pin 1, a pin 2, a pin 3, a pin 4 and a pin 8; and a pin 3 of the operational amplifier N2A is connected to the second end of the sixth resistor R6.

8. The direct current pulse signal acquisition circuit according to claim 7, wherein: the third current limiting unit comprises a seventh resistor R7 and an eighth resistor R8, each of which has a first end and a second end, the first end of the seventh resistor R7 is configured to receive a fourth reference signal, and the first end of the eighth resistor R8 is connected to pin 1 of the operational amplifier N2A;

the comparison unit comprises a comparator N3A with 2, 3, 4, 5 and 12 pins; a pin 4 of the comparator N3A is connected to the second end of the eighth resistor R8, a pin 5 of the comparator N3A is connected to the second end of the seventh resistor R7, and a pin 2 of the comparator N3A is connected to the fifth input terminal of the FPGA module, respectively.

9. The direct current pulse signal acquisition circuit according to claim 8, wherein: the isolation unit comprises a third resistor R3, wherein the third resistor R3 is provided with a first end and a second end, the first end of the third resistor R3 is connected with the second end of the second resistor R2, and the second end of the third resistor R3 is configured to be connected with an analog ground AGND;

the filtering unit comprises a first filtering unit, a second filtering unit and a third filtering unit; the first filtering unit comprises a second capacitor C2, the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the fifth resistor R5, and the second end of the second capacitor C2 is configured to be connected to an analog ground AGND; the second filtering unit includes a third capacitor C3, the third capacitor C3 has a first end and a second end, the first end of the third capacitor C3 is connected to the second end of the fourth resistor R4, and the second end of the third capacitor C3 is configured to be connected to an analog ground AGND; the third filtering unit comprises a ninth capacitor C9, the ninth capacitor C9 has a first end and a second end, the first end of the ninth capacitor C9 is connected to the second end of the seventh resistor R7, the second end of the ninth capacitor C9 is connected to the pin 12 of the comparator N3A, and the second end of the ninth capacitor C9 is configured to be connected to an analog ground AGND;

the decoupling unit comprises a first decoupling unit, a second decoupling unit, a third decoupling unit, a fourth decoupling unit and a fifth decoupling unit, the first decoupling unit comprises a sixth capacitor C6 which is provided with a first end and a second end, the first end of the sixth capacitor C6 is respectively connected with the 7-pin VS + and a first external +15V power supply, and the second end of the sixth capacitor C6 is configured to be connected with an analog ground AGND; the second decoupling unit comprises a fifth capacitor C5, wherein the fifth capacitor C5 has a first end and a second end, the first end of the fifth capacitor C5 is connected with the 5-pin REF, the first end of the fifth capacitor C5 is configured to be connected with an analog ground AGND, and the second end of the fifth capacitor C5 is respectively connected with the 4-pin VS-and a first external-15V power supply; the third decoupling unit comprises a seventh capacitor C7 having a first end and a second end, the first end of the seventh capacitor C7 is connected to the second end of the sixth resistor R6, the second end of the seventh capacitor C7 is connected to the 4-pin of the operational amplifier N2A, and the second end of the seventh capacitor C7 is configured to be connected to an analog ground AGND; the fourth decoupling unit comprises an eighth capacitor C8 having a first end and a second end, the first end of the eighth capacitor C8 is respectively connected to the pin 8 of the operational amplifier N2A and the second external +15V power supply, and the second end of the eighth capacitor C8 is configured to be connected to an analog ground AGND; the fifth decoupling unit comprises a tenth capacitor C10 having a first end and a second end, the first end of the tenth capacitor C10 is connected to the pin 3 of the comparator N3A and the third external +15V power supply, respectively, and the second end of the tenth capacitor C10 is configured to be connected to an analog ground AGND;

the voltage pulling-up unit comprises a ninth resistor R9, the ninth resistor R9 is provided with a first end and a second end, the first end of the ninth resistor R9 is connected with the pin 2 of the comparator N3A, and the second end of the ninth resistor R9 is connected with an external +3.3V power supply.

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