CN1152300C - Single instruction multiple data processing method and device in multimedia signal processor - Google Patents

Abstract

A vector processor includes a scalar register for a scalar value, and a vector register for a vector having a plurality of data elements. Operations performed by a vector processor process 2 or more than 2 vector operands to determine a vector quantity, combine scalar operands and vector operands to determine a vector quantity, and combine 2 or more than 2 scalar operands to determine a scalar quantity. Scalar registers also operate on individual data elements in the vector registers.

Description

Single instruction multiple data processing method and device in multimedia signal processor

field of invention

The present invention relates to digital signal processing technology, in particular to a method and device for parallel processing multiple data elements of each instruction for multimedia functions such as video and audio encoding and decoding.

Background technique

This patent document refers to and refers to the following concurrently filed patent applications:

U.S. Patent Application Serial No. UNKNOWN1, Attorney's Case No. M-4354, entitled "Multiprocessor Operation in a Multimedia Signal Processor";

U.S. patent application serial number UNKNOWN2, attorney case number M-4355, titled "Single-Instruction-Multiple-Data Processing in a Multimedia Signal Processor";

U.S. Patent Application Serial No. UNKNOWN3, Attorney Case No. M-4365, entitled "Efficient Context Saving and Restoring in Multiprocessors (Efficient Context Saving and Restoring in Multiprocessors)";

U.S. patent application serial number UNKNOWN4, attorney case number M-4366, titled "System and Method for Handling Software Interrupts with Argument Passing (system and method for processing software interrupts with parameter passing)";

U.S. Patent Application Serial No. UNKNOWN5, Attorney Case No. M-4367, entitled "System and Method for Handling Interrupts and Exception Events in an Asymmetric Multiprocessor Architecture (System and Method for Handling Interrupts and Exception Events in an Asymmetric Multiprocessor Architecture)" ;

U.S. patent application serial number UNKNOWN6, attorney case number M-4368, titled "Methods and Apparatus for Processing Video Data (method and device for processing video data)";

U.S. Patent Application Serial No. UNKNOWN7, Attorney's Docket No. M-4369, entitled "Single-Instruction-Multiple-Data Processing Using Multiple Banks of Vector Registers"; and

Programmable digital signal processors (DSPs) for multimedia applications (such as real-time video encoding and decoding) require considerable processing power to process large amounts of data within a limited time. Several architectures of digital signal processors are well known. The general-purpose architecture used by most microprocessors generally requires high operating frequencies to provide a DSP with sufficient computing power for real-time video encoding or decoding. This makes this kind of DSP expensive.

A Very Long Instruction Word (VLIW) processor is a type of DSP that has many functional units, most of which perform different, relatively simple tasks. A single instruction of a VLIW DSP can be 128 bytes or longer and have multiple independent sections executed in parallel by independent functional units. VLIW DSPs have strong computing power because many functional units can work in parallel. VLIWDSPs also have relatively low cost because each functional unit is relatively small and simple. A problem with VLIW DSPs is the inefficiency in handling input/output control, communication with a host computer, and other functions that are not amenable to parallel execution by multiple functional units of a VLIW DSP. In addition, the software of VLIW is different from traditional software and is difficult to develop because of the lack of programming tools and programmers who are familiar with the structure of VLIW software. Therefore, a DSP that can provide reasonable cost, high computing power and a familiar programming environment is sought for by multimedia applications.

Contents of the invention

The object of the present invention is to provide a single instruction multiple data processing method and its device.

According to one aspect of the present invention there is provided a processor comprising a scalar register adapted to store a single scalar value; a vector register adapted to store a plurality of data elements; and processing circuitry connected to said scalar register and said vector register, wherein the processing circuit executes multiple operations in parallel in response to a single instruction, each operation combining a data element in said vector register with said scalar value in said scalar register.

According to another aspect of the present invention, there is provided a method of operating a processing circuit to execute an instruction, comprising: reading register data elements constituting a vector-valued component; and performing a parallel operation that associates a scalar value with each data element , to produce a vector result.

According to yet another aspect of the invention, a method of operating a processor includes providing in said processor scalar registers and vector registers, wherein each scalar register is adapted to store a single scalar value and each vector register is adapted to Stores the multiple data elements that make up the vector components; assigns each scalar register a register number that is different from the register number assigned to the other scalar registers; assigns each vector register a register number that is different register numbers assigned to other vector registers, wherein at least some of the register numbers assigned to said vector registers are the same as the register numbers assigned to said scalar registers; forming an instruction comprising a first operand and a second operand number, wherein the first operand is a register number identifying a scalar register and the second operand is a register number identifying a vector register; and executing said instruction to operate on said scalar register identified by said first operand and by said transferring data between data elements in the vector register identified by the second operand.

A multimedia digital signal processor (DSP) according to one aspect of the present invention includes a vector processor that operates on vector data (ie, multiple data elements per operand) to provide high processing power. This processor uses a single instruction multiple data structure of a RISC type instruction set. Programmers can easily adapt to the programming environment for vector processors because it is similar to the programming environment for general-purpose processors with which most programmers are familiar.

The DSP includes a set of general-purpose vector registers. Each vector register has a fixed length, but is divided into individual data elements of a user-selectable length. Therefore, the number of data elements stored in a vector register depends on the length chosen for that element. For example, a 32-byte register can be divided into 32 8-bit data elements, 16 16-bit data elements, or 8 32-bit data elements. The choice of data length and type is determined by the instruction that processes the data associated with the vector register, and one execution datapath of the instruction performs multiple parallel operations, depending on the data length indicated by the instruction.

The instructions of the vector processor can have vector registers or scalar registers as operands, and operate on multiple data elements of multiple vector registers in parallel in order to increase computing power. An exemplary instruction set for the vector processor of the present invention includes: coprocessor interface operations; flow control operations: load/store operations; and logic/arithmetic operations. Logical/arithmetic operations include operations that combine data elements of one vector register with corresponding data elements of one or more other vector registers to produce data elements of a resulting data vector. Other logical/arithmetic operations mix various data elements of one or more vector registers, or combine data elements of a vector register with scalars.

An architectural extension of the vector processor that adds scalar registers each containing a scalar data element. The combination of scalar and vector registers facilitates extending the instruction set of a vector processor to include operations that combine each data element of a vector with a scalar value in parallel. For example, an instruction multiplies multiple data elements of a vector by a scalar value. Scalar registers also provide a location for storing a single data element to be fetched from or stored to a vector register. Scalar registers are also convenient for passing information between the vector processor and the coprocessor (the architecture of the coprocessor provides only scalar registers), and for calculating effective addresses for load/store operations.

According to another aspect of the invention, the vector registers of the vector processor are organized into banks. Each group can be selected as the "current" group and the other as the "alternative" group. The "current group" bit in the control register of the vector processor indicates the current and. To reduce the number of bits required to identify a vector register, some instructions provide only the register number identifying one vector register in the current bank. Load/store instructions have an additional bit to identify any one set of vector registers. Thus, a load/store operation can fetch data to an alternate bank while manipulating data in the current bank. This facilitates software pipelining of image processing and graphics processes, and reduces processor latency when fetching data, since logical/arithmetic operations can be performed out of order with accesses instead of register bank load/store operations. Among other instructions, the substitution group allows the use of double-length vector registers consisting of a vector register from the current group and a corresponding vector register from the substitution group. Such double-length registers can be identified from the instruction syntax. Control bits in the vector processor can be set so that the default vector length is one or two vector registers. Substitution groups also allow the use of fewer explicitly identified operands in complex instruction syntax, such as shuffle, unshuffle, saturate, and operands with two source and two destination registers. Conditional transfer.

The vector processor also implements novel instructions such as average quad, shuffle, deshuffle, pair-wise maximum and exchange, and saturation. These instructions perform operations that are common in multimedia functions such as video encoding and decoding, and replace 2 or more instructions required to implement the same function in other instruction sets. Thus, the vector processor instruction set improves the efficiency and speed of programs in multimedia applications.

Description of drawings

Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein,

FIG. 1 is a block diagram of a multimedia processor according to an embodiment of the present invention.

FIG. 2 is a block diagram of a vector processor of the multimedia processor of FIG. 1. FIG.

FIG. 3 is a block diagram of an instruction fetch unit of the vector processor in FIG. 2 .

FIG. 4 is a block diagram of an instruction fetch unit of the vector processor in FIG. 2 .

5A, 5B and 5C show the steps of the execution pipeline for register-to-register instructions, load instructions, and store instructions of the vector processor of FIG. 2 .

FIG. 6A is a block diagram of the execution data path of the vector processor of FIG. 2 .

FIG. 6B is a block diagram of the register file (register file) of the execution data path of FIG. 6A.

FIG. 6C is a block diagram of the parallel processing logic of FIG. 6A executing the data path.

FIG. 7 is a block diagram of a load/store unit of the vector processor of FIG. 2 .

FIG. 8 is a format of a vector processor instruction set according to an embodiment of the present invention.

Detailed ways

The use of the same reference symbols in different figures indicates similar or identical items.

FIG. 1 shows a block diagram of an embodiment of a multimedia signal processor (MSP) 100 according to an embodiment of the present invention. The multimedia processor 100 includes a processing core 105 composed of a general purpose processor 110 and a vector processor 120 . The processing core 105 is connected to the rest of the multimedia processor 100 through a cache memory (hereinafter referred to as cache) subsystem 130, which includes SRAM 160 and 190, ROM 170 and cache controller 180. Cache controller 180 may configure SRAM 160 as instruction cache 162 and data cache 164 for processor 110 and SRAM 190 as instruction cache 192 and data cache 194 for vector processor 120 .

On-chip ROM 170 contains data and instructions for processors 110 and 120 and can be configured as a cache. In the present embodiment, ROM170 includes: reset and initialization process; Self-test diagnosis process; Interrupt and exception handling program; And sound blaster emulation subroutine; V.34 modem signal processing subroutine; General telephone function; D and 3-D graphics subroutines; and subroutines for audio and video standards such as MPEG-1, MPEG-2, H.261, H.263, G.728, and G.723.

Cache subsystem 130 connects processors 110 and 120 to two system buses 140 and 150 and acts as a cache and switching station for processors 110 and 120 and devices coupled to buses 140 and 150 . The system bus 150 operates at a higher clock frequency than the bus 140, and is connected to a memory controller 158, a local bus interface 156, a DMA controller 154, and a device interface 152, which are respectively external local memory, the local bus of the host computer, the direct Memory access and various analog-to-digital and digital-to-analog converters provide interfaces. A system timer 142 , a UART (Universal asynchronous receiver transceiver) 144 , a bit stream processor 146 and an interrupt controller 148 are connected to the bus 140 . The aforementioned patent applications entitled "Multiprocessor Operation in a Multimedia Signal Processor" and "Methods and apparatus for Processing Video Data" more fully describe the operation of cache subsystem 130 and exemplary devices, processors 110 and 120 The devices are accessed through cache subsystem 130 and buses 140 and 150 .

Processors 110 and 120 execute separate program threads and are also structured differently in order to more efficiently perform the particular tasks assigned to them. The processor 110 is mainly used for control functions, such as the execution of a real-time operating system and similar functions that do not require a lot of repeated calculations. Therefore, the processor 110 does not require strong computing power, and can be implemented with a traditional general-purpose processor structure. The vector processor 120 mainly implements mathematical calculation (number crunching), which includes repetitive operations on common data blocks in multimedia processing. In order to have strong computing power and relatively simple programming, vector processor 120 has a SIMD (Single instruction multiple data, single instruction multiple data) structure; In the present embodiment, most of the data paths in vector processor 120 are 288 bits or 576 bits wide to support vector data operations. Furthermore, the instruction set of the vector processor 120 includes instructions that are particularly suited for multimedia problems.

In this embodiment, the processor 110 is a 32-bit RISC processor, operating at 40 MHz, conforming to the structure of an ARM7 processor, and the ARM7 processor includes a register set defined by the ARM7 standard. The structure and instruction set of the ARM 7 RISC processor are described in the "ARM7DM DataSheet (ARM7DM Product Specification)" Document Number: ARM DDI0010G, which is available from Advance RISC Machines Ltd. The ARM7DM Data Sheet is fully included here for reference. Appendix A illustrates the extension of the ARM7 instruction set of this embodiment.

The vector processor 120 operates on both vectors and scalars. In this embodiment, the vector data processor 120 includes a pipelined RISC engine operating at 80 MHz. The registers of the vector processor 120 include 32-bit scalar registers, 32-bit special purpose registers, two sets of 288-bit vector registers and two sets of double-length (ie 576-bit) vector accumulator registers. Appendix C illustrates the register set of the vector processor 120 of this embodiment. In the present embodiment, processor 120 includes 32 scalar registers, which are identified in instructions by 5-bit register numbers ranging from 0-31. There are also 64 288-bit vector registers organized into two banks of 32 vector registers each. Each vector register can be identified by a 1-bit group number (0 or 1) and a 5-bit vector register number ranging from 0 to 31. Most instructions only access vector registers in the current bank, as indicated by the default bank bit CBANK stored in the vector processor 120 control register VCSR. The second control bit VEC64 indicates whether the register number defaults to a double-length vector register consisting of one register from each bank. The syntax of the instruction distinguishes between register numbers identifying vector registers and register numbers identifying scalar registers.

Each vector register can be divided into multiple data elements whose length can be programmed. Table 1 shows the data types of data elements supported in a 288-bit vector register.

Table 1: type of data Data length explain int8 8 bits (bytes) 8-bit 2's complement between -128 and 127 int9 9 bits (byte 9) 9-bit 2's complement between -256 and 255 int16 16 bits (half word) 16-bit 2's complement between -32,768 and 32,767 int32 32 bits (word) 32-bit 2's complement between -2147483648 and 2147483647. float 32 bits (word) 32-bit IEEE 754 single-precision format

Appendix D further provides a description of the data lengths and types supported in embodiments of the present invention.

For the int9 data type, 9-bit bytes are grouped consecutively in the 288-bit vector register, while for other data types, every ninth bit in the 288-bit vector register is not used. A 288-bit vector register can hold 32 8- or 9-bit integer data elements, 16 16-bit integer data elements, or 8 32-bit integer or floating-point elements. Additionally, 2 vector registers can be combined to pack data elements into double length vectors. In an embodiment of the invention, setting control bit VEC64 in control and status register VCSR puts vector processor 120 in mode VEC64, where double length (576 bits) is the default size of the vector register.

Multimedia processor 100 also includes a set of 32-bit extension registers 115 that are accessible by both processors 110 and 120 . Appendix B describes the extended register sets and their functions in an embodiment of the present invention. Extension registers and scalar and special purpose registers of the vector processor 120 and, in some cases, accessible to the processor 110 . The 2 dedicated "user" extension registers have 2 read ports allowing processors 110 and 120 to read the registers simultaneously. Other extended registers cannot be accessed at the same time.

The vector processor 120 has two alternate states, VP_RUN and VP_IDLE, indicating whether the vector processor 120 is in a working or idle state. When vector processor 120 is in state VP_IDLE, processor 110 can read or write to vector processor 120 scalar and special purpose registers. However, the result of reading or writing a register of the vector processor 120 by the processor 110 when the vector processor 120 is in the VP_RUN state is undefined.

Extensions to the ARM7 instruction set of processor 110 include instructions to access extension registers and scalar or special purpose registers of vector processor 120 . Instructions MFER and MFEP move the data in the extended registers and the scalar or special registers of the vector processor 120 to the general-purpose registers in the processor 110 respectively, and instructions MTER and MTEP move the data in the general-purpose registers in the processor 110 to the extended registers respectively and vector processor 120 in scalar or special purpose registers. The TESTSET instruction reads the extension register and sets bit 30 of the extension register to 1. The instruction TESTSET facilitates consumer/producer synchronization by setting bit 30 to signal to processor 120 that processor 110 has read (or used) the generated result. Other instructions of the processor 110 such as STARTVP and INTVP control the working state of the vector processor 120 .

The processor 110 functions as a master processor to control the operation of the vector processor 120 . Using an asymmetric division of control between processors 110 and 120 simplifies the problem of synchronization between processors 110 and 120 . When the vector processor 120 is in the VP_IDLE state, the processor 110 initializes the vector processor 120 by writing an instruction address into the program counter of the vector processor 120 . Processor 110 then executes the STARTVP instruction, which changes vector processor 120 to state VP_RUN. In state VP_RUN, vector processor 120 fetches instructions through cache subsystem 130 and executes those instructions in parallel with processor 110 continuing to execute its own program. After startup, vector processor 120 continues executing until it encounters an exception, executes a VCJOIN or VCINT instruction that satisfies the appropriate conditions, or is interrupted by processor 110 . Vector processor 120 does this by writing the result to an extension register, writing the result to an address space shared by processors 110 and 120, or leaving the result in a scalar or special purpose register accessed by processor 110 when vector processor 120 re-enters state VP_IDLE , the results of the program execution may be transmitted to the processor 110 .

Vector processor 120 does not handle its own exceptions. When executing the instruction that caused the exception, the vector processor 120 enters the state VP_IDLE and issues an interrupt request to the processor 110 through the direct line. Vector processor 120 remains in state VP_IDLE until processor 110 executes another STARTVP instruction. Processor 110 is responsible for reading register VISRC of vector processor 120 to determine the nature of the exception, possibly handling the exception by reinitializing vector processor 120, and then directing vector processor 120 to resume execution as needed.

The vector processor 120 is interrupted by the INTVP instruction executed by the processor 110, so that the vector processor 120 enters the idle state VP_IDLE. The instruction INTVP can be used, for example, in a multitasking system to switch the execution of a vector processor from one task, such as video decoding, to another task, such as sound card emulation.

The vector processor instructions VCINT and VCJOIN are flow control instructions. If the conditions indicated by the instructions are satisfied, these instructions will stop the execution of the vector processor 120, place the vector processor 120 in the state VP_IDLE, and send an interrupt request to the processor 110, unless This request is blocked. The program counter (special purpose register VPC) of the vector processor 120 indicates the instruction address following the VCINT or VCJOIN instruction. Processor 110 can check the interrupt source register VISRC of vector processor 120 to determine whether the VCINT or VCJOIN instruction caused the interrupt request. Because the vector processor 120 has a large data bus and is more efficient at saving and restoring its registers, software executed by the vector processor 120 should save and restore registers during context switching. The above-mentioned patent application entitled "Efficient Context Saving and Restoring in Multiprocessors" illustrates an exemplary system for context switching.

FIG. 2 shows a main functional block diagram of an embodiment of the vector processor 120 . The vector processor 120 includes an instruction fetch unit (IFU) 210 , a decoder 220 , a scheduler 230 , an execution data path 240 and a load/store unit (LSU) 250 . IFU 210 fetches and processes flow control instructions (such as branches). The instruction decoder 220 decodes one instruction per cycle according to the order of arrival from the IFU 210, and writes the field value decoded from the instruction to the FIFO in the scheduler 230. The scheduler 230 selects field values to be sent to the execution control register according to the needs of executing the operation steps. The choice of dispatch depends on operand dependencies and the availability of processing resources such as execution data path 240 or load/store unit 250 . Execution data path 240 executes logic/arithmetic instructions that operate on vector or scalar data. Load/store unit 250 executes load/store instructions that access the address space of vector processor 120 .

FIG. 3 shows a block diagram of an embodiment of IFU 210 . The IFU includes an instruction buffer divided into a main instruction buffer 310 and an auxiliary instruction buffer 312 . Main buffer 310 contains 8 consecutive instructions, including the instruction corresponding to the current program count. Auxiliary buffer 312 contains eight instructions immediately following the instruction in buffer 310 . IFU 210 also includes a branch target buffer 314 that contains eight consecutive instructions, including the target of the next flow control instruction in buffer 310 or 312 . In this embodiment, the vector processor 120 uses a RISC-type instruction set, where each instruction is 32 bits long, and the buffers 310, 312 or 314 are 8×32-bit buffers connected to the cache by a 256-bit instruction bus Subsystem 130. IFU 210 can load 8 instructions from cache subsystem 130 into any one of buffers 310, 312 or 314 in one clock cycle. Registers 340, 342, and 344 indicate the base address of the load instruction in buffers 310, 312, and 314, respectively.

The multiplexer 332 selects the current instruction from the main instruction buffer 310 . If the current instruction is not a flow control instruction, and the instruction stored in instruction register 330 progresses to the decode stage of execution, then the current instruction is stored in instruction register 330 and the program count is incremented. After the program count is incremented, the last instruction in buffer 310 is selected and the next set of 8 instructions are loaded into buffer 310 . If buffer 312 contains the desired eight instructions, the contents of buffer 312 and register 342 are immediately moved to buffer 310 and register 340, and eight more instructions are prefetched from cache system 130 to auxiliary buffer 312. Adder 350 determines the address of the next set of instructions based on the base address in register 342 and the offset selected by multiplexer 352 . The resulting address obtained by adder 350 is stored in register 342, either when the address is moved from register 342 to register 340 or later. The calculated address is also sent to the cache subsystem 130 along with the request for 8 instructions. If the call to the cache control system 130 last time did not provide the following 8 instructions to the buffer 312 when the buffer 310 requested it, then the last requested instruction, when received from the cache subsystem 130, is stored immediately to buffer 310.

If the current instruction is a flow control instruction, IFU 210 processes the instruction by evaluating the condition of the flow control instruction and updating the program count after the flow control instruction. If the condition cannot be determined because the previous instruction that may change the condition has not been completed, the IFU 210 is stopped. If no branch has taken, the program counter is incremented and the following instruction is selected as described above. If a branch occurs and branch target buffer 314 contains the target of the branch, the contents of buffer 314 and register 344 are moved to buffer 310 and register 340 so that IFU 210 can continue to provide instructions to decoder 220 without Waiting for instructions from cache subsystem 130 .

To prefetch instructions for branch target buffer 314, scanner 320 scans buffers 310 and 312 to locate the next flow control instruction following the current program count. If a flow control instruction is found in buffer 310 or 312, scanner 320 determines from the base address of buffer 310 or 312 containing the instruction, to a set of aligned (aligned) 8 instructions that include the target address of the flow control instruction offset. Multiplexers 352 and 354 provide the offset of the flow control instruction and the base address from register 340 or 342 to adder 350 , which generates a new base address for buffer 314 . The new base address is passed to cache subsystem 130 , which in turn provides 8 instructions to branch target buffer 314 .

When processing flow control instructions such as "decrement and conditional branch" instructions VD1CBR, VD2CBR, and VD3CBR, and "change control register" instruction VCHGCR, IFU 210 can change the value of registers except the program count. When IFU 210 finds an instruction that is not a flow control instruction, the instruction is sent to instruction register 330 and from there to decoder 220.

As shown in FIG. 4 , the decoder 220 decodes an instruction by writing control values into various fields of the FIFO buffer 410 of the scheduler 230 . The FIFO buffer 410 includes 4 rows of flip-flops, each of which can contain 5 information fields to control the execution of an instruction. Rows 0 to 3 hold information for the oldest to newest instructions respectively, with information in the FIFO buffer 410 being moved down to lower rows as older information is removed as instructions complete. The scheduler 230 issues an instruction to the execution stage by selecting the necessary instruction fields to load into the control pipeline 420 comprising the execution registers 421-427. Most instructions can be scheduled so that they are issued and executed out of order. In particular, the order regarding logical/arithmetic operations and load/store operations is arbitrary unless there is an operand dependency between load/store operations and logical/arithmetic operations. A comparison of field values in FIFO buffer 410 indicates whether any operational dependencies exist.

FIG. 5A illustrates a 6-stage execution pipeline for an instruction that implements a register-to-register operation without accessing the vector processor 120 address space. In the instruction fetch stage 511, the IFU 210 fetches an instruction as described above. The instruction fetch stage takes 1 clock cycle unless the IFU 210 is stalled due to pipeline delays, unresolved branch conditions, or delays in the cache subsystem 130 providing prefetched instructions. In the decode stage 512 , the decoder 220 decodes the instruction from the IFU 210 and writes information for the instruction to the scheduler 230 . The decode stage 512 also takes one clock cycle unless there are no rows available in the FIFO 410 for a new operation. During the first cycle of FIFO 410, operations can be issued to control pipe 420, but will be delayed due to issuance of earlier operations.

Execution data path 240 implements register-to-register operations and provides data and addresses for load/store operations. FIG. 6A shows a block diagram of one embodiment of the execution data path 240 and is illustrated along with execution stages 514 , 515 , and 516 . Execution registers 421 provide signals identifying two registers in register file 610 , which are read in one clock cycle during read phase 514 . Register file 610 includes 32 scalar registers and 64 vector registers. FIG. 6B is a block diagram of register file 610 . Register file 610 has 2 read ports and 2 write ports to provide 2 reads and 2 writes per clock cycle. Each port includes a selection circuit 612 , 614 , 616 or 618 and a data bus 613 , 615 , 617 or 619 of 288 bits. Selection circuits such as circuits 612, 614, 616, and 618 are well known in the art and use address signals WRADDR1, WRADDR2, RDADDR1 or RDADDR2, which are obtained from the decoder 220, typically from a 5-bit register number provided in the instruction, A group bit from the instruction or control status register VCSR and the instruction syntax indicating whether the register is a vector register or a scalar register. The data read path can be through the multiplexer 656 to the load/store unit 250 , or through the multiplexers 622 and 624 , through the multiplier 620 ALU 630 , and the accumulator 640 . Most operations read 2 registers, and the read phase 514 completes in one cycle. However, some instructions, such as the multiply and add instruction VMAD and instructions that operate on double-length vectors, require more than 2 registers of data, causing the read phase 514 to take more than one clock cycle.

In the execution stage 515 , the multiplier 620 , the ALU 630 and the accumulator 640 process the data previously read from the register file 610 . Execute phase 515 may overlap with read phase 514 if multiple cycles are required to read the necessary data. The duration of the execution phase 515 depends on the type (integer or floating point) and quantity (read cycle data) of the processed data elements. Signals from execute registers 422, 423, and 425 control the insertion of data into ALU 630, accumulator 640, and multiplier 620 to implement the first step in the execute phase. Signals from execute registers 432 , 433 and 435 control the execution stage 515 to implement the second step.

FIG. 6C shows a block diagram of an embodiment of multiplier 620 and ALU 630. Multiplier 620 is an integer multiplier comprising eight independent 36×36 bit multipliers 626 . Each multiplier 626 includes four 9x9 bit multipliers connected together by control circuitry. For 8-bit and 9-bit data element widths, the control signal from the scheduler 230 disconnects the four 9×9-bit multipliers so that each multiplier 626 performs four multiplications, and the multipliers 620 perform 4 multiplications in one cycle. Implement 32 independent multiplications. For 16-bit data elements, the control circuit operates by concatenating pairs of 9x9-bit multipliers. Multiplier 620 implements 16 parallel multiplications. For 32-bit integer data element types, eight multipliers 626 implement eight parallel multiplications per clock cycle. The result of the multiplication provides a 576-bit result for 9-bit data element widths and a 512-bit result for other data lengths.

ALU 630 can process a 576-bit or 512-bit result from multiplier 620 in 2 clock cycles. ALU 630 includes eight independent 36-bit ALUs 636, each ALU 636 includes a 32x32-bit floating point unit for floating point addition and multiplication. Additional circuitry implements integer shift, arithmetic, and logic functions. For integer operations, each ALU 636 includes 4 units that can independently perform 8-bit and 9-bit operations, and for 16-bit and 32-bit integer data elements, each 2 or 4 can form a group and connect together.

Accumulator 640 accumulates results and includes two 576-bit registers for higher precision of intermediate results.

In the write phase 516 , the results from the execute phase are stored in the register file 610 . In one clock cycle, 2 registers can be written, and input multiplexers 602 and 605 select the 2 data values to be written. The duration of the write phase 516 of an operation depends on the amount of data to be written as a result of the operation and contention from the LSU 250, which may be completing a load instruction by writing to the register file 610. Signals from execute registers 426 and 427 select the registers into which data from logic unit 630 , accumulator 640 and multiplier 620 are written.

Figure 5B shows an execution pipeline 520 that executes a load instruction. The instruction fetch stage 511 , decode stage 512 and issue stage 513 of the execution pipeline 520 are identical to the illustrated register-to-register operations. The read phase 514 is also the same as described above, except that the execution datapath 240 uses data from the register file 610 to determine the address of the calling cache subsystem 130 . In address stage 525 , multiplexers 652 , 654 , and 656 select addresses, which are provided to load/store unit 250 in execute stages 526 and 527 . Information for the load operation is maintained in FIFO 410 during stages 526 and 527 while load/store unit 250 processes the operation.

One embodiment of a load/store unit 250 is shown in FIG. 7 . The cache subsystem 130 is invoked during stage 256 to request data at the address determined by stage 525 . This embodiment uses transaction based cache calls, where multiple devices including processors 110 and 120 can access a local address space through cache subsystem 130 . The requested data may not be available for several cycles after a call to cache subsystem 130, but load/store unit 250 can call the cache subsystem while other calls are pending. Therefore, load/store unit 250 does not stall. The number of clock cycles required for cache subsystem 130 to provide the requested data depends on a data cache 194 hit or miss.

During drive phase 527 , cache subsystem 130 asserts a data signal for load/store unit 250 . The cache subsystem 130 can provide 256 bits (32 bytes) of data to the load/store unit 250 per cycle, and the byte aligner 710 aligns each word of 32 bytes at a corresponding 9-bit storage location. section to provide a 288-bit value. The 288-bit format is convenient for multimedia applications such as MPEG encoding and decoding, which sometimes use 9-bit data elements. A 288-bit value is written to read data buffer 720 . For write phase 528 , scheduler 230 transfers field 4 of FIFO buffer 410 to execute register 426 or 427 and writes the 288-bit value of data buffer 720 to register file 610 .

Figure 5C shows the execution pipeline 530 used to execute the store instruction. The instruction fetch stage 511 , the decode stage 512 and the issue stage 513 of the execution pipeline 530 are the same as those described above. The reading stage 514 is also the same as that described above, except that the data to be stored and the data used for address calculation are read in the reading stage. Data to be stored is written to the write data buffer 730 in the load/store unit 250 . Multiplexer 740 converts data in 9-bit byte format to conventional 8-bit byte format. The translated data from buffer 730 and the associated addresses from address computation stage 525 are sent to cache subsystem 130 during SRAM stage 536 in parallel.

In the vector processor embodiment, each instruction is 32 bits long and has one of the nine formats shown in FIG. 8 and is labeled REAR, REAI, RRRM5, RRRR, RI, CT, RRRM9, RRRM9 ^* , and RRRM9 ^** . Appendix E describes the instruction set for vector processor 120 .

Some load, store, and cache operations using scalar registers have a REAR format when determining an effective address. The REAR format instruction is identified by bits 29-31 as 000b and has 3 operands identified by 3 register numbers, the 2 register numbers SRb and SRi are scalar registers, and the register number Rn can be a scalar or vector register, depending on the bit d. The group bit B either identifies a group for register Rn, or indicates whether vector register Rn is double length if the default vector register size is double length. The opcode field Opc identifies the operation to be performed on the operand, and the field TT indicates the type of transfer as load or store. A typical REAR format instruction is instruction VL, which loads register Rn from an address determined by adding the contents of scalar registers SRb and SRi. If bit A is set, the calculated address is stored in scalar register SRb.

The REAI format instruction is the same as the REAR instruction, except that the 8-bit immediate value from field IMM is used instead of the contents of the scalar register SRi. The REAR and REAI formats have no data element length field.

The RRRM5 format is used for instructions with 2 source operands and one destination operand. These instructions have 3 register operands or 2 register operands and a 5-bit immediate value. The encoding of fields D, S, and M shown in Appendix E determines whether the first source operand Ra is a scalar or vector register; whether the second source operand Rb/IM5 is a scalar register, a vector register, or a 5-bit immediate value; and whether the destination register Rd is a scalar or vector register.

The RRRR format is used for instructions with 4 register operands. Register numbers Ra and Rb indicate source registers. The register number Rd indicates the destination register, while the register number Rc indicates the source or destination register, depending on the field Opc. All operands are vector registers, unless bit S is set to indicate that register Rb is a scalar register. Field DS indicates the data element length of the vector register. Field Opc selects the data type of the 32-bit data element.

The RI format instruction loads an immediate value into a register. Field IMM contains an immediate value of up to 18 bits. Register number Rd indicates the destination register, which is either a vector register or a scalar register within the current bank, depending on bit D. Fields DS and F indicate the length and type of the data element, respectively. For 32-bit integer data elements, the 18-bit immediate value is sign-extended before being loaded into register Rd. For floating-point data elements, bit 18, bits 17 through 10, and bits 9 through 0 represent the sign, exponent, and mantissa, respectively, of a 32-bit floating-point value.

The CT format is used for flow control instructions, and it includes an opcode field Opc, a condition field Cond, and a 23-bit immediate value IMM. Branching occurs when the condition field indicates that the condition is true. Possible condition codes are "always (unconditional)", "Less than (less than)", "equal (equal)", "Less than orequal (less than or equal to)", "greater than (greater than)", "not equal ( Not equal to), "greaterthan or equal" and "overflow". The bits GT, EQ, LT and SO in the status and control register VCSR are used to evaluate the conditions.

The format RRRM9 provides 3 register operands or 2 register operands and a 9-bit immediate value. Combinations of bits D, S, and M indicate which operands are vector registers, scalar registers, or 9-bit immediate values. Field DS indicates the data element length. The RRRM9 ^* and RRRM9 ^** formats are special cases of the RRRM9 format and are distinguished by the opcode field Opc. The RRRM9* format replaces the source register number Ra with the condition code Cond and ID fields. The RRRM9 ^** format replaces the most significant bits of the immediate value with the condition code Cond and bit K. Further descriptions of RRRM9 ^* and RRRM9 ^** are given in Appendix E, involving conditional transfer instruction VCMOV, element mask conditional transfer CMOVM and compare and set mask instruction CMPV.

Although the present invention has been described in conjunction with specific embodiments, these descriptions are only an example of the application of the present invention and should not be regarded as a limitation. In addition, various modifications and combinations of the disclosed embodiment features still belong to the following claims The scope of the invention is defined.

Appendix A

In the exemplary embodiment, processor 110 is a general-purpose processor according to the ARM7 processor standard. For the description of the register in ARM7, refer to the ARM structure file or the ARM7 data sheet (document number ARM DDI 0020C, issued in December 1994).

To interoperate with vector processor 120, processor 110: starts and stops the vector processor; tests vector processor status, including synchronization status; passes data from scalar/special purpose registers in vector processor 120 to general purpose registers; and transfer data from general-purpose registers to scalar/special-purpose registers of the vector processor. There are no direct transfers between the general-purpose registers and the vector registers of the vector processor, and these transfers require memory as an intermediary.

Table A.1 illustrates the ARM7 instruction set extensions for vector processor interaction.

Table A.1: Extended ARM7 instruction set instruction result STARTVP This instruction makes the vector processor enter the VP-RUN state, and it has no effect if the vector processor has already entered the VP-RUN state. STARTVP is implemented as a processor data operation (CDP) class in the ARM7 structure, and no result is returned to the ARM7, and the ARM7 continues its execution. INTVP This instruction makes the vector processor enter the VP-IDEL state, and it has no effect if the vector processor has already entered the VP-IDEL state. INTVP is implemented as a processor data operation (CDP) class in the ARM7 structure, and no result is returned to the ARM7, and the ARM7 continues its execution. TESTSET This instruction reads the user extension register and sets register bit 30 to 1 to provide producer/consumer type synchronization between vector and ARM7 processors. In the ARM7 architecture, TESTSET is implemented as a processor register transfer (MRC) class. ARM7 is blocked until the instruction is executed (registers are transferred). MFER Transferring from extended registers to ARM general purpose registers, in the ARM7 architecture, MFER is implemented as a processor register transfer (MRC) class. ARM7 is blocked until the instruction is executed (registers are transferred). instruction result MFVP Transfer from vector processor scalar/special purpose registers to ARM7 general purpose registers. Unlike other ARM7 instructions, this instruction is only executed when the vector processor is in the VP-IDLE state. Otherwise the result is undefined. In the ARM7 architecture, MFVP is implemented as a processor register transfer (MRC) class. ARM7 is blocked until the instruction is executed (registers are transferred). MTER Transferring from ARM7 general-purpose registers to extended registers, MTER is implemented as a coprocessor register transfer (MCR) class in the ARM7 architecture. ARM7 is blocked until the instruction is executed (registers are transferred). MTVP Transfer from ARM7 general purpose registers to vector processor scalar/special purpose registers, unlike other ARM7 instructions, this instruction is only executed when the vector processor is in VP_IDLE state. Otherwise the result is undefined. In the ARM7 architecture, MTVP is not implemented as a coprocessor register transfer (MCR) class. ARM7 is blocked until the instruction is executed (registers are transferred). CACHE Provides software management of the ARM7 data cache PFTCH Prefetch a cache line and send it to the ARM7 data cache. WBACK Write back a cache line from the ARM7 data cache to memory.

Table A.2 lists the ARM7 exceptions that are detected and reported before the faulting instruction is executed. Exception vector addresses are given in hexadecimal notation.

Table A.2: ARM7 Exceptions exception vector illustrate 0x00000000 ARM7 reset 0x00000004 ARM7 undefined instruction exception 0x00000004 vector processor unreachable exception 0x00000008 ARM7 software interrupt 0x0000000C ARM7 single step exception 0x0000000C ARM7 instruction address breakpoint exception 0x00000010 ARM7 data address breakpoint exception 0x00000010 ARM7 illegal data address exception 0x00000018 ARM7 protection violation exception

The following explains the syntax of the ARM7 instruction set extension. Refer to the ARM structure document or the ARM7 data sheet (document number ARM DDI 0020C, published in December 1994) for the description of the terms and the format of the instruction.

The ARM architecture provides 3 instruction formats for the coprocessor interface:

1. Coprocessor Data Operation (CDP)

2. Coprocessor data transfer (LDC, STC)

3. Coprocessor register transfer (MRC, MCR)

The extension of the MSP structure uses both formats.

The coprocessor data manipulation format (CDP) used for the operation need not be returned to the ARM7. CDP format

30 25 20 15 10 5 0

The CDP format fields have the following conventions: field significance Cond Condition field, which specifies the instruction execution condition OPC coprocessor opcode CRn coprocessor operand register CRd coprocessor destination register CP# Coprocessor number; the following coprocessor numbers are currently used: 1111 - ARM7 data cache 0111 - vector processor, extended registers CP Coprocessor Information CPm coprocessor operand register

Coprocessor data transfer formats (LDC, STC) are used to directly load or store a subset of vector processor registers to memory. The ARM7 processor is responsible for providing word addresses, while the vector processor provides or receives data and controls the number of words transferred. For more details, refer to the ARM7 data sheet. LDC, STC format

30 25 20 15 10 5 0

Format fields have the following conventions: field significance Cond Condition field, which specifies the instruction execution condition P Pre/Post flag u Up/Down bit N Transfer length, since the CRd field does not have enough bits, bit N is used as part of the source or destination register identifier. W write back bit L load/store bit n base register CRn Coprocessor source/destination registers CP# Coprocessor number, the following coprocessor numbers are currently used: 1111 - ARM7 data cache 0111 - vector processor, extended registers Offset unsigned 8-bit immediate offset

The coprocessor register transfer format (MRC, MCR) is used to transfer information directly between the ARM7 and the vector processor. This format is used for transfers between ARM7 registers and vector processor scalar or special purpose registers.

MRC, MCR format

30 25 20 15 10 5 0

The format field has the following conventions: field significance Cond Condition field, which specifies the conditions under which the instruction executes OPC coprocessor opcode L Load/Store bit L=0 is moved to the vector processor L=1 is moved from the vector processor CRn: Crm Coprocessor source/destination registers. Only CRn<1:0>:CRm<3:0> are used Rd ARM source/destination registers CP# Coprocessor numbers, the following coprocessor numbers are currently used: 1111 = ARM7 data cache 0111 = vector processor, extended registers CP Coprocessor Information

Extended ARM instruction description

Extended ARM instructions are described in alphabetical order.

CACHE cache operation

Format

30 25 20 15 10 5 0

assembler syntax

STC{cond}p15, cOpc, <Address>

CACHE{cond}Opc,<Address>

where Cond = {eq, he, cs, cc, mi, pl, vs, vc, hi, Is, ge, It, gt, le, ai, nv} and Opc = {0, 1, 3}. Note that because the CRn field of the LDC/STC format is used to specify the Opc. In the first syntax, the decimal representation of Opcode must start with the letter "C" (that is, CO represents 0). Refer to the ARM7 datasheet for address mode syntax.

illustrate

Execute the instruction only if Cond is true. Opc<3:0> indicates the following operations: Opc<3:0> significance 0000 Write back and invalidate changed cache lines specified by EA. If the matching row contains unchanged data, the row is invalidated and not written back. If no cache line containing the EA can be found, the data cache is left intact. 0001 Write back and invalidate changed cache lines specified by EA pulls. If a matching row contains unchanged data, the row is discarded and not written back. 0010 For PFTCH and WBACK instructions 0011 Invalidate the cache line specified by the EA. Even if the line has been modified, the cache line is invalidated (not written back). This is a privileged operation and will cause an ARM7 protection violation if attempted in user mode other reserve

operate

Refer to the ARM7 datasheet, how the EA is calculated.

abnormal

ARM7 protection violation.

INTVP interrupt vector processor

Format 30 25 20 15 10 5 0

assembler syntax

CDP{cond}p7,1,c0,c0,co

INTVP{cond}

where cond = {eq, ne, cs, cc, mi, pl, vs, vc, hi, Is, ge, it, gt, le, al, ns}.

illustrate

This instruction is only executed when Cond is true. This instruction signals the vector processor to stall. ARM7 does not have to wait for the vector processor to stop and continue to execute the next instruction.

A MFER busy-wait loop should be used to see if the vector processor has stalled after this instruction has been executed. This instruction has no effect if the vector processor is already in VP_IDLE state. Bits 19:12, 7:15 and 3:0 are reserved.

abnormal

Vector processor not available.

MFER transfer from extended register

Format

30 25 20 15 10 5 0

assembler syntax

MRC{cond}p7,2,Rd,cP,cER,0

MFER{cond}Rd, RNAME

where Cond={eg, he, cs, cc, mi, pl, rs, vc, hi, ls, ge, lt, gt, le, al, nv}, Rd={r0,...r15}, P= {0, 1}, ER = {0, . . . 15} and RNAME refers to the architecturally specified register mnemonic (ie, PERO or CSR).

illustrate

This instruction is only executed when Cond is true. The ARM7 register Rd is transferred according to the extended register ER specified by P:ER<3:0>, as shown in the table below. Refer to Chapter 1.2 Explanation of Extended Registers. ER<3:0> P = 0 P=1 0000 UER0 PER0 0001 UER1 PER1 0010 UER2 PER2 0011 UER3 PER3 0100 UER4 PER4 0101 UER5 PER5 0110 UER6 PER6 0111 UER7 PER7 1000 UER8 PER8 1001 UER9 PER9 ER<3:0> P = 0 P=1 1010 UER10 PER10 1011 UER11 PER11 1100 UER12 pER12 1101 UER13 PER13 1110 UER14 PER14 1111 UER15 PER15

Bits 19:17 and 7:5 are reserved

abnormal

Protection violation when attempting to access PERx in user mode.

MFVP Transfer from Vector Processor

Format

assembler syntax

MRC{cond}p7,1,Rd,Crn,CRm,0

MFVP{cond}Rd, RNAME

where Cond={eq, ne, cs, cc, mi, pl, vs, vc, hi, ls, ge, lt, gt, le, al, nv}, Rd={r0,...r15}, CRn= {c0,....c15}, CRm = {c0,....c15} and RNAME refers to the structurally specified register mnemonic (ie, SPO or VCS)

illustrate

This instruction is only executed when Cond is true. ARM7 register Rd is transferred according to the vector processor's scalar/special registers CRn<1:0>:CRm<3:0>. Refer to Section 3.2.3 Register Transfer Vector Processor Register Number Assignment.

Bit 7.5 and CRn<3:2> are reserved.

The vector processor register map is shown below. Refer to Table 15 of the Vector Processor Special Registers (SP0-SP15). CRM<3:0> CRn<1:0>=00 CRn<1:0>=01 CRn<1:0>=10 CRn<1:0>=111 0000 SR0 SR16 SP0 RASR0 0001 SR1 SR17 Sp0 RASR1 0010 SR2 SR18 SP0 RASR2 0011 SR3 SR19 SP0 RASR3 0100 SR4 SR20 SP0 RASR4 0101 SR5 SR21 SP0 RASR5 0110 SR6 SR22 SP0 RASR6 0111 SR7 SR23 SP0 RASR7 1000 SR8 SR24 SP0 RASR8 1001 SR9 SR25 SP0 RASR9 1010 SR10 SR26 SP0 RASR10 1011 SR11 SR27 SP0 RASR11 1100 SR12 SR28 SP0 RASR12 1101 SR13 SR29 SP0 RASR13 1110 SR14 SR30 SP0 RASR14 1111 SR15 SR31 SP0 RASR15

SR0 always reads 32 bits of zero and ignores writes to it.

abnormal

Vector processor not available.

MTER transfer to extended register

Format 30 25 20 15 10 5 0

assembler syntax

MRC{cond}p7,2,Rd,cP,cER,0

MFVP{cond}Rd, RNAME

Here Cond={eq, he, cs, cc, mi, pl, rs, vc, hi, ls, ge, lt, gt, le, al, nv}, Rd={r0,...r15}, P= {0, 1}, ER={0, . . . 15}. RNAME refers to a structurally specified register mnemonic (ie, PERO or CSR).

illustrate

This instruction is only executed if the condition is true. The ARM7 register Rd is transferred according to the extended register ER specified by P:ER<3:0>. as shown in the table below ER<3:0> P = 0 P=1 0000 UER0 PER0 0001 UER1 PER1 0010 UER2 PER2 0011 UER3 PER3 0100 UER4 PER4 0101 UER5 PER5 0110 UER6 PER6 0111 UER7 PER7 1000 UER8 PER8 1001 UER9 PER9 1010 UER10 PER10 1011 UER11 PER11 1100 UER12 PER12 1101 UER13 PER13 1110 UER14 PER14 1111 UER15 PER15

Bits 19:17 and 7:5 spare

abnormal

Protection violation when attempting to access PERx in user mode.

MTVP transfer to vector processor

Format 30 25 20 15 10 5 0

assembler syntax

MRC{cond}p7,1,Rd,Crn,CRm,0

MFVP{cond}Rd, RNAME

Here Cond={eq, ne, cs, cc, mi, pl, vs, vc, hi, ls, ge, lt, gt, le, al, nv}, Rd={r0,...r15}, CRn= {c0,...c15}, CRm={c0,...c15}. RNAME refers to a structurally specified register mnemonic (ie, SPO or VCS).

illustrate

This instruction is only executed when Cond is true. ARM7 register Rd is transferred according to the vector processor's scalar/special registers CRn<1:0>:CRm<3:0>.

Bits 7:5 and CRn<3:2> are reserved.

The vector processor register map is shown below CRM<3:0> CRn<1:0>=00 CRn<1:0>=01 CRn<1:0>=10 CRn<1:0>=111 0000 SR0 SR16 SP0 RASR0 0001 SR1 SR17 SP0 RASR1 0010 SR2 SR18 SP0 RASR2 0011 SR3 SR19 SP0 RASR3 0100 SR4 SR20 SP0 RASR4 0101 SR5 SR21 SP0 RASR5 0110 SR6 SR22 SP0 RASR6 0111 SR7 SR23 SP0 RASR7 1000 SR8 SR24 SP0 RASR8 1001 SR9 SR25 SP0 RASR9 1010 SR10 SR26 SP0 RASR10 1011 SR11 SR27 SP0 RASR11 1100 SR12 SR28 SP0 RASR12 1101 SR13 SR29 SP0 RASR13 1110 SR14 SR30 SP0 RASR14 1111 SR15 SR31 SP0 RASR15

abnormal

Vector processor not available.

PFTCH prefetch

Format

30 25 20 15 10 5

0

assembler syntax

LDC{cond}p15,2,<Address>

PFTCH{cond}<Address>

Here Cond={eq, he, cs, cc, mi, pl, rs, vc, hi, Is, ge, lt, gt, le, al, nv}, refer to the ARM7 data table of the address mode syntax.

illustrate

This instruction is only executed when Cond is true. The cache line specified by the EA is prefetched into the ARM7 data cache.

operate

For how the EA is calculated, refer to the ARM7 datasheet.

Exception: None

STARTVP starts the vector processor

Format

30 25 20 15 10 5

0

assembler syntax

CDP{cond}p7,0,cO,cO,cO

STARTVP{cond}

where cond = {eq, he, cs, cc, mi, pl, vs, vc, hi, Is, ge, it, gt, le, al, nv}.

illustrate

This instruction is only executed when cond is true. This instruction signals the vector processor to start execution and automatically clears VISRC<vjp> and VISRC<vip>. ARM7 does not wait for the vector processor to start execution, and continues to execute the next instruction.

The state of the vector processor must be initialized to the desired state before this instruction is executed. If the vector processor is already in VP-RUN state, this instruction has no effect.

Bits 19:12, 7:5 and 3:0 are reserved.

abnormal

Vector processor not available.

TESTSET test and set

Format

30 25 20 15 10 5

0

assembler syntax

MRC{cond}p7,0,Rd,cO,cER,0

TESTSET{cond}Rd, RNAME

Here cond={eq, he, cs, cc, mi, p1, rs, re, hi, ls, ge, It, gt, le, al, nv}. Rd={r0....r15}, ER={0,...15}, RNAME refers to the structurally specified register mnemonic (ie, VER1 or VASYNC).

illustrate

This instruction is only executed when cond is true. This instruction returns the content of UERX to RD and sets UERX<30> to 1. If ARM7 register 15 is specified as the destination register then UERx<30> returns in the Z bit of the CPSR so that a short busy-wait cycle can be implemented.

Currently, only UER1 is specified to work with read commands.

Bits 19:17 and 7:5 are reserved.

Exception: none

Appendix B

The architecture of the multimedia processor 100 defines the extended registers that the processor 110 accesses with the MFER and MTER instructions. The extended registers include licensed extended registers and user extended registers.

The privileged extension register is mainly used to control the operation of the multimedia signal processor. They are shown in Table B.1

Table B.1: Licensed Extension Registers Number mnemonic illustrate PER0 CTR control register PER1 PVR Processor Type Register PER2 VIMSK Vectored Interrupt Mask Register PER3 ALABR ARM7 instruction address breakpoint register PER4 ADABR ARM7 Data Address Breakpoint Register PER5 SPREG scratch register PER6 STR status register

The control register controls the operation of the MSP100. All bits in CTR are cleared at reset. The definition of the register is shown in Table B.2.

Table B.2: Definition of CTR bit mnemonic illustrate 31-13 Reserved bits are always read as 0 12 VDCI Vector data cache invalidation bit. When set, invalidates all vector processor data caches. Only one invalidation code sequence is supported because cache invalidation operations typically conflict with normal cache operations. 11 VDE Vector data cache enable bit. When cleared, disables the vector processor data cache 10 VICI Vector instruction cache invalidation bit. When set, invalidates the entire vector processor instruction cache. Because cache invalidation operations usually conflict with normal cache operations. So only one invalid code sequence can be supported. 9 VICE Vector instruction cache enable bit. When cleared, disables the vector processor instruction cache. bit mnemonic illustrate 8 ADCI ARM7 data cache invalidation bit. When set, invalidates the entire ARM7 data cache. Since cache invalidation operations typically conflict with normal cache operations, only one invalidation code sequence is supported. 7 ADCE ARM7 data cache enable bit. Disables the ARM7 data cache when cleared. 6 AICI ARM7 instruction cache invalidation bit. When set, invalidates the entire ARM7 instruction cache. Since cache invalidation operations typically conflict with normal cache operations, only one invalidation code sequence is supported. 5 AICE ARM7 instruction cache enable bit. When cleared, disable the ARM7 instruction cache 4 APSE ARM7 processor single step enable bit. When set, causes the ARM7 processor to generate a single-step exception after executing an instruction. The single-step function is only available in user or administrative mode. 3 SPAE Cache scratchpad access enable bit. When set, allows the ARM7 to handle loading from or storing to scratchpad. When cleared, an attempt to load or store to scratchpad generated an ARM7 Invalid Data Address exception 2 VPSE Vector processor single step enable bit. When set, causes the vector processor to generate a vector processor single-step exception after executing an instruction. 1 VPPE Vector processor pipeline enable bit. When cleared, configures the vector processor to operate in non-pipelined mode. At this point in the vector processor execution pipeline, only one instruction is active. 0 VPAE Vector processor access enable bit. When set, causes the ARM7 process to execute extended ARM7 instructions as described above. When cleared, prevents ARM7 processing from executing extended ARM7 instructions. Where such an attempt would generate a vector processor unreachable exception

The Status Register indicates the status of the MSP100. All bits in the field STR are cleared on reset, and the definition of the register is shown in Table B.3.

Table B.3 STR definitions bit mnemonic illustrate 31:23 Reserved bits - always read as 0 twenty two ADAB When an ARM7 data address breakpoint match occurs, the ARM7 data address breakpoint exception bit is set, and the exception is reported through the data exception interrupt. twenty one AIDA An ARM7 Invalid Data Address exception is generated when an ARM7 load or store instruction attempts to access an undecided address or MSP specific scheme is not complete, or when an attempt is made to access an unallowable high-speed scratchpad. This exception can be reported by a data termination interrupt. 20 AIAB When an ARM7 instruction address breakpoint match occurs, the ARM7 instruction address breakpoint exception bit is set. This exception is reported by the prefetch terminated interrupt. 19 AIIA ARM7 invalid instruction address exception. This exception is reported by the prefetch termination interrupt. 18 ASTP ARM7 single step exception. This exception is reported by the prefetch terminated interrupt. 17 APV ARM7 protection violation. The exception is reported by an IRQ interrupt 16 VPUA vector processor unreachable exception reported via coprocessor unreachable interrupt 15-0 reserved - always read as 0

The processor type (Version) register identifies the specific processor type of the multimedia signal processor family of the processor.

The vector processor interrupt mask register VIMSK controls the reporting of vector processor exceptions to processor 110 . Each bit in VIMSK generates an exception for interrupt ARM7 when set along with the corresponding bit in the VISRC register. It does not affect how exceptions are detected for vector processors, but affects whether exceptions will interrupt ARM7. All bits in VIMSK are cleared on reset. The definition of the register is shown in Table B.4

Table B.4: Definition of VIMSK bit mnemonic illustrate 31 DABE Data address breakpoint interrupt enable 30 LABE Instruction Address Breakpoint Interrupt Enable 29 SSTPE Single step interrupt enable 28-14 reserved - always read as 0. 13 FOVE Floating point overflow interrupt enable 12 FINVE Floating point illegal operand interrupt enable 11 FDIVE Floating point divide by zero interrupt enable 10 IOVE Integer overflow interrupt enable 9 IDIVE Integer divide by zero interrupt enable 8-7 reserved - always read as 0 6 VIE VCINT interrupt enable 5 VJE VCJOIN interrupt enable 4-1 reserved - always read as 0 0 CSE context switch enable

ARM7 instruction address breakpoint register assists in debugging ARM7 programs. The definitions of the registers are shown in Table B.5.

Table B.5: Definition of AIABR bit mnemonic illustrate 31-2 LADR ARM7 instruction address 1 Reserved, always read as 0 0 LABE The instruction address breakpoint can be enabled and cleared at reset. If set, when the "ARM7 instruction access address" matches ALABR<31:2>, and VCSR<AIAB> is cleared, an ARM7 instruction address breakpoint exception occurs, and VCSR<ALAB> is set to indicate the exception. When a match occurs, if VCSR<ALAB> is set, the VCSR<AIAB> is cleared and the match is ignored. Report an exception before the instruction executes.

"ARM7 Data Address Breakpoint Register" assists in debugging ARM7 programs. The definitions of the registers are shown in Table B.6.

Table B.6: ADABR definitions bit mnemonic illustrate 31-2 DADR ARM data address. undefined at reset 1 SABE Store "address breakpoint enable", cleared when reset. If set, an "ARM7 Data Address Breakpoint" exception occurs when the upper 30 bits of an ARM7 memory access address match ADABR<31:2> and VCSR<ADAB> is cleared. VCSR<ADAB> is set to indicate an exception. When a match occurs, if VCSR<ADAB> is already set, this VCSR<ADAB> is cleared and the match is ignored. Exceptions are reported before the store instruction is executed. 0 LABE Load address breakpoint enable. Cleared on reset. If set, an "ARM7 Data Address Break" exception occurs when the upper 30 bits of an ARM7 load access address match ADABR<31:2> and VCSR<ADAB> is cleared. VCSR<ADAB> is set to indicate an exception. If VCSR<ADAB> has been set when a match occurs, the VCSR<ADAB> is cleared and the match is ignored. An exception is reported before the load instruction.

The “scratch register” configures the address and size of the scratch pad formed using SRAM in the cache subsystem 130 . Register definitions are shown in Table B.7

Table B.7: Definition of SPREG bit mnemonic illustrate 31-11 SPBASE "Cache base address" indicates the upper 21 bits of the start address of the scratch pad. According to the value in the MSP_BASE register, this value must have a 4M byte offset 10-2 reserve 1-0 SPSIZE Cache size 00->0K (with 4K vector processor data cache) 01->2K (with 2K vector processor data cache) 10->3K (with 1K vector processor data cache) 11-> 4K (without vector processor data cache)

The user extension registers are mainly used for synchronization of processors 110 and 120 . The user extension register is currently defined with only one bit, mapped to bit 30, and instructions such as "MFERR15, UERx" return the value of the bit as the Z flag. Bits UERx<31> and UERx<29:0> are always read as '0'. The user extension registers are described in Table B.8.

Table B.8: User extension registers Number mnemonic illustrate UER0 VPSTATE Vector register status flags. When set, bit 30 indicates that the vector processor is in the VP-RUN state and executing instructions. When cleared, indicates that the vector processor is in the VP_IDLE state and has stopped the VPC from addressing the next instruction for execution. VPSTATE<30> is cleared on Reset. UER1 VASYNC Vector and ARM7 synchronization flags. Bit 30 provides producer/consumer type synchronization between vector and ARM7 processors 120 and 110 . Vector processor 120 can set or clear this flag with the VMOV instruction. This flag can also be set or cleared by ARM7 using MFER or MTER instructions. In addition, flags can be read or set with the TESTSET instruction.

Table B.9 shows the state of the extension registers at power-on reset.

Table B.9: Extended register power-up status register Reset state CTR 0 PVR TBD VIMSK 0 ALABR AIABR<0>＝0, others are undefined ADABR ADABR<0>＝0, others are undefined STR 0 VPSTATE VPSTATE<30>＝0, others are undefined VASYNE VASYNC<3>=0, others are undefined

Appendix C

The architectural state of the vector processor 120 includes 32 32-bit scalar registers; 2 banks of 32 288-bit vector registers; a pair of 576-bit vector accumulation registers; and a bank of 32-bit special purpose registers. Scalar, vector, and accumulator registers are intended for general-purpose programming and support many different data types.

The following notations are used here and in subsequent sections: VR denotes a vector register; VRi denotes the i-th vector register (zero offset); VR[i] denotes the i-th data element in the vector register VR; VR<a:b > denotes bits a to b in the vector register, and VR[i]<a:b> denotes bits a to b of the ith data element in vector register VR.

For multiple elements in a vector register, the vector structure has an additional dimension of data type and data length. Since a vector register has a fixed size, the number of data elements it can hold depends on the length of the element. The MSP structure defines five element lengths as shown in Table C.1.

Table C.1: Length of data elements length name length (bit) Boolean 1 byte 8 Byte 9 9 half word 16 Character 32

MSP structure, which interprets vector data according to the data type and length specified in the instruction. In general, byte, byte9, halfword, and word element lengths are supported in 2's complement (integer) format for most arithmetic instructions. In addition, for most arithmetic instructions, the word element length supports IEEE754 single-precision format.

A programmer can interpret data in any way desired, as long as the sequence of instructions produces meaningful results. For example, programmers are free to use byte 9 to store 8-bit unsigned numbers, which is equivalent to being free to store 8-bit unsigned numbers into byte data elements, and use the provided 2’s complement arithmetic instructions to operate them , as long as the program can handle "false" overflow results.

There are 32 scalar registers, called SR0 through SR31. Scalar registers are 32 bits long and can hold a data element of any defined length. Scalar register SR0 is a special register. Register SR0 always reads 32 bits of zero. Writes to the SR0 register are ignored. Byte, byte9, and halfword data types are stored in the least significant bits of scalar registers, and those most significant bits have undefined values.

Since registers have no data type indicator, the programmer must know the data type of the register used by each instruction. This is different from other structures that consider 32-bit registers to contain 32-bit values. The MSP structure dictates that the result of data type A only correctly modifies the bits defined by data type A. For example, the result of adding byte 9 can only modify the lower 9 bits of the 32-bit target scalar register. The higher 23-bit values are undefined. Unless otherwise indicated with the instruction.

The 64 vector registers are organized into 2 banks of 32 registers each. Group 0 contains the first 32 registers, and group body 1 contains the next 32 registers. One of these two groups is set as the current group and the other is set or replaced. All vector instructions use registers in the current bank by default, except for load/store and register transfer instructions, which can access vector registers in an alternate bank. The CBANK bit in the "Vector Control" and "Status Register VCSR" can be used to set bank 0 or 1 to be the current bank (and the other to be the alternate bank). The vector registers in the current bank are designated as VR0 through VR31 and in the alternate bank as VRA0 through VRA31.

In addition, these two groups can conceptually be combined to provide 32 double-sized vector registers, each register 576 bits. This mode is specified by the VEC64 bit in the control register VCSR. In VEC64 mode, there is no distinction between the current group and the replacement group, and the vector register represents a pair of corresponding 288-bit vector registers in the two groups, that is

VRi<575:0>= _VR1i <287:0>: _VR0i <287:0>

Here VR ₀ i and VR ₁ i represent vector registers with register number VRi in banks 1 and 0, respectively. The double-wide vector registers are called VR0 through VR31.

Vector registers can hold multiple elements of byte, byte9, halfword, or word size, as shown in Table C.2.

Table C.2: Number of elements per vector register element length name element length (bits) Maximum number of elements total number of bits used Byte 9 9 32 288 byte 8 32 256 half word 16 16 256 Character 32 8 256

Mixing multiple element lengths in one register is not supported. Only 256 of the 288 bits are used except for byte 9 elements. Especially every 9th bit is not used. The unused 32 bits in byte, halfword, and word lengths are reserved. Programmers should make no assumptions about their values.

The vector accumulator registers provide storage for intermediate results with higher precision than the result in the destination register. The vector accumulator register consists of four 288-bit registers, VAC1H, VAC1L, VAC0H, and VAC0L. The VAC0H:VAC0L pair is used by 3 instructions by default. In VEC64 mode only, the VCL1H:VAC1L pair is used to emulate 64-byte 9-vector operations. Even if group 1 is set as the current group in VEC32 mode, this VAC0H:VAC0L pair is still used.

To produce an extended-precision result with the same number of elements as in the source vector registers, a pair of registers are used to hold the extended-precision elements, as shown in Table C.3.

Table C.3: Vector accumulator format element length logical viewport VAC format Byte 9 VAC[i]<17:0> VAC0H[i]<8>: VAC0L<i><8:0> for i=0..31 and VAC1H[i-32]<8:0>: VAC1L[i-32]<8:0> at i=32..63 byte VAC[i]<15:0> VAC0H[i]<7:0>: VAC0L<i><7:0> for i=0..31 and VAC1H[i-32]<7:0>: VAC1L[i-32]<7:0 > for i=32..63 half word VAC[i]<31:0> VAC0H[i]<15:0>: VAC0L<i><15:0> for i=0..15 and VAC1H[i-16]<15:0>: VAC1L[i-16] for i= 16..31 Character VAC[i]<63:0> VAC0H[i]<31:0>: VAC0L<i><31:0> for i=0..7 and VAC1H[i-8]<31:0>: VAC1L[i-8]<31:0 > for i = 8..15

The VAC1H:VAC1L pair is used only in VEC64 mode, where the number of elements, byte 9 (and byte), halfword and word are 64, 32 or 16, respectively.

There are 33 special purpose registers that cannot be directly loaded from or stored directly to memory. Sixteen special purpose registers, referred to as RASR0 through RASR15, form an internal return address stack and are used by subroutine call and return instructions. Another 17 32-bit special purpose registers are shown in Table C.4

Table C.4: Special purpose registers Number mnemonic illustrate SP0 VCSR Vector Control and Status Registers SP1 VPC vector program counter SP2 VEPC Vectored Exception Program Counter SP3 VISRC Vectored Interrupt Source Register SP4 VIINS Vectored Interrupt Instruction Register SP5 VCR1 Vector Count Register 1 SP6 VCR2 Vector Count Register 2 SP7 VCR3 Vector Count Register 3 SP8 VGMR0 Vector total mask register 0 SP9 VGMR1 Vector total mask register 1 SP10 VOR0 vector overflow register 0 SP11 VOR1 vector overflow register 1 SP12 VLABR Vector Data Address Breakpoint Register SP13 VDABR Vector Instruction Address Breakpoint Register SP14 VMMR0 Vector Branch Mask Register 0 SP15 VMMR1 Vector Branch Mask Register 1 SP16 VASYNC Vector and ARM7 Synchronization Registers

The definition of vector control and status register VCSR is shown in Table C.5

Table C.5: Definition of VCSR bit mnemonic illustrate 31:18 reserve 17:13 VSP<4:0> Return address stack pointer. The VSP is used by branching to and returning from subroutine instructions to track the top of the stack for internal return addresses. With only 16 entries in the return address stack, VSP<4> is used to detect stack overflow conditions. 12 SO Rollup overflow status flags. This bit is set when the result of an arithmetic operation overflows. Once set, this bit is unchanged until a 0 is written to this bit cleared only when. bit mnemonic illustrate 11 GT Greater than status flag. When SRa>SRb, use the VSUBS command to set this bit. 10 EQ Equal to status flags. When SRa = SRb, set this bit with the VSUBS command. 9 LT Less than status flag. Set this bit with the VSUBS instruction when SRa<SRb 8 SMM Select Transfer Shield. When this bit is set, VMMR0/1 pairs are masked from elements that become arithmetic operations. 7 CEM Two's complement element-wise masking. When this bit is set, the element mask is defined as the 1's complement of VGMR0/1 or VMMR0/1, regardless of which element mask is configured as an arithmetic operation. This bit does not change the contents of VGMR0/1 or VMMR0/1, it only changes the usage of these registers. SMM: CEM coding regulation: 00-use VGMR0/1 as shielding for all elements except VCMOVM. 01 - Use VGMR0/1 as mask for all elements except VCMOVM. 10 - Use VMMR0/1 as mask for all elements except VCMOVM. 11 - Use VMMR0/1 as mask for all elements except VCMOVM. 6 OED Overflow exceptions are prohibited. When this bit is set, processor 120 continues execution after detecting an overflow condition. 5 ISAT Integer saturation method. Combination of OED: ISAT bits specified: 00 None OED: ISAT bit saturated specified: 00 No saturation, reported when an overflow exception occurs. X1 saturates, does not cause overflow bit mnemonic illustrate 10 does not saturate, do not report when an overflow exception occurs. 4:3 RMODE IEEE754 floating-point operation rounding method. 00 rounding direction negative infinity 01 rounding direction zero 10 rounding direction nearest value 11 rounding direction positive infinity 2 FSAT Floating point saturation mode bit (fast IEEE mode) 1 CBANK Current group bit. When set, indicates that group 1 is the current group. When it is cleared, it means that group 0 is the current group. When the VEC64 bit is set, CBANK is ignored. 0 VEC64 64 bytes of 9 vector mode bits. When set, specifies that the vector registers and accumulators have 576 bits. The default mode specifies a length of 32 bytes 9, which is called VEC32 mode.

The vector program counter register VPC is the address of the next instruction to be executed by the vector processor 120 . ARM7 processor 110 should load register VPC before issuing a STARTVP instruction to start vector processor 120 operation.

The Vectored Exception Program Counter VEPC indicates the address of the instruction most likely to cause the latest exception. MSP100 does not support exact exceptions, hence the term "most probable".

The vectored interrupt source register VISRC indicates to the ARM7 processor 110 the source of the interrupt. The appropriate bit is set by hardware when an exception is detected. Software must clear register VISRC before vector processor 120 resumes execution. Setting any bit in register VISRC causes vector processor 120 to enter state VP-IDLE. An interrupt to processor 110 is issued if the corresponding interrupt enable bit is set in VIMSK. Table C.6 defines the contents of register VISRC.

C.6: VISRC definition bit mnemonic illustrate 31 DAB Data address breakpoint exception 30 LAB Instruction address breakpoint exception 29 SSTP single step exception 28-18 reserve 17 IIA invalid instruction address exception 16 IINS invalid instruction exception 15 IDA invalid data address exception 14 UDA Unaligned data access exception 13 FOV floating point overflow exception 12 FINV floating point invalid operand exception 11 FDIV floating point division by zero exception 10 IOV integer overflow exception 9 IDIV integer division by zero exception 8 RASO return address stack overflow exception 7 RASU return address stack underflow exception 6 VIP VCINT is abnormally suspended, execute the STARTVP instruction to clear this bit 5 VJP VCJOIN is suspended abnormally, execute the STARTVP instruction to clear this bit 4-0 VPEV vector processor exception vector

The vector interrupt instruction register VIINS , when the VCINT or VCJOIN instruction is executed to interrupt the ARM7 processor 110, the VCINT or VCJOIN instruction is updated.

Vector count registers VCR1, VCR2 and VCR3 are used for the "decrement and branch" instructions VD1CBR, VD2CBR and VD3CBR and are initialized with the executed loop count. When the VD1CBR instruction is executed, the register VCR1 is decremented by 1. If the count value is not zero and the condition indicated within the instruction matches VFLAG, then branch occurs. Otherwise, no branching occurs. Register VCR1 can be decremented by 1 in any case. Registers VCR2 and VCR3 are used in the same way.

The vector full mask register VGMR0 indicates the elements of the destination vector register to be affected in VEC32 mode and the elements in VR<287:0> in VEC64 mode. Each bit in VGMR0 controls the update of 9 bits in the vector destination register. Specifically, VGMR0<i> controls the update of VRd<9i+8:9i> in VEC32 mode and the update of VR ₀ d<9i+8:9i> in VEC64 mode. Note that VR ₀ d refers to the destination register in bank 0 in VEC64 mode, and VRd refers to the destination register in the current bank. In VEC32 mode, it can be either bank 0 or bank 1. The vector full mask register VGMR0 is used in the execution of all instructions except the VCMOVM instruction.

Vector full mask register VGMR1 indicates the elements within VR<575:288> that will be affected in VEC64 mode. Each bit in register VGMR1 controls the updating of the 9 bits in the vector destination register in group 1. Specifically, VGMR1<i> controls the updating of VR1<9i+8:9i>. The register VGMR1 is not used in VEC32 mode, but in VEC64 mode, it affects the execution of all instructions except the VCMOVM instruction.

The vector overflow register VOR0 represents the elements in VEC32 mode and VR<287:0> in VEC64 mode, which contain the overflow result after a vector arithmetic operation. This register is not modified by scalar arithmetic operations. A bit VOR0<i> setting indicates that the ith element of byte and byte9, the <i, idiv2> element of a halfword, or the (i, idiv4)th element of a word data type operation includes the overflow result. For example, bit 1 and bit 3 may be set to indicate overflow of the first halfword and word elements, respectively. The mapping of bits in VOR0 is different from the mapping of bits in VGMR0 or VGMR1.

The vector overflow register VOR1 is used to represent the elements within VR<575:288> in VEC64 mode, which contain the overflow results after vector arithmetic operations. Register VOR1 is not used in VEC32 mode and is not modified by scalar arithmetic operations. Bit VOR1<i> set indicates that the i-th element of a byte or byte9, (i, idiv2)-th element of a halfword, or (i idiv4)-th element of a word datatype operation includes an overflow result. For example, bit 1 and bit 3, respectively, may be set to indicate overflow of the first halfword or word element in VR<575:288>. The mapping of bits in VOR1 is different from the mapping of bits in VGMR0 or VGMR1.

Vector instruction address breakpoint register VLABR assists in debugging vector programs. The definitions of the registers are shown in Table C.7.

Table C.7: Definition of VLABR bit mnemonic illustrate 31-2 IADR Vector instruction address, undefined at reset 1 reserved bit 0 IABE Instruction address breakpoint enable. Undefined at reset. If set, a "vector instruction address breakpoint" exception occurs when the vector instruction access address matches VLABR<31:2>, and bit VISRC<IAB> is set to indicate the exception. This exception is reported before the instruction is executed.

Vector data address breakpoint register VDABR assists in debugging vector programs. The definition of the register is shown in Table C.8.

Table C.8: Definition of VDABR bit mnemonic illustrate 31-2 DADR Vector data address. undefined at reset 1 SABE Store address breakpoint enable. Undefined on reset. If set, a "Vector Data Address Break" exception occurs when a vector memory access address matches VDABR<31:2>. Bit VISRC<DAB> is set to indicate an exception. An exception is reported before the store instruction is executed. 0 LABE Load address breakpoint enable. Cleared on reset. If set, a "Vector Data Address Break" exception occurs when a vector load access address matches VDABR<31:2>. VISRC<DAB> is set to indicate an exception. An exception is reported before the load instruction executes.

The vector transfer mask register VMMR0 is used for VCMOVM instruction at all times, and is used for all instructions when VCSR<SMM>=1. Register VMMR0 indicates the elements of the destination vector register that will be affected in VEC32 mode, and the elements in VRL<287:0> in VEC64 mode. Each bit in VMMR0 controls the update of 9 bits in the vector destination register. Specifically, VMMR0<i> controls the update of VRd<9i+8:9i> in VEC32 mode, and controls the update of VR ₀ d<9i+8:9i> in VEC64 mode. In VEC64 mode, VR ₀ d represents the destination register in group 0, and VRd refers to the destination register in the current group. In VEC32 mode, VRd can be in group 0 or group 1.

The vector transfer mask register VMMR1 is used for VCMOVM instruction at all times, and is used for all instructions when VCSR<SMM>=1. Register VMMR1 represents the elements in VR<575:288> that are affected in VEC64 mode, and each bit in VMMR1 controls the update of 9 bits in the vector destination register in group 1. Specifically, VGMR1<i> controls the updating of VR1d<9i+8:9i>. Register VGMR1 is not used in VEC32 mode.

The vector and ARM7 synchronization register VASYNC provides producer/consumer style synchronization between processors 110 and 120 . Currently, only bit 30 is defined. When the vector processor 120 is in VP-RUN or VP_IDLE, the ARM7 processor can use the MFER, MTER and TESTSET instructions to access the register VASYNC. Register VASYNC cannot be accessed by ARM7 processors through TVP or MFVP instructions. Because these instructions cannot access special registers beyond the first 16 vector processors. Vector processing can access the register VASYNC through the VMOV instruction.

Table C.9 shows the state of the vector processor at power-on reset.

Table C.9: Vector processor power-on reset states register Reset state SR0 0 all other registers no definition

Special purpose registers are initialized by the ARM7 processor 110 before the vector processor can execute instructions.

Appendix D

Each instruction either implies or specifies the data types of the source and destination operands. Certain instructions have semantics that apply equally to more than one data type. Certain instructions have the semantics of taking one data type for the source and producing a different data type for the result. This appendix describes the data types supported by the exemplary embodiment. The supported data types int8, int9, int16, int32 and floating point numbers are described in Table 1 in this application. Unsigned integer formats are not supported, and unsigned integer values must first be converted to 2's complement format before use. Programmers are free to use arithmetic instructions with unsigned integers or choose any other format as long as overflow is handled appropriately. This structure only defines overflow for 2's complement integers and 32-bit floating-point data types. These structures do not detect the execution of 8, 9, 16, or 32-bit operations that are necessary to detect unsigned overflow. Table D.1 shows the data length supported by the load operation

D1: The data length supported by the load operation Data length in memory Data length in register load operation 8-bit 9-bit Load 8 bits, sign extend to 9 bits (for loading 8-bit 2's complement) 8-bit 9-bit Load 8 bits, zero extend to 9 bits (for loading unsigned 8 bits) 16-bit 16-bit Load 16-bit, (for loading 16-bit unsigned or 2's complement) 32-bit 32-bit Load 32-bit, (for loading 32-bit unsigned, 2's complement integer or 32-bit floating point)

This structure specifies that memory addresses are aligned on data type boundaries. That is, there is no alignment requirement for bytes; for halfwords, the alignment condition is a halfword boundary; for words, the alignment condition is a word boundary.

Table D.2 shows the data lengths supported by storage operations

Table D.2: Data lengths supported by storage operations Data length in register Data length in memory storage operation 8-bit 8-bit Store 8 bits (store 8-bit unsigned or 2's complement) 9-bit 8-bit Cut to the lower 8 bits, store 8 bits (storage 9 bits with 2's complement with unsigned values between 0-255) 16-bit 16-bit Stores 16 bits (stores 16-bit unsigned or 2's complement). 32-bit 32-bit store 32 bits

Because more than one data type is mapped to a register whether scalar or vector. So there may be undefined results for some bits in the destination register for some data types. In fact, except for byte 9 data length operations in vector destination registers and word data length operations in scalar destination registers, there are some bits in the destination register whose value is not defined by the operation. For these bits, the structure specifies that their values are undefined. Table D.3 shows the undefined bits for each data length.

Table D.3: Undefined bits for data length Data length vector destination register scalar destination register byte VR<9i+8>, for i=0 to 31 SR<31:8> Byte 9 none SR<31:9> half word VR<9i+8>, for i=0 to 31 SR<31:16> Character VR<9i+8>, for i=0 to 31 none

Programmers must know the data types of source and destination registers or memory when programming. Data type conversion from one element size to another potentially results in a different number of elements being stored in the vector register. For example, a vector register conversion from halfword to word data type requires 2 vector registers to store the same number of converted elements. Conversely, converting from a word data type that has a user-defined format in a vector register to halfword format results in the same number of elements in one half of the vector register and the remaining bits in the other half. In both cases, datatype conversion produces a structure with a configuration of converted elements whose length differs from that of the source elements.

As a matter of principle, the MSP structure does not provide implicitly changing the number of elements as a result of an operation. This structure means that the programmer must be aware of the consequences of changing the number of elements in the destination register. This structure only provides operations to convert from one data type to another data type of the same length. And when switching from one data type to another with a different length, the programmer needs to make adjustments for the difference in data length.

Dedicated instructions such as VSHFLL and VUNSHFLL described in Appendix E simplify the conversion of vectors of the first data length to vectors of the second data length. In the vector register VRa, the basic steps involved in converting from a smaller element length (such as int8) to a larger element length, (such as int16) 2's complement data type are:

1. Use the byte data type to shuffle the elements in VRa and another vector VRb into two vectors VRc:VRd. Element shift double-wide register VRc in VRa: lower byte of int16 data element in VRd. The elements of VRb whose values are irrelevant are transferred to the high byte of VRc:VRd. This operation effectively moves half of the VRa elements into VRc and the other half into VRd. At this time, the length of each element is doubled from bytes to halfwords.

2. For VRc: The arithmetic shift of elements in VRd is shifted by 8 bits, and it is sign-extended

The basic steps involved in converting a 2's complement number from a larger element size (int16) to a smaller size (eg int8) in vector register VRa are:

1. Check that each element in the int16 data type can be expressed in bytes. Saturation of the element at both ends, if desired, for smaller lengths.

2. Deshuffle the elements in VRa with another vector VRb, and transfer them to two vectors VRc:VRd. In VRa:VRd, the high half of each element is transferred to VRc, and the low half is transferred to VRd. , which effectively aggregates the lower half elements of all elements in VRa in the lower half of VRd.

Some special instructions are provided for the conversion of the following data types: int32 to single precision floating point; single precision floating point to fixed point (X.Y notation); single precision floating point to int32; int8 to int9; int9 to int16; and int16 to int9.

To provide flexibility in vector programming, most vector instructions use element masking and operate only on selected elements in vector registers. The elements identified by "vector full mask register" VGMR0 and VGMR1 are the elements to be modified in the destination register and vector accumulator by vector instructions. For the operation of byte and byte 9 data length, each of the 32 bits in VGMR0 (or VGMR1) identifies an element to be operated, and the bit VGMR0<i> is set to indicate that the element i of the byte length will be acted on . Here i is 0 to 31. For half-word data length operations, every two bits in the 32 bits in VGMR0 (or VGMR1) identify an element to be operated on. Bit VGMR0<2i:2i+1> is set to indicate that element i will be affected, and i is 0 to 15. If only one bit in a pair of VGMR0 is set in a halfword data length operation, only those bits in the corresponding byte are modified. For the word data length operation, in VGMR0 (or VGMR1), every group of 4 bits is set to indicate that an element is operated. Bit VGMR0<4i:4i+3> is set to indicate that element i will be affected, and i is 0 to 7. If not all bits in a 4-bit group in VGMR0 are set for a word data length operation, only those bits of the corresponding byte are modified.

The setting of VGMR0 and VGMR1 can be determined by comparing a vector register with a vector or scalar register or comparing a vector register with an immediate value with the VCMPV instruction, which sets the mask appropriately according to the specified data length. Because scalar registers are defined to contain only one data element, scalar operations (ie, the destination register is a scalar) are not affected by element masking.

For the flexibility of vector programming, most MSP instructions support three forms of vector and scalar operations, which are:

1. Vector = Vector Operation Vector

2. Vector = Vector Operation Scalar

3. Vector = scalar operation scalar

In case 2 the scalar register is specified as the B operand, and the individual elements in the scalar register are copied as many as are needed to match the number of elements in the vector A operand. The copied elements have the same value as the elements in the specified scalar operand. Scalar operands may come from scalar registers or instructions as immediate operands. In the case of immediate operands, if the data length specified for the data type is greater than the available immediate field length, appropriate sign extension is applied.

In many multimedia applications, special attention is paid to the precision of the source immediate and final result. In addition, integer multiply instructions produce "double precision" intermediate results that can be stored in two vector registers.

In general, MSP structures support 8, 9, 16, and 32-bit element 2's complement integer formats and 32-bit element IEEE754 single precision format. Defined overflow, which means that the result exceeds the range of the maximum positive value or the maximum negative value that can be represented by the specified data type. When an overflow occurs, the value written to the destination register is not a valid number, and the defined underflow is only used for floating-point operations.

Unless otherwise specified, all floating-point operations use one of four rounding modes specified by bits VCSR<RMODE>. Certain instructions use the well-known rounding method of truncating zeros (even rounding). These instructions are clearly stated.

Saturation is an important function in many multimedia applications. The MSP structure supports saturation for all 4 integer and floating point operations. Bit ISAT in register VCSR specifies the integer saturation mode. The floating-point saturation mode, also known as the fast IEEE mode, is specified by the FSAT bit in the VCSR. When saturation mode is enabled, results exceeding the maximum positive or maximum negative value are set to the maximum positive or maximum negative value, respectively. In this case, no overflow occurs and the overflow bit cannot be set.

Table D.4 lists the precise exceptions that are detected and reported prior to execution of the fault specification. The exception vector address is expressed in hexadecimal

Table D.4: Precise exceptions exception vector illustrate 0x00000018 Vector processor instruction address breakpoint exception 0x00000018 Vector processor data address breakpoint exception 0x00000018 vector processor invalid instruction exception 0x00000018 Vector Processor Single Step Exception 0x00000018 Vector processor return address stack overflow exception 0x00000018 Vector processor return address stack underflow exception 0x00000018 Vector processor VCINT exception 0x00000018 Vector processor VCJOIN exception

Table D.5 lists imprecise exceptions that are detected and reported after the execution of certain instructions that follow the faulting instruction in the program.

Table D.5: Inexact exceptions exception vector illustrate 0x00000018 vector processor invalid instruction address exception 0x00000018 Vector processor invalid data address exception 0x00000018 Vector processor misaligned data access exception 0x00000018 vector processor integer overflow exception 0x00000018 Vector Processor Floating Point Overflow Exception 0x00000018 Vector processor floating point invalid operand exception 0x00000018 Vector processor floating-point number is divided by 0 exception 0x00000018 vector processor integer division by 0 exception

Appendix E

This vector processor instruction includes eleven categories shown in Table E.1 Table E.1 Vector instruction class summary kind illustrate control flow This class contains instructions for controlling program flow including branch and ARM7 interface instructions. logical (bitwise, masked) This class includes bitwise logical instructions. While the (bitwise, masked) datatype is boolean-like, logic instructions use element-wise masking to modify the result, thus requiring the datatype. shift and rotate (element-wise, masking) This class contains instructions for masking of shift and rotate bits within each element. This class distinguishes the length of elements and is affected by element masking. Arithmetic (element-wise, masking) This class includes element-wise arithmetic instructions. (by element, masking) means that the result of the i-th element is calculated by the i-th element in the source. This class distinguishes the types of elements and is affected by element masking. Multimedia (by element, masked) The instructions contained in this class are used to optimize the application of multimedia (by element, masking). This class distinguishes element types and is affected by element masking. Data type conversion (element-wise, without masking) This class contains instructions for converting elements from one (element-wise, unmasked) data type to another. Instructions of this class support the specified set of data types and are not element-masked because this structure does not support more than one data type in a register. Element-wise arithmetic This class includes instructions for taking two elements from different positions in a vector to produce an arithmetic result. transfer between elements This class includes instructions for taking two elements from different positions in a vector to rearrange the elements. load/store This class includes instructions for loading or storing registers. These directives are not affected by element masking. cache operation This class contains instructions for controlling instruction and data caches. These directives are not affected by element masking. register transfer This class contains instructions for moving data between two registers. These directives are generally not affected by element masking, but some can optionally be element masked.

Table E.2 lists the flow control instructions.

Table E.2: Flow Control Instructions mnemonic illustrate VCBR conditional branch VCBRI indirect conditional branch VD1CBR Decrement VCR1 and conditional branches VD2CBR Decrement VCR2 and conditional branches VD3CBR Decrement VCR3 and conditional branches VCJSR Conditional Rotor Routine VCJSRI indirect condition rotor routine VCRSR return from program condition VCINT Conditional Interrupt ARM7 VC JOIN Conditional confluence with ARM7 VCCS conditional context switch VCBARR conditional barrier VCHGCR Change Control Register (VCSR)

Logical classes support Boolean data types and are affected by element masking. Table E.3 lists flow control instructions.

Table E.3: Logic instructions mnemonic illustrate VNOT NOT--B VAND AND-(A&B) VCAND Complementary AND-(-A&B) VANDC AND Complement -(A&-B) VNAND NAND--(A&B) VOR OR-(A|R) VCOR Complement OR-(-A|R) VORC OR complement -(A|-R) VNOR NOR--(A|R) VXOR XOR-(A^R) VXNOR XOR--(A^R)

Shift/rotate instructions operate on int8, int9, int16 and int32 data types (non-floating point data types), and are affected by element masking. Table E.4 lists the shift/rotate instructions.

Table E.4: Shift and rotate classes mnemonic illustrate VDIV2N power of 2 VLSL logical shift left VLSR logical shift right VROL cycle left VROR cycle right

In general, arithmetic instructions support int8, int9, int16, and int32 and floating-point data types, and are affected by element masking. For specific restrictions on unsupported data types, refer to the detailed description of each instruction below. The VCMPV instruction is not affected by element masking because it works in element masking situations. Table E.5 lists the arithmetic instructions.

Table E.5: Arithmetic classes mnemonic illustrate VASR arithmetic right shift VADD add VAVG average VSUB reduce VASUB subtract absolute value VMUL take VMULA accumulator multiply VMULAF multiply accumulator decimal VMULF multiply decimals VMULFR multiply decimal sum and round VMULL multiplied by low VMAD multiply and add VMADL multiply and add low VADAC Add and accumulate mnemonic illustrate VADACL Add and accumulate low bit VMAC multiply and accumulate VMACF multiply and add decimals VMACL multiply and accumulate low VMAS multiply and subtract from accumulator VMASF Multiply and Subtract Decimal from Accumulator VMASL Multiply and subtract from low accumulator VSATU saturated to the upper limit VSATL Saturation to lower limit VSUBS decrement and conditional VCMPV compare vector and set mask VDIVI In addition to initialization VDIVS remove VASL arithmetic right shift VASA Arithmetic shift of accumulator by one bit

MPEG commands are a class of commands specifically suited for MPEG encoding and decoding, but can be used in different ways. MPEG instructions do not support int8, int9, int16 and int32 data types and are subject to element masking. Table E.6 lists the MPEG directives.

Table E.6: MPEG profiles mnemonic illustrate VAAS3 plus and add(-1, 0, 1) signs VASS3 Plus and minus (-1, 0, 1) signs VEXTSGN2 Extract the (-1, 1) sign VEXTSGN3 Extract the (-1, 0, 1) symbol VXORALL XOR the least significant bits of all elements.

Each data type conversion instruction supports a specific data type and is not affected by element masking because this structure does not support more than one data type in a register. Table E.7 lists the data type conversion instructions.

Table E.7: Data type conversion classes mnemonic illustrate VCVTIF convert integer to float VCVTFF convert floating point to fixed point VROUND Round floating point to integer (supports 4 IEEE rounding modes) VCNTLZ count leading 0 VCVTB9 Convert byte 9 data type

Intrinsic element-wise arithmetic instructions support int8, int9, int16 and int32 and floating-point data types.

Table E.8 lists the internal element-wise arithmetic class instructions.

Table E.8: Inner element arithmetic classes mnemonic illustrate VADDH add two adjacent elements VAVGH Average of two adjacent elements VAVGQ four-element average VMAXE Max Swap Odd/Even Elements

Inter-element transfer instructions support byte, byte 9, halfword, and word data lengths. Table E.9 lists the inter-element transfer instructions.

Table E.9: Transfer classes between elements mnemonic illustrate VESL Element shifted one bit to the left VESR Shift the element to the right VSHFL Even/odd element shuffling VSHFL Even/odd element shuffling VSHFLH High even/odd element shuffle VSH FLL Low even/odd element shuffle VUNSHFL Even/odd element deshuffle VUNSHFLH High even/odd element deshuffle VUNSH FLL Low even/odd element deshuffle

In addition to supporting byte, halfword, and word data lengths, load/store instructions also specifically support data length operations related to byte 9, and are affected by element masking. Table E.10 lists load/store class instructions.

Table E10: Load/store classes mnemonic illustrate VL load VLD load dword QUR load quadword VLCB load from ring buffer VLR Reverse element sequence loading VLW span loading VST storage VSTD store double word VSTQ store quadword VSTCB store to ring buffer VSTR Inverse element sequence storage VSTWS stride store

Most register transfer instructions support int8, int9, int16 and int32 and floating point types, and are not affected by element masking, only VCMOVM instructions are affected by element masking. Table E.11 lists register transfer instructions.

Table E.11: Register transfer classes mnemonic illustrate VLI immediate load VMOV transfer VCMOV conditional branch VCMOVM Conditional branch with element masking VEXTRT extract an element VINSERT insert an element

Table E.12 lists the cache operation class instructions that control the cache subsystem 130 .

Table E.12: Cache operation classes mnemonic illustrate VCACHE Cache Operations to Data or Instruction Cache VPFTCH prefetch to data cache VWBACK Write back from data cache

instruction statement

To simplify the description of the instruction set, terminology is used throughout the appendix. For example, instruction operands are signed 2's complement integers of byte, byte9, halfword, or word length, unless otherwise noted. The term "register" is used to refer to general purpose (scalar or vector) registers, other types of registers are explicitly stated. In assembly language syntax, the suffixes b, b9, h, and w indicate the data length (byte, byte9, halfword, and word) and the integer data type (int8, int9, int16, and int2). In addition, terms and symbols used to describe instruction operands, operations, and assembly language syntax are as follows.

Rd destination register (vector, scalar or special purpose)

Ra, Rb Source registers a and b (vector, scalar or dedicated)

Rc source or destination register c (vector or scalar)

Rs store data source register (vector or scalar)

S 32-bit scalar or special purpose register

VR current group vector register

VRA Alternative Group Vector Register

VR0 0 set of vector registers

VR1 1 set of vector registers

VRd Vector destination register (defaults to current bank unless VRA is specified)

VRa, VRb Vector source registers a and b

VRC Vector source or destination register C

VRS Vector storage data source register

VAC0H Vector Accumulator Register 0 High

VAC0L Vector Accumulator Register 0 Low

VAC1H Vector Accumulator Register 1 High

VAC1L Vector Accumulator Register 1 Low

SRd Scalar destination register

SRa, SRb Scalar source registers a and b

SRb+ Update base register with valid address

SRs Scalar store data source registers

SP Special purpose register

VR[i] The ith element in the vector register VR

VR[i]<a:b> bit a to b of the i-th element in the vector register VR

VR[i]<msb> The most significant bit of the i-th element in the vector register VR

EA Effective address for memory access

MEM memory

BYTE[EA] A byte in memory address EA

HALF[EA] Half word in memory address EA, address EA+1 is bit <15:8>.

WORD[EA] A word in memory address EA, address EA+3 is bit <31:24>.

NumElem The number of elements specified for a given data type. In VEC32 mode, the word

Byte and byte 9, halfword or word data lengths of 32, 16 or 8 respectively; in

In VEC64 mode, the data lengths of byte and byte 9, halfword or word are respectively

64, 32 or 16. NumElem is 0 for scalar operations.

EMASK[i] Indicates the element masking of the i-th element. For byte and byte9, halfword or word count

  According to the length, in VGMR0/1, ~VGMR0/1, VMMR0/1 or ~

Represent 1, 2 or 4 bits in VMMR0/1 respectively. is a scalar operation, even if

EMASK[i]=0 also considers element masking to be set.

MMASK[i] Indicates the element masking of the i-th element. in bytes and byte9, halfword or word count

According to the length, it represents 1, 2 or 4 in VMMR0 or VMMR1

bit.

VCSR Vector Control and Status Register

VCSR<x> Indicates one or more bits in VCSR. "x" is the field name

VPC Vector Processor Program Counter

VECSIZE vector register length, in VEC32 mode is 32, in VEC64 mode is

64.

SPAD scratchpad

C programming constructs are used to describe flow control operations. The exception section is noted as follows:

= Assignment

connect

{X‖Y} Choose between X or Y (not logical OR)

sex Sign extension to the specified data length

sex_dp Extends the sign of a double-precision number with a specified data length

sign (arithmetic) right shift sign extension

zex Zero extension to the specified data length

zero " (logical) shift right zero-extend

《 Shift left (fill with zeros)

trnc7 truncate the first 7 bits (from halfword)

trnc1 Truncate the first 1 bit (from byte 9)

% Modulo operation

|expression| Take the absolute value of the expression

/ Divide (using one of four IEEE rounding modes for floating-point data types)

// Division (rounding with zero rounding mode)

Saturate() For integer types saturated to the maximum negative value or maximum positive value, no overflow will be generated; for

For floating-point data types, saturation can be to positive infinity, positive zero, negative zero, or negative

or infinity.

The general command format is shown in Figure 8 and explained below.

The REAR format is used by the load, store, and cache operation instructions, and the fields in the REAR format have

Has the meaning given in Table E.13 below.

Table E.13: REAR format field significance OPC<4:0> opcode B Bank identifier for the Rn register D. Destination/source scalar register. When set, Rn<4:0> indicates a scalar register. In VEC32 mode, legal values for encoding B:D are: 00 Rn is a vector register in the current bank 01 Rn is a scalar register (in the current bank) 10 Rn is a vector register in the alternate bank 11 undefined In VEC64 mode, legal values for encoding B:D are: 00 Only 4, 8, 16 or 32 bytes are used in vector register Rn 01 Rn is a scalar register 10 All 64 bytes of vector register Rn are used use 11 undefined TT<1:0> The transfer type, indicating a specific load or store operation. See LT and ST code table below. C Cache is off. Set this bit to bypass the data cache on load. This bit is set with the cache-off mnemonic for load and store instructions (link OFF to mnemonic) A Address update, setting this bit updates SRb with valid address. The effective address is calculated by SRb+SRi. Rn<4:0> destination/source register number SRb<4:0> Scalar base register number SRi<4:0> Scalar index register number

Bits 17:15 are reserved and should be zero to ensure compatibility for future extensions of the structure. B: Certain encodings for the D and TT fields are undefined and programmers should not use these encodings because the structure does not specify the expected results when such an encoding is used. Table E.14 shows the scalar load operations (encoded as LT in the TT field) supported by both VEC32 and VEC64 modes.

Table E.14 REAR load operation in VEC32 and VEC64 modes D: LT mnemonic significance 100 .bs9 Load 8 bits into byte 9 length, sign extend 101 .h Load 16 bits into a halfword length 110 .bz9 Load 8 bits into byte 9 length, zero-extended 111 .w Load 32 bits into word length

Table E.15 shows the vector load operations supported by VEC32 mode (encoded as LT in the TT field), when the VCSR<0> bit is cleared.

Table E.15: REAR loading operation in VEC32 mode D: LT mnemonic significance 000 .4 Load 4 bytes from memory into the lower 4 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 4 bytes 9 is sign-extended according to the corresponding 8th bit. 001 .8 Load 8 bytes from memory into the lower 8 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 8 bytes 9 is sign-extended according to the corresponding 8th bit. 010 .16 Load 16 bytes from memory into the lower 16 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 16 bytes 9 is sign-extended according to the corresponding 8th bit. 011 .32 Load 32 bytes from memory into the lower 32 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 32 bytes 9 is sign-extended according to the corresponding 8th bit.

The B bit is used to indicate the current or alternate group.

Table E.16 gives the supported vector load operations in VEC64 mode (encoded as LT in the TT field). At this time the VCSR<0> bit is set.

Table E.16: Load operation of REAR in VEC32 mode B:D:LT mnemonic significance 0000 .4 Load 4 bytes from memory into the lower 4 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 4 bytes 9 is sign-extended according to the corresponding 8th bit. 0001 .8 Load 8 bytes from memory into the lower 8 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 8 bytes 9 is sign-extended according to the corresponding 8th bit. 0010 .16 Load 16 bytes from memory into the lower 16 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 16 bytes 9 is sign-extended according to the corresponding 8th bit. B:D:LT mnemonic significance 0011 .32 Load 32 bytes from memory into the lower 32 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of the 32 bytes 9 is sign-extended according to the corresponding 8th bit. 1000 undefined 1001 undefined 1010 undefined 1011 .64 Load 64 bytes from memory into the lower 64 byte 9 of the register and leave the remaining byte 9 unchanged. Each 9th bit of 64 bytes 9 is sign-extended according to the corresponding 8th bit.

Bit B is used to indicate a 64-byte vector operation, since in VEC64 mode there is no concept of when there are groups and alternative groups.

Table E.17 lists the scalar store operations (encoded as ST in the TT field) supported in both VEC32 and VEC64 modes.

Table E.17: Scalar storage operations for REAR D: ST mnemonic significance 100 .b Store byte or byte 9 length into 8 bits (1 bit truncated from byte 9) 101 .h Storage halfword length becomes 16 bits 110 undefined 111 .w The storage word length becomes 32 bits

Table E.18 lists the vector storage operations supported by VEC32 mode (coded as ST in the TT field), and the VCSR<0> bit is cleared at this time.

Table E18: Vector storage operations of REAR in VEC32 mode D: ST mnemonic significance 000 .4 To store 4 bytes from a register to memory, every 9th bit of the 4 bytes 9 in the register is ignored. 001 .8 To store 8 bytes from a register to memory, every 9th bit of the 8 bytes 9 in the register is ignored. 010 .1b To store 16 bytes from a register to memory, every 9th bit of the 16 bytes 9 in the register is ignored. 011 .32 To store 32 bytes from a register to memory, every 9th bit of the 32 bytes 9 in the register is ignored.

Table E.19 lists the vector storage operations supported by VEC64 mode (encoded as ST in the TT field), when the VCSR<0> bit is set.

Table E.19: REAR vector storage operations in VEC32 mode B: D: ST mnemonic significance 0000 .4 To store 4 bytes from a register to memory, every 9th bit of the 4 bytes 9 in the register is ignored. 0001 .8 To store 8 bytes from a register to memory, every 9th bit of the 8 bytes 9 in the register is ignored. 0010 .16 To store 16 bytes from a register to memory, every 9th bit of the 16 bytes 9 in the register is ignored. 0011 .32 To store 32 bytes from a register to memory, every 9th bit of the 32 bytes 9 in the register is ignored. 1000 undefined 1001 undefined 1010 undefined 1011 .64 To store 64 bytes from a register to memory, every 9th bit of the 64 bytes 9 in the register is ignored.

Bit B is used to indicate 64-byte vector operations, since in VEC64 mode there is no concept of current and alternate groups.

The REAI format is used by load, store, and cache operation instructions. Table E.20 shows the meaning of each field in the REAI format.

Table E.20: REAI format field significance OPC<4:0> opcode B Bank identifier for the Rn register. When set in VEC32 mode, Rn<4:0> indicates the vector register number in the alternate group; when set in VEC64 mode, it indicates full vector (64 bytes) operation. D. Destination/source scalar register. When set, Rn<4:0> indicates a scalar register. Legal values for B:D encoding in VEC32 mode are: 00 Rn is the vector register for the current bank 01 Rn is the scalar register (in the current bank) 10 Rn is the vector register for the alternate bank 11 undefined Legal values for B:D encoding in VEC64 mode are: 00 in vector register Rn only 4, 8, 16 or 32 bytes of Rn are used 01 Rn is a scalar register 10 The entire 64 bytes in vector register Rn are used 11 Undefined TT<1:0> Transfer type, which represents a specific load or store operation. See LT and ST code table below. C Cache off, set this bit to bypass the data cache on load. This bit is set with the Cache-off mnemonic for load and store instructions (link OFF to mnemonic). A Address update, setting this bit updates SRb with valid address. The effective address is calculated by SRb+IM<7:0>. Rn<4:0> destination/source register number SRb<4:0> Scalar base register number IMM<7:0> An 8-bit immediate offset, specified as a two's complement number.

The REAR and REAI formats are used for the same encoding of the transport type. See the REAR format for further encoding details.

The RRRM5 format provides three registers or two registers and a 5-bit immediate operand. Table E.21 defines the fields of the RRRM5 format.

Table E.21: RRRM5 format field significance OP<4:0> opcode D. Destination scalar register. When set, Rd<4:1> indicate a scalar register; when cleared, Rd<4:0> indicate a vector register. S Scalar Rb register. When set, indicates that Rb<4:0> is a scalar register; when cleared, Rb<4:0> is a vector register. SD<1:0> Data width, which is coded as: 00 bytes (for int8 data type) 01 bytes 9 (for int9 data type) 10 halfwords (for int16 data type) 11 words (for int2 or floating point data type) m D: Modifier of the S bit, see the following D: S: M coding table. Rd<4:0> Target D register number Ra<4:0> Source A register number Rb<4:0> or IM5<4:0> The source B register number or 5-bit immediate value depends on the D:S:M encoding, and the 5-bit immediate value is regarded as an unsigned number.

Bits 19:15 are reserved and must be zero to ensure compatibility for future extensions.

All vector register operands refer to the current bank (either bank 0 or bank 1) unless otherwise stated. Table E.22 lists the D:S:M encoding when DS<1:0> is 00, 01 or 10.

Table E22: D:S:M encoding of RRRM5 when DS is not equal to 11 coding Rd Ra Rb/IM5 note 000 VRd VRa VRb Three vector register operands 001 undefined 010 VRd VRa SRb Operand B is a scalar register 011 VRd VRa IM5 Operand B is a 5-bit immediate value 100 undefined 101 undefined 110 SRd SRa SRb three scalar register operands 111 SRd SRa IM5 Operand B is a 5-bit immediate value

When DS<1:0> is 11, the D:S:M code has the following meanings:

Table E.23: D:S:M encoding for RRRM5 when DS is equal to 11 D:S:M Rd Ra Rb/IM5 note 000 VRd VRa VRb Three vector register operands (int32) 001 VRd VRa VRb Three vector register operands (float) 010 VRd VRa SRb Operand B is a scalar register (int32) 011 VRd VRa IM5 The B operand is a 5-bit immediate value (int32) 100 VRd VRa SRb Operand B is a scalar register (float) 101 SRb SRa SRb Three scalar register operands (float) 110 SRd SRa SRb Three scalar register operands (int32) 111 SRd SRa IM5 The B operand is a 5-bit immediate value (int32)

The RRRR format provides four register operands, and Table E.24 shows the fields in the RRRR format.

Table E.24: RRRR format field significance Op<4:0> opcode S Scalar Rb register. When set, it indicates that Rb<4:0> is a scalar register; when cleared, Rb<4:0> is a vector register. DS<1:0> Data length, its encoding is: 00 bytes (for int8 data type) 01 bytes 9 (for int9 data type) 10 half-words (for int16 data type) 11 words (for int32 data type) Rc<4:0> source/destination C register number Rd<4:0> Destination D register number Ra<4:0> Source A register number Rb<4:0> Source B register number

All vector register operands refer to the current bank (either bank 0 or bank 1), unless otherwise stated.

The RI format is only used by load immediate instructions. Table E.25 specifies the fields in the RI format.

Table E.25: RI format field significance D. Destination scalar register. When set, Rd<4:0> indicates a scalar register; when cleared, Rd<4:0> indicates a vector register in the current bank. f Floating point data type. When set, it indicates that it is a floating point data type, and requires DS<1:0> to be 11. DS<1:0> Data length, its encoding is: 00 bytes (for int8 data type) 01 bytes 9 (for intt9 data type) 10 half words (for int16 data type) 11 words (for int32 or float data types) Rd<4:0> Destination D register number IMM<18:0> A 19-bit immediate value

Field F: Some encodings of DS<1:0> are undefined. Programmers should not use these encodings, because this structure does not give expected results when using such encodings. The value loaded into Rd depends on the type of data, as shown in Table E.26.

Table E.26: Load values in RI format Format type of data register operand .b byte (8 bits) Rd<7:0>:=Imm<7:0> .b9 byte (9 bits) Rd<8:0>:=Imm<8:0> .h halfword (16 bits) Rd<15:0>:=Imm<15:0> .w word (32 bits) Rd<31:0>: = sign-extended IMM<18:0> .f floating point (32 bit) Rd<31>:=Imm<18> (symbol) Rd<30:23>:=Imm<17:0> (exponent) Rd<22:13>:=Imm<9:0> (mantissa) Rd<12 :0>:=0

The fields contained in the CT format are shown in Table E.27.

Table E.27: CT format field significance Opc<3:0> opcode Cond<2:0> Transfer condition: 000 unconditional 001 less than 010 equal to 011 less than or equal to 100 greater than 101 not equal to 110 greater than or equal to 111 overflow IMM<22:0> 23-bit immediate numeric offset, specified as a two's complement number.

The transition condition uses the VCSR[GT:EQ:LT] field. The overflow condition uses the VCSR[SO] bit, which takes precedence over the GT, EQ, and LT bits when set. VCCS and VCBARR interpret the Cond<2:0> field differently from the above, please refer to its instruction description for details.

The RRRM9 format specifies three registers or two registers and a 9-bit immediate operand. Table E.28 gives the fields of the RRRM9 format.

Table E.28: RRRM9 format field significance Opc<5:0> opcode D. Destination scalar register. When set, Rd<4:0> indicates a scalar register; when cleared, Rd<4:0> indicates a vector register. S Scalar Rb register. When set, indicates that Rb<4:0> is a scalar register; when cleared, Rb<4:0> is a vector register. DS<1:0> Data width, which is coded as: 00 bytes (for int8 data type) 01 bytes 9 (for int9 data type) 10 halfwords (for int16 data type) 11 words (for int32 or float data types) m For the modifier of the D:S bit, see the following D:S:M encoding table. Rd<4:0> destination register number Ra<4:0> Source A register number Rb<4:0> or IM5<4:0> Source B register number or a 5-bit immediate value, depending on D:S:M encoding. IM9<3:0> Together with IM5<4:0>, a 9-bit immediate value is provided, depending on the D:S:M encoding.

Bits 19:15 are reserved when the D:S:M encoding does not specify an immediate operand, and must be 0 to ensure future compatibility.

All vector register operands refer to the current bank (either bank 0 or bank 1) unless otherwise stated. The D:S:M encodings are the same as those shown in Tables E.22 and E.23 of the RRRM5 format, except that the immediate value is extracted from the immediate field according to the DS<1:0> encoding, see Table E.29 shown.

Table E.29: Immediate values in RRRM9 format DS matching data type B operand 00 int8 Source B<7:0>:=IM9<2:0>:IM5<4:0> 01 int9 Source B<8:0>:=IM9<3:0>:IM5<4:0> 10 int16 Source B<15:0>:=sex(IM9<3:0>:IM5<4:0>) 11 int32 Source B<31:0>:=sex(IM9<3:0>:IM5<4:0>)

Immediate format cannot be obtained for floating-point data types.

Below are the MSP vector instructions in alphanumeric order. Notice:

1. Unless otherwise noted, commands are subject to elemental masking. CT format instructions are not affected by element masking. REAR and REAI format instructions consisting of load, store, and cache instructions are also not affected by element masking.

2. The 9-bit immediate operand cannot be obtained under the floating-point data type.

3. Only the vector form is given in the operating instructions. For scalar operations, only one, the 0th element, is assumed to be defined.

4. For RRRM5 and RRRM9 formats, the following encodings are used for integer data types (b, b9, h, w): D:S:M 000 010 011 110 111 DS 00 01 10 11

5. For RRRM5 and RRRM9 formats, the following encodings are used for floating-point data types: D:S:M 001 100 n/a 101 n/a DS 11

6. For all instructions that may cause overflow, when the VCSR<ISAT> bit is set, the maximum or minimum limit of saturation to int8, int9, int16, int32 is adopted. Correspondingly, floating-point results saturate to -infinity, -0, +0, or +infinity when the VCSR<FSAT> bit is set.

7. According to the syntax rules, .n can be used instead of .b9 to indicate the data length of byte 9.

8. For all instructions, the floating point result returned to the destination register or to the vector accumulator is in IEEE754 single precision format. The floating-point result is written to the lower part of the accumulator, and the upper part is unchanged.

VAAS3 Add and append (-1, 0, 1) sign

Format

assembler syntax

VAAS3.dt VRd, VRa, VRb

VAAS3.dt VRd, VRa, SRb

VAAS3.dt SRd, SRa, SRb

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@V V<-V@S S<-S@S DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of vector/scalar register Ra are added to Rb to produce an intermediate result which is then appended with the sign of Ra; and the final result is stored in vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

if(Ra[i]＞0) extsgn3=1;

else if(Ra[i]<0) extsgn3=-1;

else extsgn3=0;

Rd[i]=Ra[i]+Rb[i]+extsgn3;

}

abnormal

overflow.

VADAC add and accumulate

Format

assembler syntax

VADAC.dt VRc, VRd, VRa, VRb

VADAC.dt SRc, SRd, SRa, SRb

where dt = {b, b9, h, w}.

supported modes S VR SR DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Adds each element of the Ra and Rb operands to each double precision element of the vector accumulator, and stores the double precision sum of each element to the vector accumulator and destination registers Ra and Rd. Ra and Rb use the specified data types, while VAC uses the appropriate double data type (16, 18, 32, and 64 bits correspond to int8, int9, int16, and int32, respectively). The upper bits of each double precision element are stored in VACH and Rc. If Rc = Rd, the result in Rc is undefined.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Aop[i]={VRa[i]‖SRa};

Bop[i]={VRb[i]‖SRb};

VACH[i]:VACL[i]=sex(Aop[i]+Bop[i])+VACH[i]:VACL[i];

Rc[i]=VACH[i];

Rd[i]=VACL[i];

}

VADACL Add and accumulate low bit

Format

assembler syntax

VADACL.dt VRd, VRa, VRb

VADACL.dt VRd, VRa, SRb

VADACL.dt VRd, VRa, #IMM

VADACL.dt SRd, SRa, SRb

VADACL.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:MDS V<-V@Vint8(b) V<-V@Sint9(b9) V<-V@Iint16(h) S<-S@Sint32(w) S<-S@I

Add each element of Ra and Rb/immediate operand to each extended precision element of vector accumulator, store extended precision sum in vector accumulator; return lower precision to destination register Rd. Ra and Rb/immediate use the specified data type, while VAC uses the appropriate double precision data type (16, 18, 32, and 64 bits correspond to int8, int9, int16, and int32, respectively). The high-order bits of each extended-precision element are stored in VACH.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

VACH[i]:VACL[i]=sex(Ra[i]+Bop[i])+VACH[i]:VACL[i];

Rd[i]=VACL[i];

}

VADD plus

Format

assembler syntax

VADD.dt VRd, VRa, VRb

VADD.dt VRd, VRa, SRb

VADD.dt VRd, VRa, #IMM

VADD.dt SRd, SRa, SRb

VADD.dt SRd, SRa, #IMM

where dt = {b, b9, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

Add Ra and Rb/immediate operands, and return the sum to the destination register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=[VRb[i]‖SRb‖sex(IMM<8:0>));

Rd[i]=Ra[i]+Bop[i];

}

abnormal

Overflow, floating-point invalid operand.

VADDH Add two adjacent elements

Format

assembler syntax

VADDH.dt VRd, VRa, VRb

VADDH.dt VRd, VRa, SRb

where dt = {b, b9, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S DS int8.(b) int9(b9) int16(h) int32(w) float(f) illustrate

operate

for(i=0; i<NumElem-1; i++){

Rd[i]=Ra[i]+Ra[i+1];

}

Rd[NumElem-1]=Ra[NumElem-1]+{VRb[0]‖SRb};

abnormal

Overflow, floating-point invalid operand.

programming notes

This directive is unaffected by elemental shielding.

VAND with

Format

assembler syntax

VAND.dt VRd, VRa, VRb

VAND.dt VRd, VRa, SRb

VAND.dt VRd, VRa, #IMM

VAND.dt SRd, SRa, SRb

VAND.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logical AND is performed on Ra and Rb/immediate operand, and the result is returned to the destination register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝Ra[i]<k>&Bop[i]<k>, k＝for all bits in elementi;

}

abnormal

none.

VANDC and complement

Format

assembler syntax

VANDC.dt VRd, VRa, VRb

VANDC.dt VRd, VRa, SRb

VANDC.dt VRd, VRa, #IMM

VANDC.dt SRd, SRa, SRb

VANDC.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logically AND the complement of Ra and Rb/immediate operand and return the result in destination register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=(VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝Ra[i]<k>&～Bop[i]<k>, k＝for all bits in elementi;

}

abnormal

none.

VASA Accumulator Arithmetic Shift

Format

assembler syntax

VASAL.dt

VASAR.dt

where dt = {b, b9, h, w}, and R indicates the shift direction to the left or to the right.

supported modes R left right DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each data element of the vector accumulator register is shifted left by one position and filled from the right with zeros (if R=0), or sign-extended right shifted by one position (if R=1). The result is stored in the vector accumulator.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

if(R＝1)

VACOH[i]:VACOL[i]=VACOH[i]:VACOL[i]sign＞＞1;

else

VACOH[i]: VACOL[i]=VACOH[i]: VACOL[i]<<1;

}

abnormal

overflow.

VASL arithmetic left shift

Format

assembler syntax

VASL.dt VRd, VRa, SRb

VASL.dt VRd, VRa, #IMM

VASL.dt SRd, SRa, SRb

VASL.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S>-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each data element of the vector/scalar register Ra is shifted to the left and filled with zeros from the right. The shift amount is given by the field of the scalar register Rb or IMM, and the result is stored in the vector/scalar register Rd. For those elements that cause overflow, the result is inclusive and up to the most positive or most negative value, according to their signs. The shift amount is defined as an unsigned integer.

operate

shift_amount={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=saturate(Ra[i]<<shift_amount);

}

abnormal

none.

programming notes

Note that Shift-amount is a 5-digit number obtained from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the shift amount, which is less than or equal to the number of bits of the data length. If the shift amount is greater than the specified data length, the elements will be filled with zeros.

VASR Arithmetic shift right

Format

assembler syntax

VASR.dt VRd, VRa, SRb

VASR.dt VRd, VRa, #IMM

VASR.dt SRd, SRa, SRb

VASR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each data element of the vector/scalar register Ra is arithmetically right-shifted, the most significant bit position is sign-extended, the shift amount is given in the least significant bit of the scalar register Rb or IMM field, and the result is stored in the vector/scalar register Rd middle. The shift amount is specified as an unsigned integer.

operate

shift_amount={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMAS[i]; i++)(

Rd[i]=Ra[i]sign＞＞shift_amount;

}

abnormal

none.

programming notes

Note that Shift-amount is a 5-digit number obtained from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the shift amount, which is less than or equal to the number of bits of the data length. If the shift amount is greater than the specified data length, the elements will be filled with sign bits.

VASS3 plus and minus (-1, 0, 1) symbols

Format

assembler syntax

VASS3.dt VRd, VRa, VRb

VASS3.dt VRd, VRa, SRb

VASS3.dt SRd, SRa, SRb

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@V V<-V@S S<-S@S DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of vector/scalar register Ra are added to Rb to produce an intermediate result from which the sign of Ra is then removed; the final result is stored in vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

if(Ra[i]＞0) extsgn3=1;

else if(Ra[i]<0) extsgn3=-1;

else extsgn3=0;

Rd[i]=Ra[i]+Rb[i]-extsgn3;

}

abnormal

overflow.

VASUB The absolute value of the subtraction operation

Format

assembler syntax

VASUB.dt VRd, VRa, VRb

VASUB.dt VRd, VRa, SRb

VASUB.dt VRd, VRa, #IMM

VASUB.dt SRd, SRa, SRb

VASUB.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@V V+V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

The contents of the vector/scalar register Rb or the IMM field are subtracted from the contents of the vector/scalar register Ra, and the absolute value result is stored in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=[Rb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]＝|Ra[i]～Bop[i]|;

abnormal

Overflow, floating point invalid operand.

programming notes

If the result of the subtraction is the most negative number, overflow will occur after the absolute value operation. If saturation mode is enabled, the result of this absolute value operation will be the largest positive number.

VAVG two-element average

Format

assembler syntax

VAVG.dt VRd, VRa, VRb

VAVG.dt VRd, VRa, SRb

VAVG.dt SRd, SRa, SRb

where dt = {b, b9, h, w, f}. Use VAVGT on integer data types to specify a "truncate" rounding mode.

supported modes D:S:M V<-V@V V<-V@S S<-S@S DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

The contents of vector/scalar register Ra are added to the contents of vector/scalar register Rb to produce an intermediate result; the intermediate result is then divided by 2 and the final result is stored in vector/scalar register Rd. For integer data types, the rounding mode is truncate if T=1, and truncate zeros if T=0 (the default). For floating-point data types, the rounding mode is specified by VCSR<RMODE>.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=(Rb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]=(Ra[i]+Bop[i])//2;

}

abnormal

none.

VAVGH Average of two adjacent elements

Format

assembler syntax

VAVGH.dt VRd, VRa, VRb

VAVGH.dt VRd, VRa, SRb

where dt = {b, b9, h, w, f]. Use VAVGHT on integer data types to specify a "truncate" rounding mode.

supported modes D:S:M V<-V@V V<-V@S DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

For each element, two adjacent pairs of elements are averaged. For integer data types, the rounding mode is truncate if T=1, and truncate to zero for T=0 (the default). For floating-point data types, the rounding mode is specified by VCSR<RMODE>.

operate

for(i=0; i<NumElem-1; i++){

Rd[i]=(Ra[i]+Ra[i+l])//2;

}

Rd[NumElem-1]=(Ra[NumElem-1)+{VRb[0]∥SRb})//2;

abnormal

none.

programming notes

This directive is unaffected by elemental masking.

VAVGQ four average

Format

assembler syntax

VAVGQ.dt VRd, VRa, VRb

where dt = {b, b9, h, w}. Use VAVGQT for integer data types to indicate "truncate" rounding mode.

supported modes D:S:M V<-V@V DS int8(b) int9(b9) int16(h) int32(w)

illustrate

This command is not supported in VEC64 mode.

As shown in the figure below, the average of 4 elements is calculated using the truncation mode specified by T (1 is truncation, 0 is truncation, default). Note that the leftmost element (D _n-1 ) is undefined.

operate

for(i=0; i<NumElem-1; i++){

Rd[i]=(Ra[i]+Rb[i]+Ra[i+1]+Rb[i+1])//4:

}

abnormal

none.

VCACHE Cache operation

Format

assembler syntax

VCACHE.fc SRd, SRi

VCACHE.fc SRb, #IMM

VCACHE.fc SRb+, SRi

VCACHE.fc SRb+, #IMM

where fc = {0, 1}.

illustrate

This command is used for software management of vector data cache. When part or all of the data cache is configured like temporary storage, this instruction has no effect on temporary storage.

The following options are supported: FC<2:0> significance 000 Invalidate the modified cache line that was written back and had its tag match the EA. If a matching row contains unchanged data, invalidate the row without writing it back. If no cache line is found to contain an EA, the data cache remains untouched. 001 Writes back and invalidates the modified cache line specified by the EA's index. If a matching row contains unchanged data, invalidate the row without writing it back. other undefined

operate

abnormal

none.

programming notes

This directive is unaffected by elemental masking.

VCAND complement and

Format

assembler syntax

VCAND.dt VRd, VRa, VRb

VCAND.dt VRd, VRa, SRb

VCAND.dt VRd, VRa, #IMM

VCAND.dt SRd, SRa, SRb

VCAND.dt SRd, SRa, #IMM

where dt = (b, b9, h, w). Note that .w and .f indicate the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logically AND the complement of Ra and Rb/immediate operand and return the result in destination register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝～Ra[i]<k>&Bop[i]<k>，k＝for all bits in elementi;

}

abnormal

none.

VCBARR conditional barrier

Format

assembler syntax

VCBARR.cond

where cond={0-7}. Each condition will be given a mnemonic after it.

illustrate

This instruction and all following instructions (those appearing later in the program sequence) are stalled as long as this condition remains in effect. The interpretation of the Cond<2:0> field is different from other conditional instructions in the CT format.

The following conditions are currently defined: Cond<2:0> significance 000 All earlier instructions (that occur earlier in the program sequence) are waited for to complete execution before executing any later instructions. other undefined

operate

while(Cond=true)

stall all later instructoins;

abnormal

none.

programming notes

This instruction is provided for software to enforce the serial execution of instructions. This directive can be used to force precise reporting of ambiguous exceptions. For example, if the instruction is used immediately after an arithmetic instruction that causes an exception, the exception will be reported in the program counter addressed by the instruction.

VCBR conditional transfer

Format

assembler syntax

VCBR.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

Branch if Cond is true, this is not a delayed transfer.

operate

If((Cond=VCSR[SO,GT,EQ,LT])|(Cond=un))

VPC＝VPC+sex(Offset<22:0>*4);

elseVPC=VPC+4;

abnormal

Invalid instruction address.

VCBRI indirect conditional transfer

Format

assembler syntax

VCBRI.cond SRb

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

Branches indirectly if Cond is true. This is not delayed transfer.

operate

If((Cond=VCSR[SO,GT,EQ,LT])|(Cond=un))

VPC=SRb<31:2>:b'00;

elseVPC=VPC+4;

abnormal

Invalid instruction address.

VCCS Conditional Field Conversion

Format

assembler syntax

VCCS #Offset

illustrate

If VIMSK<cse> is true, jump to the scene conversion subroutine. This is not delayed transfer.

If VIMSK<cse> is true, save VPC+4 (return address) to the return address stack. If not true, continue execution from VPC+4.

operate

If(VIMSK<cse>=1){

If(VSP<4>＞15){

VISRC<RASO>=1;

Signal ARM7 with RASO exception;

VP STATE=VP_IDLE;

}else{

RSTACK[VSP<3:0>]＝VPC+4;

VSP<4:0>＝VSP<4:0>+1;

VPC＝VPC+sex(Offset<22:0>*4);

}

}else VPC=VPC+4;

abnormal

Return address stack overflow.

VCHGCR Change Control Register

Format

assembler syntax

VCHGCR Mode

illustrate

This instruction changes the operating mode of the vector processor

Each bit in Mode is specified as follows: Way significance bit1:0 These two bits control the VCSR<CBANK> bits. Code designation: 00-no change 01-clear VCSR<CBANK> bit 10-set VCSR<CBANK> bit 11-trigger VCSR<CBANK> bit bits3: 2 These two bits control the VCSR<SMM> bits. Code designation: 00-no change 01-clear VCSR<SMM> bit 10-set VCSR<SMM> bit 11-trigger VCSR<SMM> bit bit5: 4 These two bits control the VCSR<CEM> bit. Code specification: 00-no change 01-clear VCSR<CEM>bit 10-set VCSR<CEM>bit 11-trigger VCSR<CEM>bit other undefined

operate

abnormal

none.

programming notes

This instruction is provided by hardware to change the control bits in VCSR in a more efficient way than VMOV instruction.

VCINT conditional interrupt ARM7

Format

assembler syntax

VCINT.cond #ICODE

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

If Cond is true, stop execution and interrupt the ARM7 when enabled.

operate

If((Cond=VCSR[SO,GT.EQ,LT])|(Cond=un)){

VISRC<vip>=1;

VIINS = [VCINT.cond#ICODE instruction];

VEPC=VPC;

If(VIMSK<vie>＝1)signal ARM7 interrupt;

VP_STATE=VP_IDLE;

}

else VPC=VPC+4;

abnormal

VCINT interrupt.

VCJOIN joins with ARM7 task conditions

Format

assembler syntax

VCJOIN.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

If Cond is true, stop execution and interrupt the ARM7 when enabled.

operate

If((Cond=VCSR[SO,GT,EQ,LT])|(Cond=un)){

VISRC<vjp>=-1;

VIINS = [VCJOIN.cond#Offset instruction];

VEPC=VPC;

If(VIMSK<vje>＝1)signal ARM7 interrupt;

VP_STATE=VP_IDLE;

}

else VPC=VPC+4;

abnormal

VCJOIN interrupted.

VCJSR Conditional jump to subroutine

Format

assembler syntax

VCJSR.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

If Cond is true, jump to the subroutine. This is not delayed transfer.

If Cond is true, save VPC+4 (return address) to the return address stack. If not true, execution continues from VPC+4.

operate

If((Cond=VCSR[SO,GT.EQ,LT])|(Cond=un))(

If(VSP<4>＞15){

VISRC<RASO>=1;

Signal ARM7 with RASO exception;

VP_STATE=VP_IDLE;

}else{

RSTACK[VSP<3:0>]＝VPC+4;

VSP<4:0>＝VSP<4:0>+1:

VPC＝VPC+sex(Offset<22:0>*4);

}

}else VPC=VPC+4;

abnormal

Return address stack overflow.

VCJSRI indirect conditional jump to subroutine

Format

assembler syntax

VCJSRI.cond SRb

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

Indirect jump to subroutine if Cond is true. This is not delayed transfer.

If Cond is true, save VPC+4 (return address) to the return address stack. If not true, continue execution from VPC+4.

operate

If((Cond=VCSR[SO,GT.EQ,LT])|(Cond=un)){

If(VSP<4:0>15){

VISRC<RASO>=1;

Signal ARM7 with RASO exception;

VP_STATE=VP_IDLE;

}else{

RSTACK[VSP<3:0>]＝VPC+4;

VSP<4:0>＝VSP<4:0>+1;

VPC=SRb<31:2>:b′00;

}

}else VPC=VPC+4:

abnormal

Return address stack overflow.

VCMOV conditional transfer

Format

assembler syntax

VCMOV dt Rd, Rb, cond

VCMOV.dt Rd, #IMM, cond

where dt = {b, b9, h, w, f}, cond = (un, lt, eq, le, gt, ne, ge, ov}. Note that .f and .w specify the same operation unless .f data Type does not support 9-bit immediate operands.

supported modes D:S:M V<-V V<-S V<-I S<-S S<-I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

If Cond is true, the contents of register Rb are transferred to register Rd. ID<1:0> further specifies the source and destination registers:

VR current group vector register

SR scalar register

SY Synchronization register

VAC vector accumulator register (refer to VMOV description for VAC register encoding) D:S:M ID<1:0>=00 ID<1:0>=01 ID<1:0>=10 ID<1:0>=11 V<-V VR<-VR VR<-VAC VAC<-VR V<-S VR<-SR VAC<-SR V<-I VR<-I S<-S SR<-SR S<-I SR<-1

operate

If((Cond=VCSR[SOV,GT,EQ,LT])|(Cond=un))

for(i=0; i<NumElem; i++)

Rd[i]={Rb[i]‖SRb‖Sex(IMM<8:0>)}; exception

none.

programming notes

This instruction is not affected by element masking, VCMOVM is affected by element masking.

For 8 elements, the extended floating-point precision representation in the vector accumulator uses all 576 bits. Thus, vector register transfers that include the accumulator must specify a .b9 data length.

VCMOVM conditional branch with element masking

Format

assembler syntax

VCMOVM.dt Rd, Rb, cond

VCMOVM.dt Rd, #IMM, cond

where dt = {b, b9, h, w, f}, cond = {un, lt, eq, le, gt, ne, ge, ov}. Note that .f and .w specify the same operation, except that the .f data type does not support 9-bit immediate operands.

supported modes D:S:M V<-V V<-S V<-1 DS int8(b) int9(b9) int16(h) int32(w)

illustrate

If Cond is true, the contents of register Rb are transferred to register Rd. ID<1:0> further specifies the source and destination registers:

VR current group vector register

SR scalar register

VAC vector accumulator register (refer to VMOV description for VAC register encoding) D:S:M ID<1:0>=00 ID<1:0>=01 ID<1:0>=10 ID<1:0>=11 V<-V VR<-VR VR<-VAC VAC<-VR V<-S VR<-SR VAC<-SR V<-I V<-I S<-S S<-I

operate

If((Cond=VCSR[SO,GT,EQ,LT])|(Cond=un))

for(i=0; i<NumElem &&MMASK[i]; i++)

Rd[i]={Rb[i]‖SRb‖sex(IMM<8:0>)};

abnormal

none.

programming notes

This instruction is affected by VMMR element masking, and VCMOV is not affected by element masking.

For 8 elements, the extended floating-point precision representation in the vector accumulator uses all 576 bits. Thus, vector register transfers that include the accumulator must specify a .b9 data length.

VCMPV compare and set mask

Format

assembler syntax

VCMPV.dt VRa, VRb, cond, mask

VCMPV.dt VRa, SRb, cond, mask

where dt={b, b9, h, w, f}, cond={lt, eq, le, gt, ne, ge,}, mask={VGMR, VMMR}. If no masking is specified, VGMR is assumed.

supported modes D:S:M M<-V@V M<-V@S DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

The contents of the vector registers VRa and VRb are compared element-wise by performing a subtraction operation (VRa[i]-VRb[i]). If the result of the comparison matches the Cond field of the VCMPV instruction, then VGMR (such as K=0) or The #i bit of the phase in the VMMR (eg K=1) register is set. For example, if the Cond field is less than (LT), the VGMR[i] (or VMMR[i]) bit is set when VRa[i]<VRb[i].

operate

     for(i=0: i<NumElem: i++){

Bop[i]={Rb[i]‖SRb‖sex(IMM<8:0>)};

Relationship[i]=Ra[i]? Bop[i];

If(K＝1)

MMASK[i]=(relationship[i]=Cond)? True: False;

else

EMASK[i]=(relationship[i]=Cond)? True: False;

}

abnormal

none.

programming notes

This directive is not affected by elemental masking.

VCNTLZ Count of leading zeros

Format

assembler syntax

VCNTLZ.dt VRd, VRb

VCNTLZ.dt SRd, SRb

where dt = {b, b9, h, w}.

supported modes 5 V<-V S<-S DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Counts the number of leading zeros for each element in Rb; returns the count in Rd.

operate

     for(i=0: i<NumElem &&EMASK[i]; i++){

Rd[i]=number of leading zeroes(Rb[i]);

}

abnormal

none.

programming notes

If all bits in the element are zero, the result is equal to the length of the element (8, 9, 16, or 32 for byte, byte9, halfword, or word, respectively).

The count of leading zeros has an inverse relationship to the element position index (if used after a VCMPR instruction). For conversion to element position, the result of subtracting VCNTLZ from NumElem for the given data type.

The complement of VCOR or

Format

assembler syntax

VCOR.dt VRd, VRa, VRb

VCOR.dt VRd, VRa, SRb

VCOR.dt VRd, VRa, #IMM

VCOR.dt SRd, SRa, SRb

VCOR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logically OR the complement of Ra and Rb/immediate operand, and return the result to the destination register operation

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

     Rd[i]<k>＝-Ra[i]<k>|Bop[i]<k>，k＝for all bits in elementi;

abnormal

none.

VCRSR return from subroutine condition

Format

assembler syntax

VCRSR.cond

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

Return from subroutine if Cond is true. this is not delayed transfer

If Cond is true, execution continues from the return address held on the return address stack. If not true, execution continues from VPC+4.

operate

If((Cond=VCSR[SO,GTEQ,LT])|(Cond=un)){

       if (VSP<4:0>＝0){

VISRC<RASU>=1;

Signal ARM7 with RASU exeeption:

VP_STATE=VP_IDLE;

}else{

VSP<4:0>＝VSP<4:0>-1;

VPC＝RSTACK[VSP<3:0>];

VPC<1:0>=b′00;

}

}else VPC＝VPC+4;

abnormal

Invalid instruction address, return address stack underflow.

VCVTB9 byte9 data type conversion

Format

assembler syntax

VCVTB9.md VRd, VRb

VCVTB9.md SRd, SRb

where md={bb9, b9h, hb9}.

support mode S V<-V S<-S MD bb9 b9h hb9

illustrate

Each element in Rb is converted from byte to byte9 (bb9), from byte9 to halfword (b9h) or from halfword to byte9 (hb9).

operate

If(md<1:0>＝0){//bb9 for byte to byte9 conversion

VRd=VRb;

     VRd<9i+8>＝VRb<9i+7>，i＝0 to 31(or 63 in VEC64 mode)}

    else if(md<1:0>＝2){//b9h for byte9 to halfword conversion

VRd=VRb;

     VRd<18i+16: 18i+9>＝VRb<18i+8>，i＝0 to 15(or 31 in VEC64 mode)}

    else if(md<1:0>＝3)//hb9 for halfword to byte9 conversion

     VRd<18i+8>＝VRb<18i+9>，i＝0 to 15(or 31 in VEC64 mode)

else VRd=undefined;

abnormal

none.

programming notes

Before using this instruction with b9h mode, the programmer is required to use a shuffle operation to adjust the reduced number of elements in the vector register. After using this instruction with hb9 mode, the programmer is required to use the unshuffle operation to adjust the number of elements added in the destination vector register. This directive is not affected by elemental masking.

VCVTFF floating-point to fixed-point conversion

Format

assembler syntax

VCVTFF VRd, VRa, SRb

VCVTFF VRd, VRa, #IMM

VCVTFF SRd, SRa, SRb

VCVTFF SRd, SRa, #IMM

supported modes D:S:M V<-V,S V<-V, I S<-S, S S<-S, I

illustrate

The contents of the vector/scalar register Ra are converted from 32-bit floating-point to fixed-point real numbers of the format <X, Y>, where the length of Y is specified by the Rb (modulo 32) or IMM field, and the length of X is specified by (32-the length of Y ) specified. X represents the integer part, and Y represents the fractional part. The result is stored in vector/scalar register Rd.

operate

Y_size={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem; i++){

Rd[i]＝convert to<32-Y_size.Y size>format(Ra[i]);

}

abnormal

overflow.

programming notes

This command only supports Word data length. Since structures do not support multiple data types in registers, this instruction does not use element masking. For integer data types, this instruction uses the rounding method of omitting zero.

VCVTIF Integer to floating point conversion

Format

assembler syntax

VCVTIF VRd, VRb

VCVTIF VRd, SRb

VCVTIF SRd, SRb

supported modes D:S:M V<-V V<-S S<-S

illustrate

The contents of the vector/scalar register Rb are converted from int32 to floating-point data type, and the result is stored in the vector/scalar register Rd.

operate

for(i=0; i<NumElem; i++){

Rd[i]＝convert to floating point format(Rb[i]);

}

abnormal

none.

programming notes

This command only supports word data length. Since structures do not support multiple data types in registers, this instruction does not use element masking.

VD1CBR VCR1 minus 1 and conditional transfer

Format

assembler syntax

VD1CBR.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

If Cond is true, decrement VCR1 by 1 and branch. This is not delayed transfer.

operate

VCR1 = VCR1-1;

If((VCR1>0)&((Cond=VCSR[SO, GT, EQ, LT])|(Cond=un)))

VPC＝VPC+Sex(Offset<22:0>*4);

else VPC=VPC+4;

abnormal

Invalid instruction address.

programming notes

Note that VCR1 is decremented by 1 before the transition condition is checked. Execute this instruction when VCR1 is 0, and effectively set the loop count to 2 ³² -1.

VD2CBR VCR2 minus 1 and conditional transfer

Format

assembler syntax

VD2CBR.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

If Cond is true, decrement VCR2 by 1 and branch. This is not delayed transfer.

operate

VCR2 = VCR2-1;

If((VCR2>0)&((Cond=VCSR[SO, GT, EQ, LT])|(Cond=un)))

VPC＝VPC+sex(Offset<22:0>*4);

else VPC=VPC+4;

abnormal

Invalid instruction address.

programming notes

Note that VCR2 is decremented by 1 before the transition condition is checked. Execute this instruction when VCR2 is 0, and effectively set the loop count to 2 ³² -1.

VD3CBR VCR3 minus 1 and conditional transfer

Format

assembler syntax

VD3CBR.cond #Offset

where cond = {un, lt, eq, le, gt, ne, ge, ov}.

illustrate

When Cond is true, VCR3 decrements 1 and transfers. This is not delayed transfer.

operate

VCR3=VCR3-1;

If((VCR3>0)&((Cond=VCSR[SO, GT, EQ, LT])|(Cond=un)))

VPC＝VPC+sex(Offset<22:0>*4);

else VPC=VPC+4;

abnormal

Invalid instruction address.

programming notes

Note that VCR3 is decremented by 1 before the branch condition is checked. Execute this instruction when VCR3 is 0, and effectively set the loop count to 2 ³² -1.

VDIV2N by 2 ^no remove

Format

assembler syntax

VDIV2N.dt VRd, VRa, SRb

VDIV2N.dt VRd, VRa, #IMM

VDIV2N.dt SRd, SRa, SRb

VDIV2N.dt SRd, SRa, #IMV

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The content of the vector/scalar register Ra is divided by 2 ⁿ , where n is the positive integer content of the scalar register Rb or 2MM, and the final result is stored in the vector/scalar register Rd. This instruction uses truncation (rounding towards zero) as the rounding mode.

operate

N = {SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=Ra[i]/ ^2N ;

}

abnormal

none.

programming notes

Note that N is a 5-digit number taken from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the N value in the data length that is less than or equal to the precision level. If it is greater than the precision specified for the data length, the element will be padded with a sign bit. This instruction uses a rounding mode that rounds towards zero.

VDIV2N.F floating point is 2 ^no remove

Format

assembler syntax

VDIV2N.f VRd, VRa, SRb

VDIV2N.f VRd, VRa, #IMM

VDIV2N.f SRd, SRa, SRb

VDIV2N.f SRd, SRa, #IMM

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I

illustrate

The content of the vector/scalar register Ra is divided by 2n, where n is the positive integer content of the scalar register Rb or IMM, and the final result is stored in the vector/scalar register Rd.

operate

N = {SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=Ra[i]/ ^2N ;

}

abnormal

none.

programming notes

Note that N is a 5-digit number taken from SRb or IMM<4:0>.

VDIVI incomplete deinitialization

Format

assembler syntax

VDIVI.ds VRb

VDIVI.ds SRb

where ds = {b, b9, h, w}.

supported modes S VRb SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Performs an initialization step for signed integer division without recovery. The dividend is a double-precision signed integer in the accumulator. If the dividend is single precision, it must be sign extended to double precision and stored in VACOH and VACOL. The divisor is a single-precision signed integer in Rb.

If the dividend has the same sign as the divisor, subtract Rb from the high bits of the accumulator. If different, Rb is added to the high bit of the accumulator.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb)

If(VACOH[i]<msb>＝Bop[i]<msb>)

VACOH[i]=VACOH[i]-Bop[i];

else

VACOH[i]=VACOH[i]+Bop[i]:

}

abnormal

none.

programming notes

It is the programmer's responsibility to check for overflow or division by zero before the divide step.

VDOVS incomplete removal step

Format

assembler syntax

VDIVS.ds VRb

VDIVS.ds SRb

where ds = {b, b9, h, w}.

supported modes S VRb SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Perform an alternative step for signed division without recovery. The number of times this instruction is required to be executed is the same as the length of the same data (for example, 8 times for int8, 9 times for int9, 16 times for int16, and 32 times for int32 data type). The VDIVI instruction must be used once before the divide step to produce the remainder of the initial portion in the accumulator. The divisor is a single-precision signed integer in Rb. Each step extracts a quotient bit and moves to the least significant bit of the accumulator.

If the partial remainder in the accumulator has the same sign as the divisor in Rb, subtract Rb from the upper bits of the accumulator. If different, Rb is added to the high bit of the accumulator.

The quotient is 1 if the partial remainder (the result of addition or subtraction) in the accumulator has the same sign as the divisor. If not the same, the quotient is 0. The accumulator is shifted one position to the left and filled with the quotient.

At the end of the division step, the remainder is in the high bit of the accumulator and the quotient is in the low bit of the accumulator. This quotient is in 1's complement form.

operate

VESL element shift left one

Format

assembler syntax

VESL.dt SRc, VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes S SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Shift the element in the vector register Ra to the left by one position, and fill it from the scalar register Rb. The leftmost element being shifted out is returned to scalar register Rc, the other elements are returned to vector register Rd.

operate

VRd[0] = SRb;

for(i=o; i<NumElem-1; i++)

VRd[i]=VRa[i-1];

SRc=VRa[NumElem-1];

abnormal

none.

programming notes

This directive is not affected by elemental masking.

The VESR element is shifted one bit to the right

Format

assembler syntax

VESL.dt SRc, VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes S SRb Ds int8(b) int9(b9) int16(h) int32(w)

illustrate

Shift the elements of the vector register Ra one place to the right and fill them from the scalar register Rb. The rightmost element being shifted out is returned to scalar register Rc, the other elements are returned to vector register Rd.

operate

SRc=VRa[0];

for(i=o; i<NumElem-2; i++)

VRd[i]=VRa[i+1];

VRd[NumElem-1] = SRb;

abnormal

none.

programming notes

This directive is not affected by elemental masking.

VEXTRT Extract an element

Format

assembler syntax

VEXTRT.dt SRd, VRa, SRb

VEXTRT.dt SRd, VRa, #IMM

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes D:S:M S<-S S<-I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

An element is extracted from the Ra vector register and stored into the scalar register Rd whose index is indicated by the scalar register Rb or IMM field.

operate

index32={SRb%32‖IMM<4:0>};

index64={SRb%64‖IMM<5:0>};

index=(VCSR<vec64>)? index64: index32;

SRd=VRa[index];

abnormal

none.

programming notes

This directive is not affected by elemental masking.

VEXTSGN2 extracts (1, -1) symbols

Format

assembler syntax

VEXTSGN2.dt VRd, VRa

VEXTSGN2.dt SRd, SRa

where dt = {b, b9, h, w}.

supported modes S V<-V S<-S DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Calculate the symbolic value of the element-wise content of the vector/scalar register Ra, and store the result in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=(Ra[i]<0)? -1:1;

}

abnormal

none.

VEXTSGN3 extracts (1, 0, -1) symbols

Format

assembler syntax

VEXTSGN3.dt VRd, VRa

VEXTSGN3.dt SRd, SRa

where dt = {b, b9, h, w}.

supported modes S V<-V S<-S DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Calculate the symbolic value of the element-wise content of the vector/scalar register Ra, and store the result in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

If(Ra[i]＞0) Rd[i]＝1;

       else if(Ra[i]＜0) Rd[i]＝-1;

else Rd[i]=0;

}

abnormal

none.

VINSRT Insert an element

Format

assembler syntax

VINSRT.dt VRd, SRa, SRb

VINSRT.dt VRd, SRa, #IMM

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-S V<-I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Inserts the element in scalar register Ra into vector register Rd at the index specified by the scalar register Rb or IMM field.

operate

index32={SRb%32‖IM4<4:0>};

index64={SRb%64‖IMM<5:0>};

index=(VCSR<Vec64>)? index64: index32;

VRd[index] = SRa;

abnormal

none.

programming notes

This directive is unaffected by elemental shielding.

VL loading

Format

assembler syntax

VL.lt Rd, SRb, SRi

VL.lt Rd, SRb, #IMM

VL.lt Rd, SRb+, SRi

VL.lt Rd, SRb+, #IMM

where lt={b, bz9, bs9, h, w, 4, 8, 16, 32, 64}, Rd={VRd, VRAd, SRd}. Note that .b and .bs9 specify the same operation, and .64 and VRAd cannot be specified together. Use VLOFF for cache-off loads.

operate

Load a vector register or a scalar register in the current or alternate bank.

operate

EA=SRb+{SRi‖Sex(IMM<7:0>)};

if(A=1)SRb=EA;

Rd = see the table below: LT load operation .b SR _d <7:0>:=BYTE[EA] .bz9 SR _d <8:0> = zex BYTE[EA] .bs9 SR ₄ <8:0> = sex BYTE[EA] .h _SRd <15:0>=HALF[EA] .w SR _d <31:0> = WORD[EA] .4 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 3 .8 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 7 .16 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 15 .32 VR _d <9i+8:9i>=sex BYT[EA+i], i=0 to 31 .64 VR _0d <9i+8:9i>=sex BYTE[EA+i], i=0 to 31 _{VR 1d} <9i+8:9i>=sex BYTE[EA+32+i], i=0 to 31

abnormal

Invalid data address, misaligned access.

programming notes

This directive is not affected by elemental masking.

VLCB loads from circular buffer

Format

assembler syntax

VLCB.lt Rd, SRb, SRi

VLCB.lt Rd, SRb, #IMM

VLCB.lt Rd, SRb+, SRi

VLCB.lt Rd, SRb+, #IMM

where lt={b, bz9, bs9, h, w, 4, 8, 16, 32, 64}, Rd={VRd, VRAd, SRd}. Note that .b and .bs9 specify the same operation, and .64 and VRAd cannot be specified together. Use VLCBOFF for cache-off loads.

illustrate

Loads a vector or scalar register from the circular buffer bounded by the BEGIN pointer in SR _b+1 and the END pointer in SR _b+2 .

Before the load and address update operations, if the effective address is greater than the END address, the effective address is adjusted. Additionally, for .h and .w scalar loads, circular buffer boundaries must be aligned to halfword and word boundaries, respectively.

operate

EA=SR _b +{SRi‖sex(IMM<7:0>)};

BEGIN=SR _b+1 ;

END=SR _b+2 ;

cbsize=END-BEGIN;

if(EA>END)EA=BEGIN+(EA-END);

if(A=1)SR _b =EA;

R _d = see the table below: LT load operation .bz9 SR _d <8:0> = zex BYTE[EA] .bs9 SR _d <8:0> = sex BYTE[EA] .h _SRd <15:0>=HALF[EA] .w SR _d <31:0> = WORD[EA] .4 VR _d <9i+8:9i>=sex BYTE[(EA+i>END)? EA+i-cbsize: EA+i], i=0 to 3 .8 VR _d <9i+8:9i>=sex BYTE[(EA+i>END)? EA+i-cbsize: EA+i], i=0 to 7 LT load operation .16 VR _d <9i+8:9i>=sex BYTE[(EA+i>END)? EA+i-cbsize: EA+i], i=0 to 15 .32 VR _d <9i+8:9i>=sex BYTE[(EA+i>END)? EA+i-cbsize: EA+i], i=0 to 31 .64 VR _0d <9i+8:9i>=sex BYTE[(EA+i>END)? EA+i-cbsize:EA+i], i=0 to 31VR _1d <9i+8:9i>=sex BYTE[(EA+32+i>END)? EA+32+i-cbsize: EA+32+i], i=0 to 31

abnormal

Invalid data address, misaligned access.

programming notes

This directive is not affected by elemental masking.

The programmer must determine the following conditions for this instruction to work as expected:

BEGIN＜EA＜2*END-BEGIN

That is, EA>BEGIN and EA-END<END-BEGIN.

VLD double load

Format

assembler syntax

VLD.lt Rd, SRb, SRi

VLD.lt Rd, SRb, #IMM

VLD.lt Rd, SRb+, SRi

VLD.lt Rd, SRb+, #IMM

where lt={b, bz9, bs9, h, w, 4, 8, 16, 32, 64}, Rd={VRd, VRAd, SRd}. Note that .b and .bs9 specify the same operation, and .64 and VRAd cannot be specified together. Use VLDOFF for cache-off loads.

illustrate

Load two vector registers or two scalar registers in the current or alternate bank.

operate

EA=SR _b +{SR _i ‖Sex(IMM<7:0>)};

if(A=1)SR _b =EA;

R _d : R _d+1 = see the table below: LT load operation .bz9 SR _d <8:0>=zex BYTE[EA] SR _d+1 <8:0>=zex BYTE[EA+1] .bs9 SR _d <8:0>=zex BYTE[EA] SR _d+1 <8:0>=zex BYTE[EA+1] .h SR _d <15:0>=HALF[EA]SR _d+1 <15:0>=HALF[EA+2] .w SR _d <31:0>=WORD[EA]SR _d+1 <31:0>=WORD[EA+4] .4 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 3 VR _d+1 <9i+8:9i>=sex BYTE[EA+4+i], i=0 to 3 .8 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 7 VR _d+1 <9i+8:9i>=sex BYTE[EA+8+i], i=0 to 7 LT load operation .16 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 15 VR _d+1 <9i+8:9i>=sex BYTE[EA+16+i], i=0 to 15 .32 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 31 _{VR d+1} <9i+8:9i>=sex BYTE[EA+32+i], i=0 to 31 .64 VR _0d <9i+8:9i>=sex BYTE[EA+i], i=0 to 31VR _1d <9i+8:9i>=sex BYTE[EA+32+i],i=0 to 31VR _0d+1 <9i+8:9i>=sex BYTE[EA+64+i], i=0 to 31VR _1d+1 <9i+8:9i>=sex BYTE[EA+96+i], i=0 to 31

abnormal

Invalid data address, misaligned access.

programming notes

This directive is not affected by elemental masking.

VLI load immediate

Format

assembler syntax

VLI.dt VRd, #IMM

VLI.dt SRd, #IMM

where dt = {b, b9, h, w, f}.

illustrate

Load an immediate value into a scalar or vector register.

For scalar register loads, load byte, byte9, halfword, or word depending on the data type. For byte, byte9, and halfword data types, those bytes (byte9) that are not affected are not changed.

operate

Rd = see the table below: DT scalar load vector loading .i8 _SRd <7:0> = IMM<7:0> VR _d = 32 int8 elements .i9 _SRd <8:0>=IMM<8:0> VR _d = 32 int9 elements .i16 _SRd <15:0>=IMM<15:0> VR _d = 16 int16 elements .i32 SR _d <31:0>=sex IMM<18:0> VR _d = 8 int32 elcments .f SR _d <31> = IMM <18> (sign) SR _d <30:23> = IMM <17:10> (exponent) SR _d <22:13> = IMM <9:0> (mantissa) SR _d < 12: 0>=zeroes VR _d = 8 float elements

abnormal

none.

VLQ Quad load

Format

assembler syntax

VLQ.lt Rd, SRb, SRi

VLQ.lt Rd, SRb, #IMM

VLQ.lt Rd, SRb+, SRi

VLQ.lt Rd, SRb+, #IMM

where lt={b, bz9, bs9, h, w, 4, 8, 16, 32, 64}, Rd={VRd, VRAd, SRd}. Note that .b and .bs9 specify the same operation, and .64 and VRAd cannot be specified together. Use VLQOFF for cache-off loading.

illustrate

Load four vector registers or four scalar registers in the current or alternate bank.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)];

if(A=1) SR _b = EA;

R _d : R _d+1 : R _d+2 : R _d+3 = see the table below: LT load operation .bz9 SR _d <8:0>=zex BYTE[EA]SR _d+1 <8:0>=zex BYTE[EA+1]SR _d+2 <8:0>=zex BYTE[EA+2]SR _d3 < 8: 0>= zex BYTE[EA+3] .bs9 SR _d <8:0>=zex BYTE[EA]SR _d+1 <8:0>=zex BYTE[EA+1]SR _d+2 <8:0>=zex BYTE[EA+2]SR _{d+ 3} <8:0>=zex BYTE[EA+3] .h SR _d <15:0>=HALF[EA]SR _d+1 <15:0>=HALF[EA+2]SR _d+2 <15:0>=HALF[EA+4]SR _d+3 <15 :0>=HALF{EA+6] LT load operation .w SR _d <31:0>=WORD[EA]SR _d+1 <31:0>=WORD[EA+4]SR _d+2 <31:0>=WORD[EA+8]SR _d+3 <31 : 0>=WORD[EA+12] .4 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 3VR _d+1 <9i+8:9i>=sex BYTE[EA+4+i], i=0 to 3VR _{d +2} <9i+8:9i>=sex BYTE[EA+8+i], i=0 to 3VR _d+3 <9i+8:9i>=sex BYTE[EA+12+i], i=0 to 3 .8 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 7VR _d+1 <9i+8:9i>=sex BYTE[EA+8+i], i=0 to 7VR _{d +2} <9i+8:9i>=sex BYTE[EA+16+i], i=0 to 7VR _d+3 <9i+8:9i>=sex BYTE[EA+24+i], i=0 to 7 .16 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 15VR _d+1 <9i+8:9i>=sex BYTE[EA+16+i], i=0 to 15VR _{d +2} <9i+8:9i>=sex BYTE[EA+32+i], i=0 to 15VR _d+3 <9i+8:9i>=sex BYTE[EA+48+i], i=0 to 15 .32 VR _d <9i+8:9i>=sex BYTE[EA+i], i=0 to 31VR _d+1 <9i+8:9i>=sex BYTE[EA+32+i], i=0 to 31VR _{d +2} <9i+8:9i>=sex BYTE[EA464+i], i=0 to 31VR _d+3 <9i+8:9i>=sex BYTE[EA+96+i], i=0 to 31 .64 VR _0d <9i+8:9i>=sex BYTE[EA+i], i=0 to 31VR _1d <9i+8:9i>=sex BYTE[EA+32+i],i=0 to 31VR _0d+1 <9i+8:9i>=sex BYTE[EA+64+i], i=0 to 31VR _1d+1 <9i+8:9i>=sex BYTE[EA+96+i], i=0 to 31VR _{0d +2} <9i+8:9i>=sex BYTE[EA+128+i], i=0 to 31VR _1d+2 <9i+8:9i>=sex BYTE[EA+160+i], i=0 to 31VR _0d+3 <9i+8:9i>=sex BYTE[EA+192+i], i=0 to 31VR _1d+3 <9i+8:9i>=sex BYTE[EA+224+i], i= 0 to 31

abnormal

Invalid data address, misaligned access.

programming notes

This directive is not affected by elemental masking.

VLR reverse loading

Format

assembler syntax

VLR.lt Rd, SRb, SRi

VLR.lt Rd, SRb, #IMM

VLR.lt Rd, SRb+, SRi

VLR.lt Rd, SRb+, #IMM

where lt={4, 8, 16, 32, 64}, Rd={VRd, VRAd}. Note that .64 and VRAd cannot be specified together. Use VLROFF for Cache-off loading.

illustrate

Load a vector register in reverse order of elements. This instruction does not support scalar destination registers.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)];

if(A=1)SR _b =EA;

Rd = see the table below: LT load operation .4 VR _d [31-i]<8:0>=sex BYTE[EA+i], i=0 to 3 .8 VR _d [31-i]<8:0>=sex BYTE[EA+i], i=0 to 7 .16 VE _d [31-i]<8:0>=sex BYTE[EA+i], i=0 to 15 .32 VR _d [31-i]<8:0>=sex BYTE[EA+i], i=0 to 31 .64 VR _0d [31-i]<8:0>=sex BYTE[EA+32+i], i=0 to 31VR _1d [31-i]<8:0>=sex BYTE[EA+i], i= 0 to 31

abnormal

Invalid data address address, unaligned access.

programming notes

This directive is not affected by elemental masking.

VLSL logical shift left

Format

assembler syntax

VLSL.dt VRd, VRa, SRb

VLSL.dt VRd, VRa, #IMM

VLSL.dt SRd, SRa, SRb

VLSL.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each element of the vector/scalar register Ra is logically shifted to the left, the least significant bit (LSB) position is filled with zeros, the shift amount is given in the scalar register Rb or IMM field, and the result is stored in the vector/scalar register Rd .

operate

 shift_amount={SRb%32‖IMM<4:0>};

`` for(i=0; i<NumElem && EMASK[i]:i++){

Rd[i]=Ra[i]<<shift_amount;

}

abnormal

none.

programming notes

Note that shift-amount is a 5-digit number obtained from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the shift amount of the number of bits less than or equal to the data length. If the shift amount is greater than the specified data length, the element will be filled with zeros.

VLSR logical shift right

Format

assembler syntax

VLSR.dt VRd, VRa, SRb

VLSR.dt VRd, VRa, #IMM

VLSR.dt SRd, SRa, SRb

VLSR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each element of the vector/scalar register Ra is logically shifted to the right, the most significant bit (MSB) position is filled with zeros, the shift amount is given in the scalar register Rb or IMM field, and the result is stored in the vector/scalar register Rd .

operate

shift_amount={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=Ra[i]zero＞＞shift_amount;

}

abnormal

none.

programming notes

Note that shift-amount is a 5-digit number obtained from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the shift amount of the number of bits less than or equal to the data length. If the shift amount is greater than the specified data length, the element will be filled with zeros.

VLWS span loading

Format

assembler syntax

VLWS.dt Rd, SRb, SRi

VLWS.dt Rd, SRb, #IMM

VLWS.dt Rd, SRb+, SRi

VLWS.dt Rd, SRb+, #IMM

where dt={4, 8, 16, 32}, Rd={VRd, VRAd}. Note that .64 mode is not supported, use VL instead. Use VLWSOFF for cache-off loads.

illustrate

Starting at an effective address, load 32 bytes from memory into vector register VRd using scalar register SRb+1 as the stride control register.

LT specifies the block size, the number of consecutive bytes loaded for each block. SRb+1 specifies the stride, the number of bytes separating the beginning of two consecutive blocks.

stride must be equal to or greater than block size. EA must be the aligned data length. stride and block size must be multiple data lengths.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

Block-size={4‖8‖16‖32};

Stride = SR _b+1 <31:0>;

for(i=0; i<VECSIZE/Block-size; i++)

for(j=0; j<Block-size; j++)

VRd[i*Block-size+j]<8:0>＝sex BYTE{EA+i*Stride

+j};

abnormal

Invalid data address, unaligned access.

VMAC multiply and accumulate

Format

assembler syntax

VMAC.dt VRa, VRb

VMAC.dt VRa, SRb

VMAC.dt VRa, #IMM

VMAC.dt SRa, SRb

VMAC.dt SRa, #IMM

where dt = {b, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Each element of Ra is multiplied by each element in Rb to produce a double-precision intermediate result; each double-precision element of this intermediate result is added to each double-precision element of the vector accumulator, and each element's The double precision sum is stored in the vector accumulator.

Ra and Rb use the specified data types, while VAC uses the appropriate double data type (16, 32, and 64 bits correspond to int8, int16, and int32, respectively). The high-order part of each double-precision element is stored in VACH.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++)(

Aop[i]={VRa[i]‖SRa};

Bop[i]={VRb[i]‖SRb);

If(dt=float)VACL[i]=Aop[i]*Bop[i]+VACL[i];

Else VACH[i]:VACL[i]=Aop[i]*Bop[i]+VACH[i]:VACL[i];

}

abnormal

Overflow, invalid operand for floating point.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMACF multiply and accumulate decimals

Format

assembler syntax

VMACF.dt VRa, VRb

VMACF.dt VRa, SRb

VMACF.dt VRd, #IMM

VMACF.dt SRa, SRb

VMACF.dt SRa, #IMM

where dt = {b, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of VRa with each element in Rb to produce a double-precision intermediate result; shift this double-precision intermediate result to the left by one bit; combine each double-precision element of the shifted intermediate result with the vector accumulator Each double element of is added; the double sum of each element is placed in the vector accumulator.

VRa and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits correspond to int8, int16, and int32, respectively). The high-order part of each double-precision element is stored in VACH.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

VACH[i]:VACL[i]=((VRa[i]*Bop[i])<<1)+VACH[i]:VACL[i];

}

abnormal

overflow.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMACL multiply and accumulate low bit

Format

assembler syntax

VMACL.dt VRd, VRa, VRb

VMACL.dt VRd, VRa, SRb

VMACL.dt VRd, VRa, #IMM

VMACL.dt SRd, SRa, SRb

VMACL.dt SRd, SRa, #IMM

where dt = {b, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Multiply each element of VRa with each element in Rb to produce a double-precision intermediate result; add each double-precision element of this intermediate result to each double-precision element of the vector accumulator; add each element The double-precision sum is stored in the vector accumulator; the lower part is returned to the destination register VRd.

VRa and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits correspond to int8, int16, and int32, respectively). The bit portion of each double element is stored in VACH.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb};

If(dt=float)VACL[i]=VRa[i]*Bop[i]+VACL[i];

Else VACH[i]:VACL[i]=VRa[i]*Bop[i]+VACH[i]:VACL[i];

VRd[i]=VACL[i];

}

abnormal

Overflow, invalid operand for floating point.

programming notes

This instruction does not support int9 data type. Use the int16 data type instead.

VMAD multiply and add

Format

assembler syntax

VMAD.dt VRc, VRd, VRa, VRb

VMAD.dt SRc, SRd, SRa, SRb

where dt = (b, h, w).

supported modes S VR SR DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of Ra with each element of Rb to produce a double-precision intermediate result; add each double-precision element of this intermediate result to each element of Rc; multiply the double-precision sum of each element Stored in the destination register Rd+1: Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Aop[i]={VRa[i]‖SRa];

Bop[i]=(VRb[i]‖SRb};

Cop[i]=(VRc[i]‖SRc};

Rd+1[i]: Rd[i]=Aop[i]*Bop[i]+sex_dp(Cop[i]);

}

abnormal

none.

VMADL multiply and add low

Format

assembler syntax

VMADL.df VRc, VRd, VRa, VRb

VMADL.dt SRc, SRd, SRa, SRb

where dt = {b, h, w, f}.

supported modes S VR SR DS int8(b) float(f) int16(h) int32(w)

illustrate

Multiply each element of Ra with each element in Rb to produce a double-precision intermediate result; add each double-precision element of this intermediate result to each element of Rc; add the double-precision sum of each element The low part of is returned to the destination register Rd.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++)(

Aop[i]={VRa[i]‖SRa};

Bop[i]={VRb[i]‖SRb];

Cop[i]={VRc[i]‖SRc{;

If(dt=Roat)Lo[i]=Aop[i]*Bop[i]+Cop[i];

Else Hi[i]: Lo[i]=Aop[i]*Bop[i]+sex_dp(Cop[i]);

Rd[i]=Lo[i];

}

abnormal

Overflow, invalid operand for floating point.

VMAS Multiply and Subtract from Accumulator

Format

assembler syntax

VMAS.dt VRa, VRb

VMAS.dt VRa, SRb

VMAS.dt VRa, #IMM

VMAS.dt SRa, SRb

VMAS.dt SRa, #IMM

where dt = {b, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Multiply each element of Ra with each element in Rb to produce a double-precision intermediate result; subtract each double-precision element of the intermediate result from each double-precision element in the vector accumulator; multiply the double-precision elements of each element precision and store to the vector accumulator.

Ra and Rb use the specified data types, while VAC uses the appropriate double data type (16, 32, and 64 bits correspond to int8, int16, and int32, respectively). The high-order part of each double-precision element is stored in VACH.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb};

If(dt=float)VACL[i]=VACL[i]-VRa[i]*Bop[i];

  else VACH[i]: VACL[i] = VACH[i]: VACL[i]-VRa[i]*Bop[i];

}

abnormal

Overflow, invalid operand for floating point.

programming notes

This instruction does not support int9 data type, use int16 data type instead.

VMASF Multiply and subtract decimals from accumulator

Format

assembler syntax

VMASF.dt VRa, VRb

VMASF.dt VRa, SRb

VMASF.dt VRa, #IMM

VMASF.dt SRa, SRb

VMASF.dt SRa, #IMM

where dt = {b, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of VRa with each element in Rb to produce a double-precision intermediate result; left-shift the double-precision intermediate result by one bit; subtract the shifted value from each double-precision element of the vector accumulator Each double element of the intermediate result; stores the double sum of each element to the vector accumulator.

VRa and Rb use the specified data type, while VAC uses the appropriate double precision data type (16, 32, and 64 bits for int8, int16, and int32 respectively). The high-order part of each double-precision element is stored in VACH.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)];

VACH[i]:VACL[i]=VACH[i]:VACL[i]-VRa[i]*Bop[i];

}

abnormal

overflow.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMASL Multiply and subtract from the low bits of the accumulator

Format

assembler syntax

VMASL.dt VRd, VRa, VRb

VMASL.dt VRd, VRa, SRb

VMASL.dt VRd, VRa, #IMM

VMASL.dt SRd, SRa, SRb

VMASL.dt SRd, SRa, #IMM

where dt = {b, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Multiply each element of VRa with each element in Rb to produce a double-precision intermediate result; subtract each double-precision element of the intermediate result from each double-precision element of the vector accumulator; multiply the double-precision element of each element The precision sum is stored in the vector accumulator; the lower part is stored in the destination register VRd.

RVa and Rb use the specified data type, while VAC uses the appropriate double data type (16, 32, and 64 correspond to int8, int16, and int32, respectively). The high-order part of each double-precision element is stored in VACH.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb};

If(dt=float)VACL[i]=VACL[i]-VRA[i]*Bop[i];

Else VACH[i]: VACL[i]=VACH[i]: VACL[i]-VRa[i]*Bop[i]:

VRd[i]=VACL[i];

}

abnormal

Overflow, invalid operand for floating point.

programming notes

This instruction does not support int9 data type. Use the int16 data type instead.

VMAXE Pairwise maximum-sum exchange

Format

assembler syntax

VMAXE.dt VRd, VRb

where dt = {b, b9, h, w, f}.

supported modes D:S:M V<-V DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

VRa should be equal to VRb. When VRa differs from VRb, the result is undefined.

Each even/odd data element of vector register Rb is compared in pairs and the larger value of each data element pair is stored into the even location and the smaller value of each data element pair is stored into the odd location of vector register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i=i+2)(

VRd[i]=(VRb[i]>VRb[i+1])? VRb[i]: VRb[i+1];

VRd[i+1]=(VRb[i]>VRb[i+1])? VRb[i+1]:VRb[i]:

}

abnormal

none.

VMOV transfer

Format

assembler syntax

VMOV.dt Rd, Rb

where dt = {b, b9, h, w, f}. Rd and Rb indicate structurally specified register names.

Note that .w and .f indicate the same operation.

supported modes

illustrate

The content of register Rb is transferred to register Rd. The Group field specifies the source and destination register groups. The marking method of the register group is:

VR current group vector register

VRA Alternative Group Vector Register

SR scalar register

SP special register

RASR return address stack register

MAC vector accumulation register (see VAC register encoding table below) group<3:0> source group target group note 0000 reserve 0001 VR VRA 0010 VRA VR 0011 VRA VRA 0100 reserve 0101 reserve 0110 VRA VAC 0111 VAC VRA 1000 reserve 1001 SR VRA 1010 reserve 1011 reserve 1100 SR SP 1101 SP SR 1110 SR RASR 1111 RASR SR

Note that vector registers cannot be transferred to scalar registers with this instruction. The VEXTRT instruction is provided for this purpose.

Use the following table for VAC register coding: R<2:0> register note 000 undefined 001 VAC0L 010 VAC0H 011 VAC0 Specify both VAC0H:VAC0L. If specified as source, the VRd+1:VRd register pair is updated. VRd must be an even register. 100 undefined 101 VAC1L 110 VAC1H 111 VAC1 Specify both VAC1H:VAC1L. If specified as source, the VRd+1:VRd register pair is updated. VRd must be an even register. other undefined

operate

Rd=Rb

abnormal

Setting an exception event status bit in VCSR or VISRC will cause the corresponding exception event.

programming notes

This directive is not affected by elemental masking. Note that the concept of substitution group does not exist in VEC64 mode. In VEC64 mode, this instruction cannot be used to transfer from or to the register of the substitution group.

VMUL multiply

Format

assembler syntax

VMUL.dt VRc, VRd, VRa, VRb

VMUL.dt SRc, SRd, SRa, SRb

where dt = {b, h, w}.

supported modes S VR SR DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of Ra with each element in Rb to produce a double-precision result; return the double-precision sum of each element to the destination register Rc:Rd.

Ra and Rb use the specified data type, while Rc:Rd uses the appropriate double precision data type (16, 32, and 64 bits correspond to int8, int16, and int32, respectively). The high-order part of each double-precision element is stored in Rc.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Aop[i]={VRa[i]‖SRa};

Bop[i]={VRb[i]‖SRb};

Hi[i]: Lo[i]=Aop[i]*Bop[i]:

Rc[i]=Hi[i];

Rd[i]=Lo[i];

}

abnormal

none.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead. This instruction also does not support floating-point data types, because the result of the expansion is an unsupported data type.

VMULA multiply to accumulator

Format

assembler syntax

VMULA.dt VRa, VRb

VMULA.dt VRa, SRb

VMULA.dt VRa, #IMM

VMULA.dt SRa, SRb

VMULA.dt SRa, #IMM

where dt = {b, h, w, f}.

supported modes D:S:M V@V V@S V@I S@S S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Multiply each element of VRa by each element of Rb to produce a double-precision result; write this result to the accumulator.

Floating point data type, all operands and results are single precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb};

If(dt==float)VACL[i]=VRa[i]*Bop[i];

Else VACH[i]: VACL[i]=VRa[i]*Bop[i];

}

abnormal

none.

programming notes

This instruction does not support int9 data type. Use the int16 data type instead.

VMULAF Multiply to accumulator decimal

Format

assembler syntax

VMULAF.dt VRa, VRb

VMULAF.dt VRa, SRb

VMULAF.dt VRa, #IMM

VMULAF.dt SRa, SRb

VMULAF.dt SRa, #IMM

where dt = {b, h, w}.

supported modes D:S:M V@V V@S V@I S@S S@I DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of VRa by each element of Rb to produce a double-precision intermediate result; this double-precision intermediate result is shifted left one bit; the result is written to the accumulator.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

VACH[i]: VACL[i]=(VRa[i]*Bop[i])<<1;

}

abnormal

none.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMULF multiply decimals

Format

assembler syntax

VMULF.dt VRd, VRa, VRb

VMULF.dt VRd, VRa, SRb

VMULF.dt VRd, VRa, #IMM

VMULF.dt SRd, SRa, SRb

VMULF.dt SRd, SRa, #IMM

where dt = {b, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of VRa with each element in Rb to produce a double-precision intermediate result; this double-precision intermediate result is shifted left by one bit; the high-order part of the result is returned to the destination register VRd+1, and the low-order part is returned to Destination register VRd. VRd must be an even register.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Hi[i]: Lo[i]=(VRa[i]*Bop[i])<<1;

VRd+1[i]=Hi[i];

VRd[i]=Lo[i];

}

abnormal

none.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMULFR multiply decimals and round

Format

assembler syntax

VMULFR.dt VRd, VRa, VRb

VMULFR.dt VRd, VRa, SRb

VMULFR.dt VRd, VRa, #IMM

VMULFR.dt SRd, SRa, SRb

VMULFR.dt SRd, SRa, #IMM

where dt = {b, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w)

illustrate

Multiply each element of VRa by each element of Rb to produce a double-precision intermediate result; shift the double-precision intermediate result to the left by one bit; round the shifted intermediate result to the high-order part; return the high-order part to Destination register VRd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=(VRb[i]‖SRb‖sex(IIMM<8:0>)};

Hi[i]: Lo[i]=(VRa[i]*Bop[i])<<1;

If(Lo[i]<msb>==1) Hi[i]=Hi[i]+1;

VRd[i]=Hi[i];

}

abnormal

none.

programming notes

This instruction does not support the int9 data type, use the int16 data type instead.

VMULL Multiply the low bit

Format

assembler syntax

VMULL.dt VRd, VRa, VRb

VMULL.dt VRd, VRa, SRb

VMULL.dt VRd, VRa, #IMM

VMULL.dt SRd, SRa, SRb

VMULL.dt SRd, SRa, #IMM

where dt = (b, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int16(h) int32(w) float(f)

illustrate

Each element of VRa is multiplied by each element of Rb to produce a double-precision result; the low-order part of the result is returned to the destination register VRd.

For floating-point data types, all operands and results are single-precision.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb};

if(dt=Roat)Lo[i]=VRa[i]*Bop[i];

Else Hi[i]: Lo[i]=VRa[i]*Bop[i];

VRd[i]=Lo[i];

}

abnormal

Overflow, invalid operand for floating point.

programming notes

This instruction does not support int9 data type. Use the int16 data type instead.

VNAND NAND

Format

assembler syntax

VNAND.dt VRd, VRa, VRb

VNAND.dt VRd, VRa, SRb

VNAND.dt VRd, VRa, #IMM

VNAND.dt SRd, SRa, SRb

VNAND.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logical NAND is performed on each bit of each element in Ra with the corresponding bit in Rb/immediate operand, and the result is returned in Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]=[VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝-(Ra[i]<k> & Bop[i]<k>).for k＝all bits in elementi;

}

abnormal

none.

VNOR or not

Format

assembler syntax

VNOR.dt VRd, VRa, VRb

VNOR.dt VRd, VRa, SRb

VNOR.dt VRd, VRa, #IMM

VNOR.dt SRd, SRa, SRb

VNOR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) ini9(b9) int16(h) int32(w)

illustrate

Logically NORs each bit of each element in Ra with the corresponding bit in Rb/immediate operand; the result is returned in Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝-(Ra[i]<k>|Bop[i]<k>).for k＝all bits in elementi;

}

abnormal

none.

VOR or

Format

assembler syntax

VOR.dt VRd, VRa, VRb

VOR.dt VRd, VRa, SRb

VOR.dt VRd, VRa, #IMM

VOR.dt SRd, SRa, SRb

VOR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Logically ORs each bit of each element in Ra with the corresponding bit in Rb/immediate operand; result is returned in Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>=Ra[i]<k>|Bop[i]<k>, for k=all bits in elementi;

}

abnormal

none.

VORC or two's complement

Format

assembler syntax

VORC.dt VRd, VRa, VRb

VORC.dt VRd, VRa, SRb

VORC.dt VRd, VRa, #IMM

VORC.dt SRd, SRa, SRb

VORC.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that .w and .f specify the same operation.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Perform logical OR of each bit of each element in Ra with the complement of the corresponding bit in Rb/immediate operand; result is returned in Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)}

Rd[i]<k>＝Ra[i]<k>|-Bop[i]<k>, for k＝all bits in elementi;

}

abnormal

none.

VPFTCH prefetch

Format

assembler syntax

VPFTCH.ln SRb, SRi

VPFTCH.ln SRb, #IMM

VPFTCH.ln SRb+, SRi

VPFTCH.ln SRb+, #IMM

where ln={1, 2, 4, 8}.

illustrate

Prefetch multiple vector data cache lines starting from an effective address. The number of cache lines is specified as follows:

LN<1:0>=00: prefetch a 64-byte Cache line

LN<1:0>=01: prefetch two 64-byte Cache lines

LN<1:0>=10: prefetch 4 cache lines of 64 bytes

LN<1:0>=11: prefetch 8 cache lines of 64 bytes

If the effective address does not fall on a 64-byte boundary, it is first truncated to align to a 64-byte boundary.

operate

abnormal

Invalid data address exception event.

programming notes

EA<31:0> indicates a byte address in local memory.

VPFTCHSP prefetches to scratch memory

Format

assembler syntax

VPFTCHSP.ln SRp, SRb, SRi

VPFTCHSP.ln SRp, SRb, #IMM

VPFTCHSP.ln SRp, SRb+, SRi

VPFTCHSP.ln SRP, SRb+, #IMM

where ln={1, 2, 4, 8}. Note that VPFTCH and VPFTCHSP have the same opcode.

illustrate

Multiple 64-byte blocks are transferred from memory to temporary storage. The effective address gives the starting address of the memory, while SRp gives the starting address of the scratch memory. The number of 64-byte blocks is specified as follows:

LN<1:0>=00: transfer a block of 64 bytes

LN<1:0>=01: transfer 2 blocks of 64 bytes

LN<1:0>=10: transfer 4 blocks of 64 bytes

LN<1:0>=11: transfer 8 blocks of 64 bytes

If the effective address does not fall on a 64-byte boundary, it is first truncated to align to a 64-byte boundary. It also truncates to align to a 64-byte boundary if the scratch memory pointer address in SRp does not fall on a 64-byte boundary. Aligned scratch memory pointer address incremented by the number of bytes transferred.

operate

EA=SRb+{SRi‖sex(IMM<7:0>)};

if(A=1)SRb=EA;

Num_bytes={64‖128‖256‖512};

Mem_adrs = EA<31:6>:6b'000000;

SRp = SRp<31:6>:6b'000000;

for(i=0; i<Num_bytes; i++)

SPAD[SRp++]=MEM[Mem_adrs+i];

abnormal

Invalid data address exception event.

VROL Cycle left

Format

assembler syntax

VROL.dt VRd, VRa, SRb

VROL.dt VRd, VRa, #IMM

VROL.dt SRd, SRa, SRb

VROL.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each data element of the vector/scalar register Ra is cyclically shifted to the left, the number of bits shifted to the left is given in the field of the scalar register Rb or IMM, and the result is stored in the vector/scalar register Rd.

operate

rotate_amount={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=Ra[i]rotate_left rotate_amount;

}

abnormal

none.

programming notes

Note the 5 digits of rotate-amount taken from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the total amount of cyclic shifts that is less than or equal to the number of bits of the data length. If the total amount of shifting is greater than the specified data length, the results are undefined.

Note that a circular left shift of n bits is equivalent to a circular right shift of ElemSize-n bits, where ElemSize represents the number of bits of a given data length.

VROR Circular shift right

Format

assembler syntax

VROR.dt VRd, SRa, SRb

VROR.dt VRd, SRa, #IMM

VROR.dt SRd, SRa, SRb

VROR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

Each data element of the vector/scalar register Ra is cyclically shifted to the right, and the number of bits shifted to the right is given in the field of the scalar register Rb or IMM, and the result is stored in the vector/scalar register Rd.

operate

rotate_amount={SRb%32‖IMM<4:0>};

for(i=0; i<NumElem &&EMASK[i]; i++){

Rd[i]=Ra[i]rotate_right rotate_amount;

}

abnormal

none.

programming notes

Note that rotate-amount is a 5-digit number obtained from SRb or IMM<4:0>. For byte, byte9, and halfword data types, the programmer is responsible for correctly specifying the total amount of cyclic shifts that is less than or equal to the number of bits of the data length. If the shift amount is greater than the specified data length, the results are undefined.

Note that a cyclic right shift of n bits is equivalent to a cyclic left shift of ElemSize-n bits, where ElemSize represents the number of bits of a given data length.

VROUND rounds floating-point numbers to integers

Format

assembler syntax

VROUND.rm VRd, VRb

VROUND.rm SRd, SRb

where m = {ninf, zero, near, pinf}.

supported modes D:S:M V<-V S<-S

illustrate

The content of the floating-point data format of the vector/scalar register Rb is rounded to the nearest 32-bit integer (Word), and the result is stored in the vector/scalar register Rd. The rounding mode is specified in RM. RM<1:0> model significance 00 ninf round towards -∞ 01 zero round towards zero 10 near round to nearest even 11 pinf round towards +∞

operate

for(i=0; i<NumElem; i++){

Rd[i]=Convert to int32(Rb[i]);

}

abnormal

none.

programming notes

This directive is not affected by elemental masking.

VSATL saturate to low limit

Format

assembler syntax

VSATL.dt VRd, VRa, VRb

VSATL.dt VRd, VRa, SRb

VSATL.dt VRd, VRa, #IMM

VSATL.dt SRd, SRa, SRb

VSATL.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}. Note that 9-bit immediates do not support the .f data type.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

Each data element of the vector/scalar register Ra is checked against its corresponding lower bound in the vector/scalar register Rb or IMM field. If the data element's value is less than this lower bound, it is set equal to the lower bound and the final result is stored in vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]=(Ra[i]<Bop[i]? Bop[i]:Ra[i];

}

abnormal

none.

VSATU Saturation to high limit

Format

assembler syntax

VSATU.dt VRd, SRa, SRb

VSATU.dt VRd, SRa, SRb

VSATU.dt VRd, SRa, #IMM

VSATU.dt SRd, SRa, SRb

VSATU.dt SRd, SRa, #IMM

where dt = {b, b9, h, w, f}. Note that 9-bit immediates do not support the .f data type.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

Each data element of the vector/scalar register Ra is checked against its corresponding high limit in the vector/scalar register Rb or IMM field. If the value of the data element is greater than this high limit, it is set equal to the high limit and the final result is stored in vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)];

Rd[i]=(Ra[i]>Bop[i])? Bop[i]: Ra[i];

}

abnormal

none.

VSHFL Shuffle

Format

assembler syntax

VSHFL.dt VRc, VRd, VRa, VRb

VSHFL.dt VRc, VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes S VRb SRb DS int8(b) int9(b9) int18(h) int32(w)

illustrate

The content of the vector register Ra is shuffled with Rb, and the result is stored in the vector register Rc:Rd, as shown in the following figure:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VSHFLH Shuffle High

Format

assembler syntax

VSHFLH.dt VRd, VRa, VRb

VSHFLH.dt VRd, VRa, SRb

where dt = {b, b9, h, w, f]. Note that .w and .f specify the same operation.

supported modes S VRb SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The content of the vector register Ra is shuffled with Rb, and the high-order part of the result is stored in the vector register Rd, as shown in the following figure:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VSHFLL Shuffle Low

Format

assembler syntax

VSHFLL.dt VRd, VRa, VRb

VSHFLL.dt VRd, VRa, SRb

where dt = {b, b9, h, W, f}. Note that .w and .f specify the same operation.

supported modes S VRb SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The content of the vector register Ra is shuffled with Rb, and the lower part of the result is stored in the vector register Rd, as shown in the following figure:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VST storage

Format

assembler syntax

VST.st Rs, SRb, SRi

VST.st Rs, SRb, #IMM

VST.st Rs, SRb+, SRi

VST.st Rs, SRb+, #IMM

Where st = {b, b9t, h, w, 4, 8, 16, 32, 64}, Rs = {VRs, VRAs, SRs}.

Note that .b and .b9t indicate the same operation, and .64 and VRAs cannot be specified together. Use VSTOFF for Cache-off storage.

illustrate

Store a vector or scalar register.

operate

EA=SR _b +[SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

MEM[EA]=see the table below: ST storage operation .b BYTE[EA]=SR _s <7:0> .h HALF[EA]= _SRs <15:0> .w WORD[EA]= _SRs <31:0> .4 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 3 .8 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 7 .16 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 15 .32 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 31 .64 BYTE[EA+i]=VR _0s <9i+7:9i>, i=0 to 31 BYTE[EA+32+i]=VR _1s <9i+7:9i>, i=0 to 31

abnormal

Invalid data address, misaligned access.

programming notes

This directive is not affected by elemental masking.

VSTCB store to circular buffer

Format

assembler syntax

VSTCB.st Rs, SRb, SRi

VSTCB.st Rs, SRb, #IMM

VSTCB.st Rs, SRb+, SRi

VSTCB.st Rs, SRb+, #IMM

Where st = {b, b9t, h, w, 4, 8, 16, 32, 64}, Rs = {VRs, VRAs, SRs}.

Note that .b and .b9t indicate the same operation, and .64 and VRAs cannot be specified together. Use VSTCBOFF for Cache-off.

illustrate

From circular buffer storage to vector or scalar registers, the boundaries of the circular buffer are determined by the BEGIN pointer in SR _b+1 and the END pointer in SR _b+2 .

Before store and address update operations, if the effective address is greater than the END address, it will be adjusted. In addition, the boundaries of the circular buffer for .h and .w scalar loads must be aligned with the boundaries of halfword and Word, respectively.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

BEGIN=SR _b+1 ;

END=SR _b+2 ;

cbsize=END-BEGIN;

if(EA>END)EA=BEGIN+(EA-END);

if(A=1)SR _b =EA;

MEM[EA]=see the table below: ST storage operation .b BYTE[EA] = SR _s <7:0>; .h HALF[EA]= _SRs <15:0>; .w WORD[EA]=SR _s <31:0>; .4 BYTE[(EA+i>END)? EA+i-cbsize:EA+i]=VR _s <9i+7:9i>, i=0 to 3 .8 BYTE[(EA+i>END)? EA+i-cbsize:EA+i]=VR _s <9i+7:9i>, i=0 to 7 .16 BYTE[(EA+i>END)? EA+i-cbsize:EA+i]=VR _s <9i+7:9i>, i=0 to 15 .32 BYTE[(EA+i>END)? EA+i-cbsize:EA+i]=VR _s <9i+7:9i>, i=0 to 31 .64 BYTE[(EA+i>END)? EA+i-cbsize:EA+i]=VR _0s <9i+7:9i>, i=0 to 31BYTE[(EA+32+i>END)? EA+32+i-cbsize:EA+32+i]=VR _1s <9i+7:9i>.i=0 to 31

abnormal

Invalid data address, unaligned access.

programming notes

This directive is not affected by elemental masking.

The programmer must determine the following conditions for this instruction to work as desired:

BEGIN＜EA＜2*END-BEGIN

That is, EA>BEGIN and EA-END<END-BEGIN

VSTD dual storage

Format

assembler syntax

VSTD.st Rs, SRb, SRi

VSTD.st Rs, SRb, #IMM

VSTD.st Rs, SRb+, SRi

VSTD.st Rs, SRb+, #IMM

Where st = {b, b9t, h, w, 4, 8, 16, 32, 64}, Rs = {VRs, VRAs, SRs}. Note that .b and .b9t specify the same operation, and .64 and VRAs cannot be specified together. Use VSTDOFF for Cache-off storage.

illustrate

Store two vector registers or two scalar registers from the current or alternate bank.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

MEM[EA]=see the table below: ST storage operation .b BYTE[EA]=SR _s <7:0> BYTE[EA+1]=SR _s+1 <7:0> .h HALF[EA]= _SRs <15:0>HALF[EA+2]=SRs ₊₁ <15:0> .w WORD[EA]=SR _s <31:0>WORD[EA+4]=SR _s+1 <31:0> .4 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 3 BYTE[EA+4+i]=VR _s+1 <9i+7:9i>, i=0 to 3 .8 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 7 BYTE[EA+8+i]=VR _s+1 <9i+7:9i>, i=0 to 7 .16 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 15 BYTE[EA+16+i]=VR _s+1 <9i+7:9i>, i=0 to 15 ST storage operation .32 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 31 BYTE[EA+32+i]=VR _s+1 <9i+7:9i>, i=0 to 31 .64 BYTE[EA+i]=VR _0s <9i+7:9i>, i=0 to 31BYTE[EA+32+i]=VR _1s <9i+7:9i>, i=0 to 31BYTE[EA+64+ i]=VR _0s+1 <9i+7:9i>, i=0 to 31BYTE[EA+96+i]=VR _1s+1 <9i+7:9i>, i=0 to 31

abnormal

Invalid data address, unaligned access.

programming notes

This directive is unaffected by elemental shielding.

VSTQ Quad storage

Format

assembler syntax

VSTQ.st Rs, SRb, SRi

VSTQ.st Rs, SRb, #IMM

VSTQ.st Rs, SRb+, SRi

VSTQ.st Rs, SRb+, #IMM

Where st = {b, b9t, h, w, 4, 8, 16, 32, 64}, Rs = {VRs, VRAs, SRs}.

Note that .b and .b9t specify the same operation, and .64 and VRAs cannot be specified together. Use VSTQOFF for Cache-off storage.

illustrate

Store four vector registers or four scalar registers from the current or alternate bank.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

MEM[EA]=see the table below: ST storage operation .b BYTE[EA]=SR _s <7:0> BYTE[EA+1]=SR _s+1 <7:0> BYTE[EA+2]=SR _s+2 <7:0> BYTE[EA+3] =SRs ₊₃ <7:0> .h HALF[EA]=SR _s <15:0>HALF[EA+2]=SR _s+1 <15:0>HALF[EA+4]=SR _s+2 <15:0>HALF[EA+6] =SRs ₊₃ <15:0> .w WORD[EA]=SR _s <31:0>WORD[EA+4]=SR _s+1 <31:0>WORD[EA+8]=SR _s+2 <31:0>WORD[EA+12] =SRs ₊₃ <31:0> ST storage operation .4 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 3BYTE[EA+4+i]=VR _s+1 <9i+7:9i>, i=0 to 3BYTE[EA+ 8+i]=VR _s+2 <9i+7:9i>, i=0 to 3BYTE[EA+12+i]=VR _s+3 <9i+7:9i>, i=0 to 3 .8 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 7BYTE[EA+8+i]=VR _s+1 <9i+7:9i>, i=0 to 7BYTE[EA+ 16+i]=VR _s+2 <9i+7:9i>, i=0 to 7BYTE[EA+24+i]=VR _s+3 <9i+7:9i>, i=0 to 7 .16 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 15BYTE[EA+16+i]=VR _s+1 <9i+7:9i>, i=0 to 15BYTE[EA+ 32+i]=VR _s+2 <9i+7:9i>, i=0 to 15BYTE[EA+48+i]=VR _s+3 <9i+7:9i>, i=0 to 15 .32 BYTE[EA+i]=VR _s <9i+7:9i>, i=0 to 31BYTE[EA+32+i]=VR _s+1 <9i+7:9i>, i=0 to 31BYTE[EA+ 64+i]=VR _s+2 <9i+7:9i>, i=0 to 31BYTE[EA+96+i]=VR _s+3 <9i+7:9i>, i=0 to 31 .64 BYTE[EA+i]=VR _0s <9i+7:9i>, i=0 to 31BYTE[EA+32+i]=VR _1s <9i+7:9i>, i=0 to 31BYTE[EA+64+ i]=VR _0s+1 <9i+7:9i>, i=0 to 31BYTE[EA+96+i]=VR _1s+1 <9i+7:9i>, i=0 to 31BYTE[EA+128+ i]=VR _0s+2 <9i+7:9i>, i=0 to 31BYTE[EA+160+i]=VR _1s+2 <9i+7:9i>, i=0 to 31BYTE[EA+192+ i]=VR _0s+3 <9i+7:9i>, i=0 to 31BYTE[EA+224+i]=VR _1s+3 <9i+7:9i>, i=0 to 31

abnormal

Invalid data address, unaligned access.

programming notes

This directive is not affected by elemental masking.

VSTR reverse storage

Format

assembler syntax

VSTR.st Rs, SRb, SRi

VSTR.st Rs, SRb, #IMM

VSTR st Rs, SRb+, SRi

VSTR.st Rs, SRb+, #IMM

where st = {4, 8, 16, 32, 64}, Rs = {VRs, VRAs}. Note that .64 and VRAs cannot be specified together. Use VSTROFF for Cache-off storage.

illustrate

Store vector registers in reverse element order. This instruction does not support scalar data source registers.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

MEM[EA]=see the table below: ST storage operation .b BYTE[EA+i]=VR _s [31-i]<7:0>, for i=0 to 31 .h HALF[EA+i]=VR _s [15-i]<15:0>, for i=0 to 15 .w WORD[EA+i]=VR _s [7-i]<31:0>, for i=0 to 7 .4 BYTE[EA+i]=VR _s [31-i]<7:0>, i=0 to 3 .8 BYTE[EA+i]=VR _s [31-i]<7:0>, i=0 to 7 .16 BYTE[EA+i]=VR _s [31-i]<7:0>, i=0 to 15 .32 BYTE[EA+i]=VR _s [31-i]<7:0>, i=0 to 31 .64 BYTE[EA+32+i]=VR _0s [31-i]<7:0>, i=0 to 31BYTE[EA+i]=VR _1s [31-i]<7:0>, i=0 to 31

abnormal

Invalid data address, unaligned access.

programming notes

This directive is unaffected by elemental shielding.

VSTWS span storage

Format

assembler syntax

VSTWS.st Rs, SRb, SRi

VSTWS.st Rs, SRb, #IMM

VSTWS.st Rs, SRb+, SRi

VSTWS.st Rs, SRb+, #IMM

where st = [8, 16, 32}, Rs = {VRs, VRAs}. Note that .64 mode is not supported, use VST instead. Use VSTWSOFF for Cache-off storage.

illustrate

Starting from the effective address, store 32 bytes from the vector register VRs to the memory using the scalar register SR _b+1 as the stride control register.

ST indicates the block size, the number of consecutive bytes stored from each block. SR _b+1 indicates stride, the number of bytes separating the beginning of two consecutive blocks.

Stride must be equal to or greater than block size. EA must align data length. stride and block size must be multiple data lengths.

operate

EA=SR _b +{SR _i ‖sex(IMM<7:0>)};

if(A=1)SR _b =EA;

Block-size={4‖8‖16‖32};

Stride=SR _b+1 <31:0);

for(i=0; i<VECSIZE/Block-size; i ⁺⁺ )

for(j=0; j<Block-size; j ⁺⁺ )

BYTE[EA+I*Stride+j]=VRs{i*Block-size+j}<7:0>;

abnormal

Invalid data address, unaligned access.

VSUB minus

Format

assembler syntax

VSUB.dt VRd, VRa, VRb

VSUB.dt VRd, VRa, SRb

VSUB.dt VRd, VRa, #IMM

VSUB.dt SRd, SRa, SRb

VSUB.dt SRd, SRa, #IMM

where dt = {b, b9, h, w, f}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

The contents of the vector/scalar register Rb are subtracted from the contents of the vector/scalar register Ra, and the result is stored in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={Rb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]=Ra[i]-Bop[i];

}

abnormal

Overflow, invalid operand for floating point.

VSUBS Subtract and set

Format

assembler syntax

VSUBS.dt SRd, SRa, SRb

VSUBS.dt SRd, SRa, #IMM

where dt = {b, b9, h, w, f}.

supported modes D:S:M S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w) float(f)

illustrate

Subtract SRb from SRa; store result in SRd and set VFLAG bit in VCSR.

operate

Bop={SRb‖sex(IMM<8:0>)};

SRd = SRa - Bop;

VCSR<lt, eq, gt> = status(SRa-Bop);

abnormal

Overflow, invalid operand for floating point.

VUNSHFL to shuffle

Format

assembler syntax

VUNSHFL.dt VRc, VRd, VRa, VRb

VUNSHFL.dt VRc, VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f indicate the same operation.

supported modes S VRb SRb DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of vector register VRa are deshuffled with Rb and sent to vector registers VRc:VRd as follows:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VUNSHFLH to shuffle high

Format

assembler syntax

VUNSHFLH.dt VRd, VRa, VRb

VUNSHFLH.dt VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f indicate the same operation.

supported modes S VRb SRb Ds int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of vector register VRa are deshuffled with Rb; the upper part of the result is returned to vector register VRd as follows:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VUNSHFLL to shuffle low bits

Format

assembler syntax

VUNSHFLL.dt VRd, VRa, VRb

VUNSHFLL.dt VRd, VRa, SRb

where dt = {b, b9, h, w, f}. Note that .w and .f specify the same operation.

supported modes S VRb SRb Ds int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of vector register VRa are deshuffled with Rb; the low-order part of the result is returned to vector register VRd as follows:

operate

abnormal

none.

programming notes

This directive does not use element masking.

VWBACKSP Write back from temporary storage

Format

assembler syntax

VWBACKSP.ln SRp, SRb, SRi

VWBACKSP.ln SRp, SRb, #IMM

VWEACKSP.ln SRp, SRb+, SRi

VWBACKSP.ln SRp, SRb+, #IMM

where ln={1, 2, 4, 8}. Note that VWBACK and VWBACKSP use the same opcode.

illustrate

Transfer multiple 64-byte blocks from temporary storage to storage. The effective address gives the starting address of the memory, and SRp gives the starting address of the scratch memory. The number of 64-byte blocks is specified as follows:

LN<1:0>=00: transfer a block of 64 bytes

LN<1:0>=01: transfer 2 blocks of 64 bytes

LN<1:0>=10: transfer 4 blocks of 64 bytes

LN<1:0>=11: transfer 8 blocks of 64 bytes

If the effective address does not fall on a 64-byte boundary, it is first truncated to align with a 64-byte boundary. If the address of the scratchpad pointer in SRp does not fall on a 64-byte boundary, it is also truncated and aligned to a 64-byte boundary. The pointer address of the aligned scratchpad is incremented by the number of bytes transferred.

operate

EA＝SRb+{SRi‖sex(IMM<7:0>)};

if(A=1)SRb=EA;

Num_bytes={64‖128‖256‖512};

Mem_adrs=EA<31:6>:6b′000000;

SRp=SRp<31:6>:6b′000000;

for(i=0; i<Num_bytes; i++)

SPAD[SRp++]=MEM[Mem_adrs+i];

abnormal

Invalid data address exception event.

VXNOR XOR

Format

assembler syntax

VXNOR.dt VRd, VRa, VRb

VXNOR.dt VRd, VRa, SRb

VXNOR.dt VRd, VRa, #IMM

VXNOR.dt SRd, SRa, SRb

VXNOR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of the vector/scalar register Ra and the contents of the vector/scalar register Rb are logically XORed, and the result is stored in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝-(Ra[i]<k>^Bop[i]<k>), for k＝all bits in elementi;

}

abnormal

none.

VXOR XOR

Format

assembler syntax

VXOR.dt VRd, VRa, VRb

VXOR.dt VRd, VRa, SRb

VXOR.dt VRd, VRa, #IMM

VXOR.dt SRd, SRa, SRb

VXOR.dt SRd, SRa, #IMM

where dt = {b, b9, h, w}.

supported modes D:S:M V<-V@V V<-V@S V<-V@I S<-S@S S<-S@I DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The contents of the vector/scalar register Ra and the contents of the vector/scalar register Rb are logically ORed, and the result is stored in the vector/scalar register Rd.

operate

for(i=0; i<NumElem &&EMASK[i]; i++){

Bop[i]={VRb[i]‖SRb‖sex(IMM<8:0>)};

Rd[i]<k>＝Ra[i]<k>^Bop[i]<k>, for k＝all bits in elementi;

}

abnormal

none.

VXORALL XOR all elements

Format

assembler syntax

VXORALL.dt SRd, VRb

where dt = {b, b9, h, w}. Note that .b and .b9 specify the same operation.

supported modes DS int8(b) int9(b9) int16(h) int32(w)

illustrate

The least significant bits of each element in VRb are XORed together, and the 1-bit result is returned to the least significant bit of SRd. This directive is not affected by elemental masking.

operate

abnormal

none.

VWBACK write back

Format

assembler syntax

VWBACK.ln SRb, SRi

VWBACK.ln SRb, #IMM

VWBACK.ln SRb+, SRi

VWBACK.ln SRb+, #IMM

where ln={1, 2, 4, 8}.

illustrate

Cache lines whose indices are specified by the EA in the Vector Data Cache (as opposed to those whose tags match the EA) are updated into memory if they contain modified data. If more than one cache line is specified, subsequent cache lines are updated to memory when they contain modified data. The number of cache lines is specified as follows:

LN<1:0>=00: write a 64-byte cache line

LN<1:0>=01: write two 64-byte Cache lines

LN<1:0>=10: write four 64-byte Cache lines

LN<1:0>=11: Write 8 Cache lines of 64 bytes

If the effective address does not fall on a 64-byte boundary, it is first truncated to align with a 64-byte boundary.

operate

abnormal

Invalid data address exception event.

programming notes

EA<31:0> indicates the byte address in local memory.

Claims (9)

1. A processor comprising: a scalar register, suitable for storing a single scalar value; a vector register suitable for storing multiple data elements; and processing circuitry coupled to said scalar register and said vector register, wherein the processing circuitry performs a plurality of operations in parallel in response to a single instruction, each operation combining a data element in said vector register with a data element in said scalar register The scalar values of are combined. 2. A method of operating a processing circuit to execute instructions, comprising: read the register data elements that make up the vector-valued components; and Performs a parallel operation that combines a scalar value with each data element to produce a vector result. 3. The method of claim 2, wherein the parallel operations performed include multiplying the scalar value by each of the data elements to produce a vector data result. 4. The method of claim 2, wherein said parallel operations performed include adding said scalar value to each of said data elements to produce a vector data result. 5. The method of claim 2, further comprising reading the scalar value from another register adapted to store a single scalar value to combine with the data element. 6. The method of claim 2, further comprising extracting the scalar value from an instruction to combine with the data element. 7. A method of operating a processor, comprising: providing a plurality of scalar registers and a plurality of vector registers in said processor, wherein each scalar register is adapted to store a single scalar value and each vector register is adapted to store a plurality of data elements constituting a vector component; Assign each scalar register a register number that is different from the register numbers assigned to other scalar registers; assigning each vector register a register number different from register numbers assigned to other vector registers, wherein at least some of the register numbers assigned to the vector registers are the same as the register numbers assigned to the scalar registers; forming an instruction comprising a first operand and a second operand, wherein the first operand is a register number identifying a scalar register and the second operand is a register number identifying a vector register; and The instruction is executed to transfer data between data elements in the one scalar register identified by the first operand and the one vector register identified by the second operand. 8. The method of claim 7, wherein: The instruction formed also includes a third operand for identifying data elements in a vector; and wherein The instruction is executed to transfer data between data elements identified by the third operand in the scalar register identified by the first operand and the vector register identified by the second operand. 9. The method of claim 7, wherein: said instruction formed also includes a third operand identifying another scalar register; and wherein executing the instruction to operate in the scalar register identified by the first operand and in the vector register identified by the second operand and identified by a stored value in the other scalar register Transfer data between data elements.

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