CN115223876A - A Batch High Precision Layer Transfer Heterogeneous Integration Method - Google Patents

Abstract

The invention discloses a batch high-precision layer transfer heterogeneous integration method. First, a temporary bonding process is used to reconstruct the separated chips after screening on a support carrier with high precision, and then a substrate peeling process is used to combine extremely thin chips. The chip device layer is peeled from the substrate and the bonding is transferred to the target substrate. In this way, it can not only solve the problem of batch integration of multi-chips, but also be compatible with subsequent high-precision microelectronic process processing, so as to meet the development requirements of chip miniaturization, integration and high performance. In addition, by removing the substrate and buffer layer with low thermal conductivity, adding a heat dissipation layer, using a bonding medium with high thermal conductivity, etc., the heat dissipation effect of the integrated chip can also be effectively improved.

Description

A Batch High-Precision Layer Transfer Heterogeneous Integration Method

technical field

The invention belongs to the technical field of semiconductor technology, and particularly relates to a method for heterogeneous integration of semiconductor devices.

Background technique

In the post-Moore era, the performance of traditional single-material devices is approaching the bottleneck, and the cost and complexity of developing chips based on a single process node and material structure continue to increase. By integrating different process nodes, different materials, and different types of chips, it has become an important solution for the development of chip technology in the post-Moore era. Often these chips are discrete pieces, and the challenge is how to put these discrete chips back together. A current mainstream solution is to bond these discrete chips face-down to the target substrate through die-to-wafer/die-to-die and other die-bonding equipment. Although high integration accuracy can be obtained through high-precision bonding equipment, this integration scheme is the integration of two or more chips, and the total chip thickness increases significantly after integration, and it is difficult to continue processing in microelectronics. At the same time, if only relying on bumps or gold balls for bonding, the upper chip will also face severe heat dissipation challenges, which will adversely affect the performance and reliability of the integrated chip.

SUMMARY OF THE INVENTION

Aiming at the above-mentioned deficiencies of the prior art, the present invention designs a batch high-precision layer transfer heterogeneous integration method, which solves the problem of batch integration of multi-chips, and is compatible with subsequent high-precision microelectronic process processing, so as to meet the requirements of chip miniaturization and high performance. performance development requirements.

A batch high-precision layer transfer heterogeneous integration method, comprising the following steps:

1) Spin coating protective agent on the surface of the discrete chip that needs to be integrated, covering the chip surface devices and circuit structures; 2) Spin coating adhesive on the front side of the support carrier;

3) Oppose the front side of the discrete chip to the front side of the support carrier, place them in a specific position on the support carrier in turn, and perform temporary bonding;

4) thinning the substrate temporarily bonded to the discrete chip on the support carrier;

5) removing the remaining substrate except the device layer of the discrete chip temporarily bonded to the support carrier;

6) Spin-coating permanent bonding material on the back of the discrete chip device layer after removing the substrate;

7) Align the back side of the discrete chip device layer with the front side of the target substrate to be integrated, and bond permanently;

8) separating the support carrier from the target substrate and the bonding structure composed of the discrete chip device layers permanently bonded to the target substrate, and cleaning;

9) cleaning and removing the protective agent on the surface of the discrete chip device layer on the target substrate.

Further, in step 1), the discrete chips include but are not limited to microelectronic devices, MEMS devices, optoelectronic devices, memories and/or processors, and the materials of the discrete chips include but are not limited to Si, GaAs, InP, GaN, SiC and/or LiNO ₃ , the structure of the discrete chip includes a substrate, a device layer or substrate over the substrate, a self-stop layer over the substrate, and a device layer over the self-stop layer, the discrete chip The size is 10μm×10μm to 5cm×5cm, the total thickness of the discrete chip is 30μm-725μm, the thickness of the device layer is 500nm-20μm, the protective agent is a polymer material, and the polymer material includes but does not Limited to polymethyl methacrylate, the thermal stability temperature of the protective agent is 100°C-300°C, and the protective agent can be dissolved in organic and/or alkaline inorganic reagents such as acetone.

Further, in step 2), the support carrier includes but is not limited to one of sapphire, silicon wafer, silicon carbide wafer or aluminum nitride wafer, and the thickness of the support carrier is 100 μm-1000 μm; the The adhesive is a polymer, including but not limited to one of photoresist, high temperature wax or BCB.

Further, in step 3), the method of placing the support slide at a specific position is to use flip-chip bonding or chip bonding equipment, and the placement accuracy is ±0.5μm-5μm; the temperature of the temporary bonding is 80 -250℃, the pressure is 5MPa-100MPa, and the time is 5-60 minutes.

Further, in step 4), the method for thinning the substrate is any one or more of mechanical grinding, mechanical polishing, and chemical polishing, and the thickness of the remaining substrate after thinning is not less than 1 μm, and not more than 1 μm. 100μm.

Further, in step 5), the method for removing the remaining substrate is any one or more of wet etching or dry etching, and after removing the remaining substrate, the backside of the device layer is exposed, or the device is exposed. Self-stop layer on the back of the layer.

Further, in step 6), the permanent bonding material is polymer or metal solder, the polymer includes but not limited to BCB or PI, the metal solder includes but not limited to gold tin or gold indium, the permanent bond The thickness of the composite material is 20 nm to 20 μm.

Further, in step 7), the alignment method is to use a bonding machine to align with alignment marks; the permanent bonding method includes eutectic bonding, thermocompression bonding, activation bonding and direct bonding One of the bonding methods, the bonding temperature is 100°C to 350°C, the bonding time is 1 minute to 2 hours, and the bonding pressure is 200N to 60000N.

Further, in step 8), the separation method includes but is not limited to thermal debonding, laser debonding and gas debonding.

Further, in step 9), the method for removing the protective agent includes but is not limited to solution soaking and gas etching.

Beneficial effects of the present invention:

The invention firstly adopts a temporary bonding process to reconstruct the separated chips after screening on a support carrier with high precision, and then adopts a substrate peeling process to peel off the extremely thin chip device layer from the substrate, and transfer the bonding to the target substrate. bottom. In this way, it can not only solve the problem of batch integration of multi-chips, but also be compatible with subsequent high-precision microelectronic process processing, and meet the development requirements of chip miniaturization and high performance. In addition, by removing the substrate and buffer layer with low thermal conductivity, adding a heat dissipation layer, and using a bonding medium with high thermal conductivity, the heat dissipation effect of the integrated chip can also be effectively improved.

Description of drawings

1 is a schematic diagram of spin coating a protective agent on a discrete chip surface;

Figure 2 is a schematic view of the temporary bonding of discrete chips to a support carrier;

3 is a schematic diagram of substrate thinning of discrete chips temporarily bonded to a support carrier;

4 is a schematic view of the removal of the remaining substrate of the discrete chip temporarily bonded to the support carrier;

5 is a schematic diagram of the removal of a self-stop layer from a discrete chip temporarily bonded to a support carrier;

6 is a schematic diagram of the preparation of an adhesive on the backside of a device layer of a discrete chip temporarily bonded to a support carrier;

7 is a schematic diagram of permanently bonding the backside of a device layer of a discrete chip temporarily bonded to a support carrier to a target substrate;

8 is a schematic diagram of separating a discrete chip device layer permanently bonded to a target substrate from a support carrier;

FIG. 9 is a schematic diagram of removing the protective agent from the surface of the discrete chip device layer.

Numeral description in the figure: 1, chip device layer; 2, chip self-stop layer; 3, chip substrate; 4, protective agent; 5, support carrier; 6, adhesive; 7, permanent bonding material; 8, Surface structure of target substrate; 9. Target substrate.

Detailed ways

The technical solutions of the present invention are further described below with reference to the accompanying drawings.

A batch high-precision layer transfer heterogeneous integration method, comprising the following steps:

1) Spin coating a protective agent on the surface of the discrete chip that needs to be integrated, covering the chip surface devices, circuits and other structures: the discrete chips include but are not limited to functional devices such as microelectronic devices, MEMS devices, optoelectronic devices, memories, processors, etc.; The materials of the discrete chips include, but are not limited to, Si, GaAs, InP, GaN, SiC, LiNO3, etc.; the structures of the discrete chips include a substrate, a device layer or substrate above the substrate, a self-stop layer above the substrate, and The structure of the device layer above the self-stop layer; the size of the discrete chip is 10μm×10μm to 5cm×5cm; the total thickness of the discrete chip is 30μm-725μm; the thickness of the device layer is 500nm-20μm; The protective agent is a polymer material such as polymethyl methacrylate; the thermal stability temperature of the protective agent is 100°C-300°C; the protective agent can be dissolved in organic solvents such as acetone or inorganic reagents such as TMAH, as shown in Figure 1 shown.

2) Spin coating adhesive on the front side of the support slide: wherein the support slide includes but is not limited to one of sapphire, silicon wafer, silicon carbide or aluminum nitride sheet; wherein the support slide has a thickness of 100μm-1000μm; the adhesive includes but is not limited to one of photoresist, high temperature wax or BCB and other polymers.

3) Oppose the front side of the discrete chip to the front side of the support carrier, place them in a specific position on the support carrier in turn, and perform temporary bonding: the method for placing the discrete chips on the specific position on the support carrier is to use flip-chip welding or chip Bonding and other equipment; the placement accuracy is ±0.5μm-5μm; the temporary bonding temperature is 80-250°C, the pressure is 5MPa-100MPa, and the time is 5-60 minutes, as shown in Figure 2.

4) Thinning the substrate of the discrete chip temporarily bonded to the support carrier: wherein the substrate thinning method is any one or more of mechanical grinding, mechanical polishing, and chemical polishing, and the remainder after thinning The thickness of the substrate is not less than 1 μm and not more than 100 μm, as shown in FIG. 3 .

5) Remove the remaining substrate except the device layer of the discrete chip temporarily bonded to the support carrier; wherein the remaining substrate removal method is any one or more of wet etching or dry etching, and the remaining substrate is removed. After bottoming, the backside of the device layer is exposed, or the self-stop layer on the backside of the device layer is exposed, as shown in FIG. 4 and FIG. 5 .

5) Spin-coating permanent bonding material on the back of the discrete chip device layer after removing the substrate: wherein the permanent bonding material is a polymer such as BCB (benzocyclobutene) or PI (polyimide) or gold tin , gold indium and other metal solders; the thickness of the permanent bonding material is 20nm to 20μm, as shown in Figure 6.

6) Align the back side of the discrete chip device layer after removing the substrate and the front side of the target substrate to be integrated, and permanently bond: the alignment method is to use a bonding machine to align through alignment marks; the permanent The bonding method includes one of eutectic bonding, thermocompression bonding, activated bonding and direct bonding. The bonding temperature is 100°C to 350°C, and the bonding time is 1 minute to 2 hours. The pressure is from 200N to 60000N, as shown in Figure 7.

7) Separate the support carrier from the target substrate and the bonding structure composed of the discrete chip device layers permanently bonded to the target substrate, and clean them: the separation methods include but are not limited to thermal debonding, laser debonding and gas debonding, etc. way, as shown in Figure 8.

8) Cleaning and removing the protective agent on the surface of the discrete chip device layer on the target substrate: The protective agent removal method includes but is not limited to solution immersion, gas etching, etc., as shown in FIG. 9 .

Example 1

A PMMA polymer with a thickness of about 10 μm was spin-coated on the surface of a GaAs pHEMT multifunctional chip with a size of 1.5mm×1.5mm. The GaAs pHEMT chip was composed of the device active layer, the InGaP barrier layer and the GaAs substrate.

A high temperature wax (HT10.10) with a thickness of about 15 μm was spin-coated on the front of a 4-inch sapphire support slide at a spin-coating speed of 1500 rpm, a spin-coating time of 60 s, and a pre-baking temperature of 110 °C for 2 minutes.

Through the Die to Wafer die bonding machine, the front side of the multi-functional chip spin-coated with GaAs of PMMA is opposite to the front side of the support carrier, placed in a specific position, and a temporary bonding process is performed. The specific position is aligned by the preset alignment. Mark decision. The temporary bonding process parameters are temperature 250°C, bonding time 15 minutes, and bonding pressure 200MPa.

The GaAs substrate of the GaAs multifunctional chip was thinned to 80 μm from back grinding by mechanical grinding.

The remaining 80 μm GaAs substrate of the GaAs multifunctional chip was completely removed by etching with a sulfuric acid-based etching solution until the InGaP layer was exposed.

The InGaP layer is removed by a hydrochloric acid-based etching solution to expose the backside of the active layer of the pHEMT device.

PI was spin-coated on the back of the active layer of the pHEMT device of the GaAs pHEMT multifunctional chip as a permanent bonding material, where the thickness of PI was about 2 μm, and the spin-coating speed of PI was about 2000 rpm.

The back of the GaAs multifunctional chip device layer on the support carrier is opposite to the front of the target substrate, and put into the bonding machine for permanent bonding. The bonding process parameters are temperature 200°C, bonding time 30 minutes, and bonding pressure 1500MPa.

The temporary bonding structure composed of the support carrier, the GaAs multi-functional chip device layer and the target substrate is placed face up on a heating table for heating, and the heating temperature is 250 °C. The substrates were separated, and the adhesives and protectants were cleaned with a stripper, acetone, and alcohol.

After the above steps, a batch high-precision layer transfer heterogeneous integration method is realized.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A batch high-precision layer transfer heterogeneous integration method is characterized by comprising the following steps:

1) Coating protective agent on the surface of the discrete chip to be integrated in a spinning mode to cover the device and the circuit structure on the surface of the chip;

2) Spin coating an adhesive on the front surface of the support slide;

3) The front surface of the discrete chip is opposite to the front surface of the supporting slide glass, and the discrete chip and the supporting slide glass are sequentially placed at a specific position on the supporting slide glass and are temporarily bonded;

4) Thinning a substrate of the discrete chip temporarily bonded to the support slide;

5) Removing the residual substrate of the discrete chip temporarily bonded to the supporting slide except the device layer;

6) Spin-coating a permanent bonding material on the back surface of the discrete chip device layer after the substrate is removed;

7) Aligning the back surface of the discrete chip device layer with the front surface of a target substrate to be integrated, and permanently bonding;

8) Separating and cleaning a bonding structure consisting of a support slide, a target substrate and a discrete chip device layer which is permanently bonded to the target substrate;

9) And cleaning and removing the protective agent on the surface of the discrete chip device layer on the target substrate.

2. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 1), the discrete chips comprise but are not limited to microelectronic devices, MEMS devices, optoelectronic devices, memories and/or processors, and the materials of the discrete chips comprise but are not limited to Si, gaAs, inP, gaN, siC and/or LiNO ₃ The structure of the discrete chip comprises a substrate, a device layer or a substrate above the substrate, a self-stop layer above the substrate and a device layer above the self-stop layer, the size of the discrete chip is 10 mu m multiplied by 10 mu m to 5cm multiplied by 5cm, the total thickness of the discrete chip is 30 mu m to 725 mu m, the thickness of the device layer is 500nm to 20 mu m, the protective agent is a polymer material, the polymer material comprises but is not limited to polymethyl methacrylate, the thermal stability temperature of the protective agent is 100 ℃ to 300 ℃, and the protective agent can be dissolved in organic and/or inorganic reagents.

3. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 2), the support slide comprises but is not limited to one of sapphire, silicon wafer, silicon carbide wafer or aluminum nitride sheet, and the thickness of the support slide is 100 μm-1000 μm; the adhesive is a polymer including, but not limited to, one of photoresist, high temperature waxes, or BCB.

4. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in the step 3), the method for placing the carrier at the specific position on the supporting slide adopts a flip chip bonding or chip bonding device, and the placing precision is within the range of +/-0.5 μm-5 μm; the temperature of the temporary bonding is 80-250 ℃, the pressure is 5-100 MPa, and the time is 5-60 minutes.

5. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in the step 4), the substrate is thinned by any one or more of mechanical grinding, mechanical polishing and chemical polishing, and the thickness of the thinned residual substrate is not less than 1 μm and not more than 100 μm.

6. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 5), the method for removing the residual substrate is one or more of wet etching and dry etching, and after the residual substrate is removed, the back surface of the device layer is exposed, or a self-stop layer on the back surface of the device layer is exposed.

7. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 6), the permanent bonding material is a polymer or a metal solder, the polymer includes but is not limited to BCB or PI, the metal solder includes but is not limited to gold tin or gold indium, and the thickness of the permanent bonding material is 20nm to 20 μm.

8. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in the step 7), the alignment is performed by using a bonding machine through an alignment mark; the permanent bonding mode comprises one of eutectic bonding, hot-pressing bonding, activation bonding and direct bonding, the bonding temperature is 100-350 ℃, the bonding time is 1 min-2 h, and the bonding pressure is 200N-60000N.

9. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 8), the separation method includes but is not limited to thermal decomposition bonding, laser decomposition bonding and gas decomposition bonding.

10. The batch high-precision layer transfer heterogeneous integration method according to claim 1, wherein in step 9), the method for removing the protective agent includes but is not limited to a solution immersion method and a gas etching method.

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