CN115223866A - Semiconductor device and method of forming the same - Google Patents

Abstract

The embodiment of the disclosure discloses a semiconductor device and a forming method thereof, wherein the method comprises the following steps: providing a substrate; injecting first doping ions into a first depth interval of the substrate to form a first doping layer; activating the first doping layer at high temperature to form a drain layer; injecting second doping ions into a second depth interval of the substrate to form a second doping layer; the second depth interval is non-overlapping with the first depth interval; activating the second doping layer at high temperature to form a source electrode layer; etching the source electrode layer, the drain electrode layer and the substrate between the source electrode layer and the drain electrode layer to form a channel column array; the array of channel pillars comprises a plurality of transistor channel pillars; two ends of the transistor channel column respectively comprise a source electrode and a drain electrode; and forming a plurality of storage capacitors which are not connected with each other on the sources of the channel pillars of the channel pillar array.

Description

Semiconductor device and method of forming the same

technical field

Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor device and a method for forming the same.

Background technique

The DRAM (Dynamic Random Access Memory, dynamic random access memory) architecture can be a BCT (Buried Channel Transistor, buried channel transistor) architecture, in which the source S and drain D of the transistor are located at the level of the gate G, respectively On both sides, the source S can be connected to the bit line, and the drain D can be connected to the capacitor. In this way, the source electrode S and the drain electrode D occupy different positions respectively on the horizontal plane, so that the horizontal area of the buried channel transistor is larger.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present disclosure provide a semiconductor device and a method for forming the same.

In a first aspect, embodiments of the present disclosure provide a method for forming a semiconductor device, including:

a substrate is provided; the substrate has a first surface and a second surface;

implanting first dopant ions into the first depth interval of the substrate to form a first dopant layer;

activating the first doping layer at a high temperature to form a drain layer;

implanting second doping ions into the second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval;

activating the second doping layer at a high temperature to form a source layer;

etching the source layer, the drain layer and the substrate between the source layer and the drain layer to form a channel pillar array; the channel pillar array includes a plurality of transistor channel pillars ; The two ends of the channel column of the transistor respectively comprise a source electrode and a drain electrode;

A plurality of storage capacitors that are not connected to each other are formed on the source electrodes of the plurality of channel columns of the channel column array.

In some embodiments, the method further includes:

An oxide layer is formed on the first surface of the substrate; the oxide layer is used for etching the source layer, the drain layer and between the source layer and the drain layer etch stop layer of the substrate.

In some embodiments, the step of forming an oxide layer on the first surface of the substrate is before the step of forming the first doped layer; the step of implanting the first region of the substrate into a doping ion to form a first doping layer, including:

From the surface of the oxide layer along a first direction, the first dopant ions are implanted into a first depth interval in the substrate to form the first dopant layer; wherein the first direction is formed by The first surface faces the direction of the second surface of the substrate.

In some embodiments, before the step of forming the first doped layer, the method further comprises:

along a first direction, ion implantation is performed from the oxide layer to a third depth interval of the substrate to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the first depth the distance between the interval and the first surface;

After the step of forming the first doped layer, the method further includes:

Using the ion implantation layer to remove a part of the substrate between the ion implantation layer and the second surface;

The ion implantation layer is removed to expose the third surface of the substrate.

In some embodiments, the method further includes:

Provide carrier wafers;

Bonding the oxide layer with the carrier wafer.

In some embodiments, the method further includes:

The carrier wafer and substrate are turned over so that the third surface of the substrate faces vertically upwards.

In some embodiments, the method further includes:

The third surface is planarized.

In some embodiments, the implanting of second dopant ions into the second depth interval of the substrate to form a second dopant layer includes:

implanting the second dopant ions from the third surface into the second depth interval of the substrate along a second direction to form the second dopant layer; wherein the second direction is from the The third surface faces the direction of the first surface.

In some embodiments, after forming a plurality of the storage capacitors, the method further includes:

The oxide layer is removed.

In some embodiments, between the etched channel pillar arrays, there are a plurality of parallel first trenches along a third direction; the third direction is a direction parallel to the first surface of the substrate ;

The method also includes:

A word line structure is formed within the first trench.

In some embodiments, before forming a word line structure in the first trench, the method further includes:

filling a first dielectric material between the etched channel pillar arrays;

A plurality of the first trenches along the third direction are formed in the first dielectric material.

In some embodiments, the method further includes:

A bit line structure connecting a plurality of the storage capacitors is formed.

In a second aspect, an embodiment of the present disclosure provides a semiconductor device formed by the method described in any of the foregoing embodiments.

In the embodiment of the present disclosure, the high-temperature activation of the first ion implantation layer and the second ion implantation layer has been completed before the storage capacitor is formed, and the source electrode and the drain electrode are formed, so that after the storage capacitor is formed, the device does not need to be further activated. High temperature activation. This ensures that the performance of the material used in the storage capacitor is not damaged by high temperature, and also ensures that the performance of the formed device meets the design requirements.

Description of drawings

1 is a schematic diagram of a semiconductor structure in some embodiments;

2 is a schematic diagram of a semiconductor structure in some embodiments;

3 to 13 are flowcharts of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

14 to 30 are schematic diagrams of forming a semiconductor device and an intermediate structure thereof using the method provided by the embodiments of the present disclosure.

Detailed ways

In order to facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the related drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, some technical features that are well known in the art are not described in order to avoid confusion with the present disclosure; that is, all features of an actual embodiment may not be described herein, and well-known functions and structures may not be described in detail.

In general, terms can be understood, at least in part, from their contextual usage. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a combination of features, structures or characteristics in the plural, depending at least in part on the context . Similarly, terms such as "a" or "said" may also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, belonging to "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on context.

Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not limiting of the present disclosure. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure is capable of other embodiments in addition to these detailed descriptions.

As shown in FIG. 1, the DRAM architecture can be a BCT architecture, in which the source S and the drain D of the transistor are located on the horizontal sides of the gate G respectively, the source S can be connected to the bit line, and the drain D can be connected to the capacitor connect. In this way, the source electrode S and the drain electrode D occupy different positions respectively on the horizontal plane, so that the horizontal area of the buried channel transistor is larger.

In an embodiment of the present disclosure, the DRAM architecture may be a vertical channel memory architecture (Vertical Channel Array Transistor, VCAT) as shown in FIG. 2 . The source S and the drain D of the transistor 20 in FIG. 2 are located at the upper and lower ends of the vertical channel region. In some embodiments, during the formation of the semiconductor device, a combination of wafer bonding and backside substrate reduction may be used. Thin technology, wires or other structures that connect devices can be disposed in the upper and lower surfaces of a semiconductor structure (eg, wafer), respectively. The specific formation method can be as follows: first define the source electrode on the upper surface of the semiconductor structure, and then use the bonding technology to invert the semiconductor structure, so that the upper surface of the inverted semiconductor structure (that is, the upper surface of the semiconductor structure before the inversion can be turned over) can be formed. A drain is defined on the lower surface (the other side opposite to the upper surface). This achieves the industry's most advanced 4F ² structure. However, since the drain and source are distributed at both ends of the semiconductor structure, it is necessary to perform high-temperature activation separately. If the drain is turned up, the drain is activated at high temperature. Because of the good thermal conductivity of single crystal silicon, it is difficult to absorb the activation. After the high temperature, the temperature will be conducted downward. When the temperature at the drain exceeds 950 degrees, the temperature at the capacitor structure 30 is only slightly less than 800 degrees. Degeneration occurs. And this method also increases the high temperature activation process at the primary drain, thereby increasing the cost.

If the source electrode is already defined on the upper surface of the semiconductor structure, and then the drain electrode is defined from the upper surface of the semiconductor structure, the diffusion of the ion implanted impurities will be too wide to meet the requirements of forming the target semiconductor device.

An embodiment of the present disclosure provides a method for forming a semiconductor device, as shown in FIG. 3 , including:

Step S101, providing a substrate;

Step S102, implanting first dopant ions into the first depth interval of the substrate to form a first dopant layer;

Step S103, activating the first doped layer at a high temperature to form a drain layer;

Step S104, implanting second doped ions into the second depth interval of the substrate to form a second doped layer; the second depth interval does not overlap with the first depth interval;

Step S105, activating the second doping layer at a high temperature to form a source layer;

Step S106, etching the source layer, the drain layer and the substrate between the source layer and the drain layer to form a channel column array; the channel column array includes a plurality of transistor channel columns; The terminals include a source electrode and a drain electrode, respectively;

Step S107 , forming a plurality of storage capacitors that are not connected to each other on the source electrodes of the plurality of channel columns in the channel column array.

First, step S101 is performed, and the provided substrate may be the substrate 100 shown in FIG. 14 , and the substrate 100 may include a P-type semiconductor material substrate (for example, a silicon (Si) substrate or a germanium (Ge) substrate, etc. ), N-type semiconductor substrates (such as indium phosphide (InP) substrates), compound semiconductor material substrates (such as silicon germanium (SiGe) substrates, etc.), silicon-on-insulator (SOI) substrates, and germanium-on-insulator ( GeOI) substrate, etc.

Step S102 is performed to implant first dopant ions into the first depth interval of the substrate to form a first dopant layer. The first dopant ions include N-type and P-type ions, wherein the N-type ions include phosphorus (P), arsenic (As), and antimony (Sb). P-type ions include boron (B), indium (In), and the like. The depth interval of the ion implantation is determined by the energy of the ion implantation, and the implantation depth of the first doping ions can be adjusted by adjusting the energy of the ion implantation. Ion implantation can also consider the concentration of ion implantation. Different implantation concentrations of the same implanted ions will have different effects on device performance. In some embodiments, a lower concentration of ions can be used to form a lightly doped first doped layer to Prevent device-generated hot carrier effects.

The execution step is to execute S103 , activating the first doping layer at a high temperature to form a drain layer. After the first doping layer is formed, in order to reduce ion diffusion in the first doping layer, the first doping layer may also be activated at a high temperature to fix the implanted ions in the first doping layer. Here, the first doped layer activated at high temperature is called the drain layer, and the drain layer can form the drain of the MOS device in the subsequent process. In order to activate the implanted first dopant ions and restore the mobility and other material parameters, the first dopant layer may be annealed at an appropriate time and temperature, ie, the above-mentioned high temperature activation operation. Illustratively, the high temperature activation temperature may be 900 degrees.

Step S104 is performed to implant second doping ions into the second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval.

The second dopant ions are implanted into the second depth interval of the substrate to form a second dopant layer. The second dopant ions include N-type and P-type ions, wherein the N-type ions include phosphorus (P), arsenic (As), and antimony (Sb). P-type ions include boron (B), indium (In), and the like. The depth range of the ion implantation is determined by the energy of the ion implantation, and the implantation depth of the second doping ions can be adjusted by adjusting the energy of the ion implantation. Here, the first depth interval and the second depth interval respectively represent the implantation depth ranges of the two ion implantations, that is, the positions of the first doped layer and the second doped layer in the substrate. The second depth interval does not overlap with the first depth interval, and there is a substrate with a certain thickness between them, so the implantation energy of the second dopant ions and the implantation energy of the first ions may be different.

In some embodiments, the ion implantation directions of the first ion implantation to form the first doped layer and the second ion implantation to form the second doped layer may be different. For example, referring to FIG. 4 , for the first time, ion implantation is performed from the S1 surface of the substrate 100 into the substrate 100 to form a first doped layer. For the second time, ion implantation is performed from the S2 surface of the substrate 100 into the substrate 100 to form a second doped layer. The ion implantation depths of the two ion implantations extend from the S1 surface and the S2 surface to the substrate respectively, so the two can be the same or different, but the first depth interval where the first doping layer is finally formed and the second doping layer are located. The second depth intervals in which the layers are located are located at different locations and do not overlap.

In addition, in some embodiments, the ion implantation concentration of the second doping layer and the ion implantation concentration of the first doping layer may be the same or different.

The execution step is to execute S105, activate the second doping layer at a high temperature, and form a source layer. In some embodiments, after the second doping layer is formed, in order to reduce ion diffusion in the second doping layer, the second doping layer may be activated at a high temperature to fix the implanted ions in the second doping layer. Here, the second doping layer activated at high temperature is called a source layer, and the source layer can form the source of the device in a subsequent process. The depth of the source layer in the substrate is greater than the depth of the drain layer in the substrate.

Step S106 is performed to etch the source layer, the drain layer and the substrate between the source layer and the drain layer to form a channel column array; the channel column array includes a plurality of transistor channel columns; The two ends respectively include a source electrode and a drain electrode, and there is a channel between the source electrode and the drain electrode. Because the depths of the source layer and the drain layer in the substrate are different, there is still a part of the substrate between the source layer and the drain layer.

The above-mentioned etching processes include but are not limited to dry etching and wet etching, wherein dry etching includes but is not limited to dry etching including ion milling etching, plasma etching and reactive ion etching. The etching process can also have pattern etching, which uses a masking layer (patterned photoresist) to define the area of the surface material to be etched away, and only the selected part on the substrate (not photoetched) The part covered with glue) is etched away during the etching process. There are pattern etchings that can be used to create a variety of different features on a substrate. Two ends of the plurality of transistor channel pillars formed after etching are respectively a source electrode formed by a part of the source electrode layer and a drain electrode formed by a part of the drain electrode layer. That is to say, since the source and drain of the transistor have been doped and activated at high temperature in the above steps S102 to S105, the transistor channel column and the source and drain at both ends can be formed after etching.

Step S107 is performed to form a plurality of storage capacitors that are not connected to each other on the source electrodes of the plurality of channel columns in the channel column array. In some embodiments, the substrate over the source can be removed before the storage capacitor is formed on the source. A storage node contact structure may also be included between the storage capacitor and the source. It can be understood that under the condition that the structure remains unchanged, a high-k (dielectric coefficient) dielectric material can be selected to increase the capacity of the storage capacitor. The storage capacitor may be a columnar capacitor. In some embodiments, the dielectric material in the storage capacitor may be a material with a relative permittivity value greater than a preset relative permittivity value, for example, the preset relative permittivity value may be 3.9, and the dielectric material may be TiN (nitrogen titanium).

After performing each of the above steps, a semiconductor device of an embodiment of the present disclosure may be formed.

In the embodiment of the present disclosure, the high-temperature activation of the first ion implantation layer and the second ion implantation layer has been completed before the storage capacitor is formed, and the source electrode and the drain electrode are formed, so that after the storage capacitor is formed, the device does not need to be further activated. High temperature activation. This ensures that the performance of the material used in the storage capacitor is not damaged by high temperature, so that the performance of the formed device meets the design requirements.

In some embodiments, the above method may further include:

Step S201 , forming an oxide layer on the first surface of the substrate; the oxide layer is used as an etching stop layer for etching the source electrode layer, the drain electrode layer and the substrate between the source electrode layer and the drain electrode layer. Therefore, this step S201 may be performed in the steps between the above-mentioned steps S106 and S101. For example, as shown in FIG. 4 , step S201 may be performed after step S101.

An oxide layer is formed between the drain layer and the substrate, so that when the source layer, the drain layer and the substrate between the source layer and the drain layer are etched, the oxide layer can be used as the current etching etch stop layer without over-etching into the substrate. The above oxide layer can be formed by selective growth using a growth process, for example, In-Situ Steam Generation (ISSG). The in-situ vapor generation method is a thermal annealing deposition method, which forms a high-quality oxide film by heating in a cavity and introducing oxygen atoms to combine with atoms in the semiconductor substrate. A deposition process can also be used, and the deposition process can include chemical vapor deposition (Chemical VaporDeposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), sputtering (Sputtering) , Organometallic Chemical Vapor Deposition (Metal Organic Chemical Vapor Deposition, MOCVD) or Atomic Layer Deposition (Atomic Layer Deposition, ALD) and the like. The material of the oxide layer can be silicon dioxide.

In some embodiments, the above-mentioned step S201 may be performed before the step S102; as shown in FIG. 4, in the above-mentioned step S102, the first dopant ions are implanted into the first interval of the substrate to form the first dopant layer, including :

Step S301, injecting first dopant ions into a first depth interval in the substrate from the surface of the oxide layer along a first direction to form a first dopant layer; wherein, the first direction is from the first surface to the substrate; Orientation of the second surface.

That is, the above-mentioned ion implantation process can be performed through the oxide layer. In the process of ion implantation, the first dopant ions can be implanted into the substrate from the surface of the oxide layer, and the first dopant ions can penetrate the oxide layer based on a certain energy and be implanted into the above-mentioned first depth range, thereby forming the first dopant ions. doped layer.

It can be understood that, the subsequent step of activating the first doped layer also needs to perform the step of high temperature activation on the first doped layer in the first depth interval in the substrate through the oxide layer. The oxide layer can also enhance the randomness of the direction when the doping ions enter, and suppress the channel effect of the ion implantation.

In some embodiments, before step S102, as shown in FIG. 5, the above method further includes:

Step S401, along the first direction, perform ion implantation from the oxide layer to a third depth interval of the substrate to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the distance between the first depth interval and the first surface ;

After step S102 or step S301, the above method further includes:

Step S402, using the ion implantation layer to remove part of the substrate between the ion implantation layer and the second surface;

Step S403, removing the ion implantation layer to expose the third surface of the substrate.

The oxide layer is formed on the first surface of the substrate, and the second surface of the substrate is opposite to the first surface of the substrate. Here, the direction from the first surface to the second surface is defined as the first direction. Step S401 is performed, and ion implantation is performed from the oxide layer to the third depth interval of the substrate along the first direction to form an ion implantation layer. In some embodiments, the implanted ions may be hydrogen ions, and the hydrogen ion implantation may form a bubble layer in the silicon wafer.

The distance from the third depth interval to the first surface is greater than the distance from the first doped layer to the first surface. That is, the first doped layer is not between the ion implantation layer and the second surface of the substrate.

In some embodiments, after step S102 or step S301 is performed, the following steps may be performed:

Step S402 is performed, using the ion implantation layer to remove a part of the substrate between the ion implantation layer and the second surface. For example, a substrate containing an ion implanted layer (eg, a hydrogen ion layer) can be completely cleaved from the bubble layer (ie, the ion implanted layer) by an appropriate heat treatment to form a silicon-on-insulator structure.

Step S403 is performed to remove the ion implantation layer to expose the third surface of the substrate. The cleaved remaining ion implantation layer remaining on the substrate is removed. The removal methods include but are not limited to etching process and chemical mechanical polishing (Chemical Mechanical Polishing, CMP) until the substrate is exposed. At this time, the exposed surface of the substrate is defined as a third surface, which is opposite to the first surface.

In some embodiments, as shown in FIG. 6 , the above method further includes:

Step S501, providing a carrier wafer;

Step S502, bonding the oxide layer to the carrier wafer.

In some embodiments, before step S402 is performed, the oxide layer on the first surface of the substrate can also be fixed on a support structure, and the support structure can ensure that the distance between the ion implantation layer and the second surface is removed. The structure between the ion implantation layer and the oxide layer will not be damaged when part of the substrate is placed between them. The support structure can be a carrier wafer, and the carrier wafer can use the same material as the substrate. For example, when the substrate is a silicon substrate, the carrier wafer may be a silicon wafer. The oxide layer on the first surface of the substrate can be connected to the carrier wafer by bonding.

In some embodiments, as shown in FIG. 7 , the above method further includes:

In step S601, the carrier wafer and the substrate are turned over so that the second surface of the substrate is vertically upward.

In some embodiments, the oxide layer has been bonded to the carrier wafer, and the carrier wafer is now the uppermost layer. Because what needs to be removed is a part of the substrate between the ion implantation layer and the second surface. In order to more easily remove the part of the substrate, step S601 may be performed.

In some embodiments, as shown in FIG. 8 , the above method further includes:

Step S701, performing a planarization process on the third surface.

In some embodiments, the third surface of the substrate formed after step S403 is performed may be uneven. At this time, step S701 may be performed to planarize the third surface of the thinned substrate, so as to perform subsequent steps. The method of planarization includes, but is not limited to, CMP.

In some embodiments, as shown in FIG. 9 , in the foregoing step S104 , the second dopant ions are implanted into the second depth interval of the substrate to form the second dopant layer, including:

Step S801, implanting second dopant ions from the third surface into the second depth interval of the substrate along the second direction to form a second dopant layer; wherein the second direction is the direction from the second surface to the first surface .

In some embodiments, the second doped layer may be formed by performing a second ion implantation from the third surface toward the first surface.

It can be understood that the second doping layer can be formed by the first ion implantation from the first surface, and can also be formed by ion implantation from the third surface. But the injection energy required by these two injection methods is not used. As viewed from the first surface of the substrate in the first direction, the implantation depth of the second doping layer is greater than the implantation depth of the first doping layer. Viewed from the third surface in the second direction, the implantation depth of the second doping layer is smaller than the implantation depth of the first doping layer.

In some embodiments, after step S107 is performed to form a plurality of storage capacitors, as shown in FIG. 10 , the above method further includes:

Step S901, removing the oxide layer.

In some embodiments, the oxide layer may also be removed to expose the drains of the transistor channel pillars, and other structures, such as bit line structures, may subsequently be formed on the exposed drains.

In some embodiments, before step S901 is performed, the surface of the storage capacitor can be fixed on another support structure, and the support structure can ensure that the device structure formed on the oxide layer will not be damaged when the oxide layer is removed. . The support structure may be a second carrier wafer, and the second carrier wafer may use the same material as the substrate. For example, when the substrate is a silicon substrate, the second carrier wafer may be a silicon wafer. The surface of the storage capacitor can be connected to the second carrier wafer by means of bonding. Then, the second carrier wafer and the substrate are turned over so that the first carrier wafer on the oxide layer faces upward, and then the first carrier wafer and the oxide layer are removed.

In some embodiments, after step S106 is performed, there are a plurality of parallel first trenches along a third direction between the etched channel pillar arrays; the third direction is parallel to the first surface of the substrate As shown in Figure 11, the above method further includes:

Step S1001 , forming a word line structure in the first trench.

In some embodiments, a word line structure may also be formed between two adjacent channel pillars, and the word line structure includes a gate insulating layer and a gate oxide layer. The word line structures and the channel pillars may constitute transistors. Two channel columns may share a word line structure to form a transistor, or one channel column may use a word line structure to form a transistor. The word line structure is formed at least in the first trench between the channel pillar arrays, the word line structure may cover at least one sidewall of the channel pillar, and the word line structure may also be formed around the channel pillar, which is not limited herein.

In some embodiments, before forming the word line structure in the first trench, as shown in FIG. 12 , the above method further includes:

Step S1101, filling a first dielectric material between the etched channel pillar arrays;

Step S1102 , forming a plurality of the first trenches along the third direction in the first dielectric material.

In some embodiments, the transistors may be separated from the transistors or the channel pillars may be separated by a first dielectric material to ensure electrical isolation between the transistors. Therefore, the trenches between the channel pillar arrays can now be filled with the first dielectric material to form the insulating structure. The insulating structure is etched to form a first trench. The first dielectric material may be an insulating material, such as oxides, nitrides, and combinations thereof.

In some embodiments, as shown in FIG. 13 , the above method further includes:

Step S1201, forming a conductive layer connecting a plurality of storage capacitors.

After the storage capacitor is formed, a conductive layer over the storage capacitor can also be formed, and when the DRAM formed by the method of the embodiment of the present disclosure is used, the conductive layer can be grounded and used. The conductive layer may be formed of a conductive material, such as tungsten, aluminum, copper, and the like.

The conductive layer may include a plurality of metal lines, each of which may be used to connect a plurality of storage node contacts and to ground the storage capacitor or to other circuit structures.

Embodiments of the present disclosure further provide a semiconductor device formed by the method described in any one of the above embodiments. The semiconductor device involved in the embodiments of the present disclosure is to be used in a subsequent process to form at least a part of the final device structure. Here, the final device may include a memory.

The embodiments of the present disclosure also include the following examples:

Step S101 is first performed to provide a substrate 100 as shown in FIG. 14 , the substrate has a first surface S1 and a second surface S2 opposite to the first surface, and the substrate may be a silicon substrate.

Then, step S201 is performed to form an oxide layer 200 as shown in FIG. 15 on the first surface S1 of the above-mentioned substrate 100 . In the embodiment of the present disclosure, the oxide layer 200 may be formed by implanting oxygen ions into the first surface S1 of the substrate 100 to oxidize the first surface S1 of the substrate, and then annealing at a high temperature to form the oxide layer 200 .

Then step S401 is performed, ion implantation is performed from the oxide layer 200 to the third depth interval of the substrate along the first direction, that is, the direction from the first surface S1 to the second surface S2, to form the ion implantation layer 300 as shown in FIG. 16 . In the embodiment of the present disclosure, the ions implanted by the ion implantation may be hydrogen ions, and a hydrogen ion implantation layer is formed.

Then, step S102 is performed to implant first doped ions from the oxide layer 200 into the first depth interval of the substrate 100 along the first direction to form the first doped layer 400 as shown in FIG. 17 . The first doped layer 400 is located under the oxide layer 200 , the first doped layer 400 is located on the ion implantation layer 300 , and there is a part of the substrate 100 between the first doped layer 400 and the hydrogen ion implantation layer 300 .

Then, step S501 is performed to provide a carrier wafer, and the carrier crystal may be a silicon wafer.

Then, step S502 is performed to bond the oxide layer to the carrier wafer.

Then, step S601 is performed, and the carrier wafer and the substrate are turned over so that the second surface of the substrate is vertically upward. As shown in FIG. 18 , at this time, the second surface S2 of the substrate 100 is on the topmost layer, and the carrier wafer 500 is on the bottommost layer.

Then, step S402 is performed, using the ion implantation layer to remove a part of the substrate between the ion implantation layer and the second surface. For example, by performing low temperature annealing on the semiconductor structure shown in FIG. 18 , a microbubble layer or a microcavity layer is formed in the ion implantation layer 300 , so that the carrier wafer 500 and the substrate 100 can be cleaved from the ion implantation layer 300 . , so that part of the substrate 100 between the ion implantation layer 300 and the second surface S2 can be removed to form the semiconductor structure shown in FIG. 19 . The semiconductor structure is composed of an ion implantation layer 300 , a substrate 100 , a first ion implantation layer 400 , an oxide layer 200 and a carrier wafer 500 from an upper layer to a lower layer.

Then, step S403 is performed to remove the ion implantation layer to expose the third surface of the substrate.

Then, step S103 is performed to activate the first doping layer at a high temperature to form a drain layer. The high temperature activation of the first doped layer at an appropriate temperature and time can restore the mobility and other material parameters of the implanted first ions, so that the drain layer has the target mobility and other target material parameters.

Then, step S701 is performed to planarize the third surface, and the planarization process may be CMP to form a semiconductor structure as shown in FIG. 20 . The semiconductor structure shown is the substrate 100 , the drain layer 410 , the oxide layer 200 and the carrier wafer 500 from the upper layer to the lower layer, respectively.

Then, step S104 is performed to implant second doped ions into the second depth interval of the substrate to form a second doped layer 600; the second depth interval does not overlap with the first depth interval. In the embodiment of the present disclosure, on the third surface after the planarization treatment, implantation of the second dopant ions may be performed to form the second dopant layer 600 as shown in FIG. 21 . The second doped layer 600 does not overlap with the drain layer 410 , and there is a part of the substrate 100 between the second doped layer 600 and the drain layer 410 .

Then, step S105 is performed to activate the second doped layer at high temperature to form the source layer 610 as shown in FIG. 22 ; high temperature activation of the second doped layer at an appropriate temperature and time can restore the implanted second ions Mobility and other material parameters, so the source layer 610 has a target mobility and other target material parameters.

Step S106 is then performed to etch the source layer 610 , the drain layer 410 and the substrate 100 between the source layer 610 and the drain layer 410 shown in FIG. 22 . The oxide layer 200 can be used as an etch stop layer to form a channel pillar array as shown in FIG. 23; the channel pillar array includes a plurality of transistor channel pillars 700; two ends of the transistor channel pillars 700 respectively include drains There is also a channel 110 between the electrode 411 and the source electrode 611 , and between the drain electrode 411 and the source electrode 611 . There are trenches 701 between adjacent channel pillars 700 .

Then, step S1101 is performed to fill the trenches 701 between the etched channel pillar arrays with a first dielectric material. The first dielectric material may be an oxide, nitride (eg, silicon nitride) or other insulating material. Filling the first dielectric material forms an insulating structure 702 as shown in FIG. 24 , the insulating structure 702 covers the sidewalls of the adjacent transistors, and the insulating structure 702 also covers the bottoms of the trenches between the adjacent transistors. The insulating structure 702 may be used to isolate the electrical properties between adjacent channel pillars 700 .

Then, step S1102 is performed to form a plurality of first trenches along the third direction in the first dielectric material. The third direction may be any direction parallel to the third surface of the substrate. The portion between the array of channel pillars that is not filled with the first dielectric material forms a first trench. The insulating structure 702 is etched along the third direction to form the first trench 703 as shown in FIG. 25 .

Then, step S1001 is performed to form a word line structure in the first trench. The word line structure includes a gate insulating layer and a gate conductive layer. The material for forming the gate insulating layer may be insulating materials, such as oxides, silicides, and combinations thereof. The material for forming the gate conductive layer may be a conductive material, such as metal tungsten, polysilicon, and the like.

As shown in FIG. 26 , a gate insulating layer 704 and a gate conductive layer 705 can be respectively formed in the first trench through a deposition process, which together constitute a word line structure 706 . The projection of the word line structure 706 in the Z direction may overlap with a portion of the source electrode 611 and a portion of the drain electrode 411 . Therefore, the bottom height of the word line structure 706 may be lower than the upper surface of the drain electrode 411 in the Z direction, and the top height of the word line structure 706 may be higher than the lower surface of the source electrode 611 in the Z direction. The recess structures above the word line structures 706 may be further filled with insulating material to form an insulating layer. The upper surface of the insulating layer may be flush with the third surface S3. The insulating material may be the same as or different from the first dielectric material. The shape and position of the word line structure 706 in FIG. 26 is only an example. In some embodiments, the word line structure may be shared by two adjacent transistors, and the shape of the word line structure may surround one or more sidewalls of the transistors.

Then step S107 is performed to form a plurality of storage capacitors 800 that are not connected to each other on the source electrodes 611 of the plurality of channel pillars of the channel pillar array as shown in FIG. 27 , and adjacent storage capacitors 800 may also be filled with The second dielectric layer with the same material as the first dielectric layer, for example, the material of the second dielectric layer may be nitride (eg, silicon nitride). Storage capacitor 800 may be constructed of high-k materials. A first storage node contact 803 may also be included between the storage capacitor 800 and the source electrode 611 and/or a second storage node contact 801 may be included on the storage capacitor 800 . As shown in FIG. 27, the left side of the dotted line AA' is the memory cell array area, and each memory cell may include a transistor and a storage capacitor 800. The right side of the dotted line AA' is the peripheral circuit area of the memory cell array.

Then, step S1201 is performed to form a conductive layer 900 connected to the plurality of storage capacitors 800 as shown in FIG. 28 . The conductive layer 900 may electrically connect the memory cell array with peripheral circuits of the memory cell array. The conductive layer 900 may be formed of a metal material, such as tungsten, aluminum, copper, and the like. The conductive layer 900 may also be covered with a third dielectric layer of the same material as the first dielectric layer, and the material of the third dielectric layer may be nitride (eg, silicon nitride).

In this embodiment of the present disclosure, before step S901 is performed, the surface of the third dielectric layer may also be fixed on another support structure, and the support structure can ensure that when the oxide layer is removed, the memory cell array formed on the oxide layer and the The peripheral circuit part will not be damaged. The support structure may be a second carrier wafer, and the second carrier wafer may use the same material as the substrate. For example, when the substrate is a silicon substrate, the second carrier wafer may be a silicon wafer. The surface of the third dielectric layer can be connected to the second carrier wafer by means of bonding. Then, the second carrier wafer and the substrate are turned over, as shown in FIG. 29 , so that the first carrier wafer 500 on the oxide layer 200 faces upward, and the second carrier wafer 502 is located at the bottom. Then, step S901 is performed to remove the oxide layer 200 .

The first carrier wafer 500 and the oxide layer 200 can be removed to obtain the semiconductor structure shown in FIG. 30 . A bit line structure may also be formed on the drain 411 of the semiconductor structure, which will not be repeated here.

The semiconductor device formed by the method of the embodiment of the present disclosure has completed the high temperature activation of the source terminal and the drain terminal before forming the storage capacitor, so the step of high temperature activation can not be performed after the storage capacitor is formed, so that the storage capacitor can be avoided. The loss caused by the degradation and decomposition of the dielectric composed of high-k dielectric materials ensures the performance of storage capacitors and even semiconductor devices.

It is to be understood that reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the size of the sequence numbers of the above-mentioned processes does not imply the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, rather than the embodiments of the present disclosure. implementation constitutes any limitation. The above-mentioned serial numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above are only the embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art who is familiar with the technical scope of the present disclosure can easily think of changes or substitutions. Included within the scope of protection of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (13)

1. A method for forming a semiconductor device, wherein the method comprises: a substrate is provided; the substrate has a first surface and a second surface; implanting first dopant ions into the first depth interval of the substrate to form a first dopant layer; activating the first doping layer at a high temperature to form a drain layer; implanting second doping ions into the second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval; activating the second doping layer at a high temperature to form a source layer; etching the source layer, the drain layer and the substrate between the source layer and the drain layer to form a channel pillar array; the channel pillar array includes a plurality of transistor channel pillars ; The two ends of the channel column of the transistor respectively comprise a source electrode and a drain electrode; A plurality of storage capacitors that are not connected to each other are formed on the source electrodes of the plurality of channel columns of the channel column array. 2. The method according to claim 1, wherein the method further comprises: An oxide layer is formed on the first surface of the substrate; the oxide layer is used for etching the source layer, the drain layer and between the source layer and the drain layer etch stop layer of the substrate. 3. The method of claim 2, wherein the step of forming an oxide layer on the first surface of the substrate precedes the step of forming the first doped layer; The first dopant ions are implanted in the first interval of the substrate to form a first dopant layer, including: From the surface of the oxide layer along a first direction, the first dopant ions are implanted into a first depth interval in the substrate to form the first dopant layer; wherein the first direction is formed by The first surface faces the direction of the second surface of the substrate. 4. The method of claim 2, wherein before the step of forming the first doped layer, the method further comprises: along a first direction, ion implantation is performed from the oxide layer to a third depth interval of the substrate to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the first depth the distance between the interval and the first surface; After the step of forming the first doped layer, the method further includes: Using the ion implantation layer to remove a part of the substrate between the ion implantation layer and the second surface; The ion implantation layer is removed to expose the third surface of the substrate. 5. The method according to claim 4, wherein the method further comprises: Provide carrier wafers; Bonding the oxide layer with the carrier wafer. 6. The method according to claim 5, wherein the method further comprises: The carrier wafer and substrate are turned over so that the third surface of the substrate faces vertically upwards. 7. The method according to claim 4, wherein the method further comprises: The third surface is planarized. 8 . The method according to claim 4 , wherein the implanting second dopant ions into the second depth interval of the substrate to form a second dopant layer comprises: 8 . implanting the second dopant ions from the third surface into the second depth interval of the substrate along a second direction to form the second dopant layer; wherein the second direction is from the The third surface faces the direction of the first surface. 9. The method according to claim 2, wherein after forming a plurality of the storage capacitors, the method further comprises: The oxide layer is removed. 10 . The method according to claim 1 , wherein, between the etched channel pillar arrays, there are a plurality of parallel first trenches along a third direction; and the third direction is parallel. 11 . in the direction of the first surface of the substrate; The method also includes: A word line structure is formed within the first trench. 11. The method of claim 10, wherein before forming the word line structure in the first trench, the method further comprises: filling a first dielectric material between the etched channel pillar arrays; A plurality of the first trenches along the third direction are formed in the first dielectric material. 12. The method of claim 1, wherein the method further comprises: A conductive layer connecting a plurality of the storage capacitors is formed. 13. A semiconductor device, wherein the semiconductor device is formed by the method of any one of claims 1 to 12.

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