CN115223613A - Phase change memory device, operation method and memory chip - Google Patents

Abstract

A phase change memory device, an operation method and a memory chip are used for accelerating the writing operation speed of the phase change memory device and improving the working efficiency of the phase change memory device. The phase change memory device includes: a memory array comprising a plurality of memory cells; the signal generating circuit is used for applying a pre-operation voltage to a first group of memory cells in the plurality of memory cells, and the first group of memory cells are positioned in the same row or the same column of the memory array; the current limiting modules are connected with the first group of storage units and used for limiting the operation current passing through the first group of storage units to be target current when the signal generating circuit applies the pre-operation voltage to the first group of storage units, and the target current is used for enabling the first group of storage units to be in a pre-crystallization state; and the control circuit is used for writing or erasing the first group of memory cells in the pre-crystallization state.

Description

A phase change memory device, operation method and memory chip

This application claims the priority of the Chinese patent application with the application number 202110414856.3 and the application title "A method of operating a phase change memory", which was submitted to the China Patent Office on April 17, 2021, the entire contents of which are incorporated herein by reference. middle.

technical field

The present application relates to the field of storage, and in particular, to a phase-change storage device, an operation method, and a memory chip.

Background technique

Phase change memory (phase change memory, PCM) is a new type of semiconductor memory based on chalcogenide compounds. The writing operation principle of the phase-change memory is to make the phase-change memory in a low-resistance crystalline state or a high-resistance amorphous state by applying an electrical pulse with a specific amplitude and duration to the phase-change material.

In actual use, when the phase change memory performs a write 0 operation, electrical pulses with high amplitude, short duration and rapid rising and falling edges can be applied to the phase change material of the phase change memory, and the temperature of the phase change material rises rapidly. Above the melting temperature and quenched, the state of the phase change material remains in a highly resistive amorphous state because the microscopic atoms do not have enough time to complete crystallization. When the phase change memory performs a write 1 operation, an electrical pulse with a lower amplitude but a longer duration can be applied to the phase change material, so that the temperature of the phase change material can be kept above the crystallization temperature and below the melting temperature for a period of time, thereby Can have enough time to crystallize in a low-resistance polycrystalline state.

It can be seen that the time required for the write 1 operation (ie, the crystallization process) of the phase change material is longer than the time required for the write 0 operation, which will affect the working efficiency of the phase change material in actual use.

SUMMARY OF THE INVENTION

The present application provides a phase change storage device, an operation method and a memory chip, which are used to accelerate the writing operation speed of the phase change storage device and improve the working efficiency of the phase change storage device.

In a first aspect, an embodiment of the present application provides a phase change memory device, and the phase change memory device may include: a memory array, a signal generation circuit, a plurality of current limiting modules, and a control circuit.

Wherein, the memory array includes a plurality of memory cells; a signal generation circuit is used to apply a pre-operation voltage to a first group of memory cells in the plurality of memory cells, and the first group of memory cells is located in the same row or the same column of the memory array; a current limiting module, connected to the first group of memory cells, for limiting the operating current passing through the first group of memory cells to a target current when the signal generating circuit applies a pre-operation voltage to the first group of memory cells, and the target current is used to make the first group of memory cells One group of storage cells is in a pre-crystallized state, and one current-limiting module in the multiple current-limiting modules is connected to one storage cell in the first group of storage cells; the control circuit is used for writing to the first group of storage cells in the pre-crystallized state operate.

Using the above phase change memory device, before the first group of memory cells is written, a pre-operation voltage can be applied to the first group of memory cells, and current limiting processing can be performed on the memory cells under the pre-operation voltage, so that the first group of memory cells can be stored The cell is in a pre-crystallized state, and when the memory cells in the pre-crystallized state are subsequently written separately, the memory cell can quickly enter the crystalline state from the pre-crystallized state, which speeds up the crystallization speed of the memory cell, thereby improving the phase. Storage efficiency of variable storage devices.

In a possible implementation manner, the first group of memory cells is located in the same column of the memory array, the first current limiting module in the plurality of memory modules is connected to the first memory cell in the first group of memory cells, and the first current limiting module is connected to the first memory cell in the first group of memory cells. The flow module is also used for connecting a plurality of storage units in which the first storage unit is located in the same row.

With the above phase change memory device, a plurality of current limiting modules can be connected to the first group of memory cells through the first current limiting module.

In a possible implementation manner, the first group of storage cells is located in the same row of the storage array, the second current limit module in the multiple current limit modules is connected to the second storage cell in the first group of storage cells, the second The current limiting module is also used for connecting a plurality of memory cells located in the same column of the second memory cell.

With the above-mentioned phase change memory device, a plurality of current limiting modules can be connected to the first group of memory cells through the second current limiting module.

In a possible implementation manner, the first current limiting module in the multiple current limiting modules includes any one of the following: a current mirror, a metal oxide semiconductor field effect transistor MOS, a bipolar junction transistor (BJT), an insulated gate double Polar type transistor IGBT and gallium nitride field effect transistor GaN.

In a second aspect, an embodiment of the present application provides an operation method of a phase change memory device, and the control method is applied to the phase change memory device. Specifically, the operation method includes the following steps:

Receive a write instruction, the write instruction includes a first address; according to the first address, control the signal generation circuit in the phase-change memory device to apply a pre-operation voltage to the first group of memory cells, and restrict the operation of the first group of memory cells through a plurality of The current is the target current, and the target current is used to make the first group of memory cells in a pre-crystallization state; the phase-change memory device includes a memory array, and the first group of memory cells are located in the same row or column of the memory array; the control signal generation circuit is in the pre-crystallization state. A write operation signal is applied to the first group of memory cells in the crystalline state to perform a write operation on the first group of memory cells in the pre-crystallized state.

By using the above operation method, the pre-operation voltage can be applied to the first group of memory cells corresponding to the first address, and the current flowing through the first group of memory cells can be subjected to current limiting processing. Under the action of the current state, it is converted from the current state to the pre-crystalline state. When the first group of memory cells is subsequently written separately, the memory cells can quickly enter the crystalline state from the pre-crystalline state, thereby speeding up the writing operation and improving the phase transition. The efficiency of the storage device.

In a possible implementation manner, the first group of memory cells are located in the same row of the memory array, and applying the pre-operation signal to the first group of memory cells includes: applying a first voltage to a row of memory cells in which the first group of memory cells is located, The second voltage is applied to the plurality of columns of memory cells in which the first group of memory cells are located; the absolute value of the voltage difference between the first voltage and the second voltage is greater than or equal to the threshold voltage.

In a possible implementation manner, the first group of memory cells are located in the same column of the memory array, and applying the pre-operation signal to the first group of memory cells includes: applying the first voltage to the plurality of rows of memory cells in which the first group of memory cells are located , applying a second voltage to a column of memory cells where the first group of memory cells is located.

In a possible implementation manner, the durations of the first voltage and the second voltage are within a preset interval.

With the above control method, the first group of memory cells needs to be maintained in the electric field applied by the pre-operation voltage for a period of time to ensure that the first memory cells enter the pre-crystallized state.

In a third aspect, an embodiment of the present application provides a memory chip. The memory chip may include a control circuit and a storage array, where the control circuit is used to execute an instruction, and the instruction is used to instruct the memory chip to implement the second aspect of the embodiment of the present application and any of the same. A method provided in a possible design.

Description of drawings

FIG. 1 is a schematic structural diagram 1 of a phase change memory device according to an embodiment of the present application;

FIG. 2 is a second schematic structural diagram of a phase change memory device according to an embodiment of the present application;

FIG. 3 is a third structural schematic diagram of a phase change memory device provided by an embodiment of the present application;

FIG. 4 is a fourth schematic structural diagram of a phase change memory device according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram 1 of a plurality of current limiting modules according to an embodiment of the present application;

FIG. 6 is a second schematic structural diagram of a plurality of current limiting modules according to an embodiment of the present application;

FIG. 7 is a first structural schematic diagram of a first current limiting module and a second current limiting module according to an embodiment of the present application;

FIG. 8 is a second schematic structural diagram of a first current limiting module and a second current limiting module according to an embodiment of the present application;

9 is a schematic flowchart of a control method of a phase change memory device provided by an embodiment of the present application;

FIG. 10 provides a schematic diagram of a time sequence of an erasing operation after a pre-operation according to an embodiment of the present application.

Detailed ways

The specific operation methods in the method embodiments may also be applied to the apparatus embodiments or the system embodiments. It should be noted that, in the description of the present application, "at least one" refers to one or more, wherein a plurality of refers to two or more. In view of this, in the embodiment of the present invention, "a plurality" may also be understood as "at least two". "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/", unless otherwise specified, generally indicates that the related objects are an "or" relationship. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and should not be understood as indicating or implying relative importance, nor should it be understood as indicating or implied order.

It should be pointed out that the "connection" in the embodiments of the present application refers to an electrical connection, and the connection of two electrical elements may be a direct or indirect connection between the two electrical elements. For example, the connection between A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B, or the direct connection between A and C, C and B are directly connected, and A and B are connected through C.

It should be noted that the switches in the embodiments of the present application may be metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors One or more of various types of switching devices (insulated gate bipolar transistor, IGBT), gallium nitride field effect transistor (GaN), silicon carbide (SiC) power transistor, etc., which are not one by one in this embodiment of the present application enumerate. Each switching device may include a first electrode, a second electrode and a control electrode, wherein the control electrode is used to control closing or opening of the switching device. When the switching device is closed, current can be transmitted between the first electrode and the second electrode of the switching device, and when the switching device is open, current cannot be transmitted between the first electrode and the second electrode of the switching device. Taking a MOSFET as an example, the control electrode of the switching device is the gate, the first electrode of the switching device may be the source of the switching device, the second electrode may be the drain of the switching device, or the first electrode may be the drain of the switching device. The second electrode may be the source of the switching device.

The following describes the technical features involved in the embodiments of the present application.

The phase change memory device is a new type of semiconductor memory device based on chalcogenide compounds, which is a non-volatile memory device. Phase change technology was first proposed by Ovshinsky in the 1960s. Its main technical advantages include low cost, large capacity, long life, fast speed, non-mechanical, shock-resistant, non-volatile, radiation-resistant and can be combined with standard complementary metals. Oxide semiconductor (complementary metal-oxide-semiconductor, CMOS) circuit integration.

A phase change memory device generally includes a plurality of storage cells, each storage cell includes a phase change material for storing information and a switching device connected to the phase change material. When the switching device is closed, the phase change material can receive input from an external device. When the switching device is turned off, the phase change material cannot receive the electrical signal input by the external device.

A double-ended gated device is a device with two ports, with switch-like characteristics at a specific electrical bias voltage. When an electric pulse with a specific direction and an amplitude greater than or equal to the starting voltage is applied to the two ports of the double-ended gated device, the double-ended gated device is turned on, and current can be transmitted between the two ports of the double-ended gated device. When When the amplitude of the electrical pulse applied to the two ports of the double-ended gated device is smaller than the starting voltage, the double-ended gated device is disconnected, and current cannot be transmitted between the two ports of the double-ended gated device. Specifically, the double-ended gate device may be a diode or a bidirectional threshold switch (Ovonic Threshold Switch, OTC).

Write 0 operation (RESET): The write operation of the phase-change memory device is realized by applying a high-amplitude and narrow-width electric pulse to the memory cell. Under the action of this electrical pulse, the temperature of the memory cell is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms do not have sufficient time to crystallize, the memory cell remains in a high-resistance amorphous state. It should be noted that when the memory cell is in a high resistance state, the memory cell stores data 0.

Write 1 operation (SET): It can also be called an erase operation. The erase operation of the phase change memory device is achieved by applying an electric pulse with a lower amplitude but a relatively longer duration to the memory cell. Under the action of this electrical pulse, the temperature of the memory cell is raised above the crystallization temperature and below the melting temperature, so the memory cell can be transformed into a low-resistance state through a thermally induced crystallization process. It should be noted that when the memory cell is in a low resistance state, the memory cell stores data 1 . The write operation in this embodiment of the present application includes a write 0 operation and a write 1 operation.

Direct Write: A typical feature of phase-change memory devices compared to Flash is that write operations and erase operations do not require execution order, so multi-bit write and erase operations can be completed simultaneously under a single instruction, without the need for Knowing the storage state of the operated unit in advance, there is no need to perform an erase operation and then a write operation like Flash. Due to the different writing and erasing times, the unit to which 0 data is written will complete the operation earlier than the unit to which 1 data is written.

Pre-operation: apply a pre-operation voltage pulse with a longer duration relative to the write 0 operation to the memory cell of the phase-change memory device, and limit the operation current on the memory cell to which the pre-operation voltage pulse is applied to the target current, in this voltage pulse Under the action of the current and the target current, the memory cell enters the pre-crystallization state from the current state. The principle of the pre-operation to realize the memory cell entering the pre-crystalline state is that the amorphous state of the phase change memory is a short-range disordered state, but some crystal grains are still interspersed between amorphous atoms. Under the action of an external electric field, the electric field with the highest local intensity is often distributed on the shortest path between grains and grains. Amorphous atoms under the action of these electric fields have higher energy and probability to complete the crystallization operation. Through this pre-operation, under the action of the micro-localized electric field, randomly distributed small conductive channels or nucleation crystallization centers can be formed inside the memory cell. The next write 1 operation creates a favorable condition to reduce the time required for the write 1 operation. It should be understood that under the action of the electric field of the pre-operating voltage pulse, since the operating current of the memory cell is limited, the temperature of the memory cell is lower than the crystallization temperature, and thermal crystallization does not dominate, which reduces the pre-crystallization loss of the memory cell, and also improves the performance of the memory cell. Parallelism of memory cell pre-crystallization.

Word Line (WL): A signal line required to select a row of memory cells in a memory array, and works together with a bit line to complete the selection of one or more memory cells.

Bit Line (BL): A signal line required to select a certain column of memory cells in a memory array, and works together with a word line to complete the selection of one or more memory cells.

As shown in FIG. 1, which is a schematic diagram of a possible structure of the phase change memory, referring to FIG. 1, the phase change memory may include a control circuit 101, a storage array 102, a row address decoder 103, a column address decoder 104, a data selection A multiplexer (MUX) 105 , a signal generation circuit 106 , a buffer circuit 107 and an input/output interface circuit 108 are included.

The memory array 102 may be coupled to the row address decoder 103 through the word line WL, and the memory array 102 may also be coupled to the fixed terminal of the data selector 105 through the bit line BL. The first active terminal of the data selector 105 can be coupled to the signal generating circuit 106, the second active terminal of the data selector 105 can be connected to ground or a negative voltage, wherein the fixed terminal of the data selector 105 is coupled to the second The active end, that is, the bit line BL is grounded or connected to a negative voltage by default. Signal generation circuit 106 may be coupled to buffer circuit 107 , which may be coupled to input-output interface circuit 108 . The output terminal of the column address decoder 104 is coupled to the control terminal of the data selector 105 through an address signal line (ASL).

The buffer circuit 107 is used for buffering the data transmitted between the memory array 102 and the input/output interface circuit 108 .

The address decoder (row address decoder 103 or column address decoder 104) is a multi-input and multi-output combinational logic digital circuit device. Assume that the input of the address decoder is a K-bit binary address code, and the output is 2 ^K address signals. For the ^2K changes of the input address code, only one of the ^2K address signals output by the address decoder is valid (for example, high level), and the rest are not valid (for example, low level), and different address codes The corresponding address signals are not the same.

The control circuit 101 can receive operation commands and addresses through the input and output interface circuit 108, and control other devices to perform corresponding actions according to the operation commands. The operation command may include a read command and a write command, etc., wherein the read command corresponds to a read operation, and the write command corresponds to a write operation. The address is used to indicate the location of the memory cell in the memory array 102 where the operation command is executed.

The control circuit 101 can process the input address and then send the address code of the word line to the row address decoder 103, and the row address decoder 103 decodes the address code to obtain the selected word line WL. The control circuit 101 can also process the input address and send the address code of the bit line to the column address decoder 104, and the column address decoder 104 decodes the address code to obtain the selected bit line BL. Specifically, the column address decoder 104 decodes the address code to obtain the selected address signal line ASL, and the selected address signal line ASL controls the data selector 105 to couple its fixed end with the first active end to select the bit line BL. The control circuit 101 can also control the signal generation circuit 106 to generate an operation electrical signal (eg, a voltage signal) provided to the row address decoder 103, and the row address decoder 103 applies the operation electrical signal to the corresponding word line. The control circuit 101 can also control the signal generation circuit 106 to generate an operating electrical signal (eg, a voltage signal, a current signal, usually a voltage signal) provided to the column address decoder 104, and the column address decoder 104 applies the operating electrical signal on the corresponding address signal line ASL. The control circuit 101 can also control the signal generation circuit 106 to generate an operating electrical signal provided to the bit line BL and applied to the coupled memory cells through the selected bit line BL.

The signal generating circuit 106 is configured to generate a corresponding operating electrical signal according to the instruction of the control circuit 101 . It should be noted that, according to different operations, the operation electrical signals generated by the signal generating circuit 106 are also different. The operating electrical signal involved in the embodiment of the present application may refer to a voltage signal or a current signal. The embodiment of the present application uses a voltage signal as an example for description, but is not intended to be limited thereto. In addition, the signal generating circuit 106 may be a circuit, or may include a read circuit and a write circuit according to the difference of the generated operation electrical signals, and the write circuit includes a write 0 circuit and a write 1 circuit, wherein the read circuit is used to generate the operation of the read operation Electrical signal; the write 0 circuit is used to generate the operation electrical signal of the write 0 operation; the write 1 circuit is used to generate the operation electrical signal of the write 1 operation.

The working principle of the phase change memory shown in FIG. 1 will be described below with reference to FIG. 2 and FIG. 3 .

As shown in FIG. 2 , a memory cell 200 of a memory array 102 of a phase change memory includes a coupled double terminal gate device 202 and a phase change material 201 as a variable resistor. The word line WL of the memory array 102 is coupled to one end of the double terminal gate device 202 . The bit line BL of the memory array is coupled to one end of the phase change material 201 , and the other end of the phase change material 201 is coupled to the other end of the double terminal gate device 202 .

The memory cells of the memory array of the phase change memory are repeatedly arranged in the XY physical direction. Typically, a memory array includes 2 ^M rows of memory cells in the X direction and 2 ^N columns of memory cells in the Y direction, and a total of 2 ^M+N memory cells. In order to reduce the complexity of the operation and prevent mutual interference of electrical signals, a memory cell can be selected from a memory array to perform a corresponding write operation or read operation. Among them, M and N are both natural numbers greater than 0.

The word line WL refers to the signal line used to select a row of memory cells in the memory array, and the bit line BL refers to the signal line used to select a column of memory cells in the memory array. Memory cells, that is to say, in order to select a memory cell from the memory array for corresponding operations, a word line WL can be selected by the row address decoder, and a bit line BL can be selected by the column address decoder, thereby selecting a memory cell. The number of word lines WL or bit lines BL involved in the embodiments of the present application may be multiple or one.

The row address decoder 103 includes a signal input terminal S, an enable terminal EN, ^2M input terminals and ^2M output terminals: the enable terminal EN is controlled by the control circuit 101 for enabling or disabling the row address Decoder 103; ^2M input terminals are used for inputting ^2M -bit binary address codes from the control circuit; ^2M output terminals are coupled to the 2M word lines WL of the memory array, and are used to send the ^2M word lines WL to the ^2M word lines WL 2 ^M address signals are output; the signal input terminal S is used to input the operating electrical signal from the signal generating circuit, and the row address decoder 103 can apply the input operating electrical signal to the selected word line WL.

The column address decoder 104 includes an input terminal S, an enable terminal EN, 2 ^N input terminals and 2 ^N output terminals: the enable terminal EN is controlled by the control circuit for enabling or disabling the column address decoding The ^2N input terminals are used to ^input the ^{2N -} bit ^binary address code from the control circuit; Output 2 ^N address signals; the signal input terminal S is used to input the operating electrical signal from the signal generating circuit, and the column address decoder 104 can apply the input operating electrical signal to the selected address signal line ASL to control the 2 ^N A data selector is connected to the signal generating circuit.

The data selector 105 includes ^2N enable terminals, ^2N first active terminals, ^2N second active terminals and ^2N selectors; the ^2N enable terminals are controlled by the column address decoder 104, Used to enable or disable the ^2N selectors; the ^2N first active terminals are all coupled with the signal generating circuit to receive electrical pulses input by the signal generating circuit; the ^2N second active terminals are all connected to the ground wire Connect or connect to a negative voltage; the input terminals of the 2 ^N selectors can be coupled to the first active terminal or to the second active terminal. When the input terminal of the selector is coupled to the first active terminal, the selector output terminal is selected The coupled bit line BL, the signal generating circuit applies a corresponding operating electrical pulse to the selected bit line. When the input terminal of the selector is coupled to the second active terminal, the bit line BL coupled to the output terminal of the data selector is not selected, and the memory cell connected to the non-selected bit line BL maintains the current state.

When using the phase change memory shown in FIG. 1 to perform a write operation on the first row of memory cells, the write operation process can be divided into the following steps: Step 1: Select the first word in the current storage array through the row address decoder 103 line WL; step 2, select the first bit line BL through the column address decoder 104, that is, the selected bit line BL is connected to the write circuit, and the level on the remaining unselected bit lines is 0, at this time The memory cell coupled with this bit line BL and the selected word line WL in step 1 is selected; in step 3, the write circuit sends corresponding electrical pulses to the selected memory cell to complete the write operation. It should be understood that the word line connected to the selected memory cell and The voltage difference between the bit lines should be greater than the turn-on voltage of the double-ended gate device; step 4, select other root bit lines in turn through the column address decoder 104, and repeat step 3 until the last bit line is selected the memory cell to complete the write operation.

The phase change memory operation memory cell is based on the electrothermal process generated by the electric pulse of the above-mentioned operation signal, so that the memory effective area is completely melted (write 0) and crystallized (write 1). Its main disadvantages include: restricted by physical laws, the time required for write 1 operation (generally greater than 500 nanoseconds) is more than the time required for write 0 operation (generally less than 100 nanoseconds), and the time difference between write 1 operation and write 0 operation It is very large, which affects the working efficiency of the phase change memory.

In view of this, the embodiments of the present application provide a phase change memory device, an operation method and a memory chip, which are used to speed up the write 1 operation of a memory cell and improve the work efficiency of the phase change memory device.

As shown in FIG. 3 , which is a schematic structural diagram of a phase change memory device provided by an embodiment of the present application, referring to FIG. 3 , the phase change memory device includes: a memory array 301 , a signal generation circuit 302 , a plurality of current limiting modules 303 and Control circuit 304 .

The memory array 301 includes a plurality of memory cells; the signal generation circuit 302 is used to apply a pre-operation voltage to a first group of memory cells in the plurality of memory cells, and the first group of memory cells is located in the same row or column of the memory array A plurality of current-limiting modules 303 are connected to the first group of storage cells, and are used to limit the operating current passing through the first group of storage cells to be the target current when the signal generating circuit applies a pre-operation voltage to the first group of storage cells. It is used to make the first group of memory cells in a pre-crystallized state; the control circuit 304 is used to perform a write operation on the first group of memory cells in the pre-crystallized state. Wherein, one current limiting module in the plurality of current limiting modules is connected to one storage unit in the first group of storage units. The target current may be any value in a preset current interval.

When the above-mentioned phase change memory device is used to perform a write operation on the first group of memory cells, a pre-operation voltage can be applied to the first group of memory cells in advance, and the operating current on the first group of memory cells is The first group of memory cells is pre-operated, and the first group of memory cells is placed in the pre-crystallized state in advance. When the write 1 operation signal is applied to the first group of memory cells in the pre-crystallized state in the later stage, the first group of memory cells can be quickly changed from the pre-crystallized state. The crystalline state enters the crystalline state, thereby improving the write 1 operation speed of the first group of memory cells and improving the working efficiency of the phase change memory device.

It should be understood that after the pre-operation process and pre-operation are performed on the first group of storage units, the data stored in the first group of storage units will be destroyed with a high probability. The reliability of the data cannot be guaranteed. Based on the above reasons, it is not recommended to send read commands of the same address to the storage device during the pre-operation and the write operation time after the pre-operation, but the read commands sent to storage units with different addresses are not subject to this restriction.

In actual use, as shown in FIG. 4 , the phase change memory device may further include a row address decoder 305 , a column address decoder 306 , a data selector 307 , a buffer circuit 308 and an input/output interface circuit 309 .

Among them, the row address decoder 305 is respectively connected with the control circuit 304, the signal generation circuit 302 and a plurality of current limiting modules 303, and the column address decoder is respectively connected with the control circuit 304, the signal generation circuit 302 and the data selection circuit 307; The selection circuit 307 is respectively connected with the signal generation circuit 302 and the multiple current limiting modules 303; the buffer circuit 308 is respectively connected with the signal generation circuit 302, the input and output interface circuit 309 and the control circuit 304; the input and output interface circuit 309 is respectively connected with the buffer circuit 308 and the control circuit 304. The control circuit 304 is connected.

It should be noted that the row address decoder 305, the column address decoder 306, the data selector 307, the buffer circuit 308 and the I/O interface circuit 309 have the same purpose as the conventional phase change memory, and will not be repeated here in this application.

The following describes the process of performing a write 1 operation on the first group of memory cells by taking the first group of memory cells as the first row of memory cells as an example with reference to the phase change memory device shown in FIG. 4 .

Specifically, the write 1 operation to the first address may include the following four processes:

Step 1: Select the first group of memory cells corresponding to the first address.

Specifically, the control circuit 304 outputs an effective address signal (eg, a high level) to one or more word lines WL coupled to the first group of memory cells through the row address decoding circuit 305, so as to select the memory cells associated with the first group of memory cells. For the coupled word lines WL, the control circuit 304 outputs inactive address signals (eg, low level) to the remaining word lines WL through the row address decoding circuit 305 .

The control circuit 304 outputs a valid address signal (eg, a high level) to one or more address signal lines ASL through the column address decoding circuit 306, so as to select a plurality of address signal lines ASL, and under the action of the valid address signal , the fixed end of the selector coupled with the valid address signal ASL is coupled to the first active end to select the bit line BL, that is, the selected bit line BL is coupled to the signal generating circuit 302, and the rest are connected to the unselected address signal line ASL The fixed terminal of the coupled selector is still coupled to the second active terminal under the action of the inactive address signal, so that the unselected bit line BL is still kept grounded or connected to a negative voltage. It should be understood that under the action of the selected word line WL and the selected bit line BL, the first group of memory cells is selected.

The control circuit 304 outputs an effective address signal (eg, a high level) to the plurality of bit lines BL through the signal generating circuit 302. At this time, the word line WL and the bit line BL connected to the selected first group of memory cells are respectively applied. Two electrical signals, the voltage difference between the electrical signals can satisfy the turn-on voltage of the double-ended gate device in the first group of memory cells, the double-ended gate device is turned on, and the phase change material in the storage cell can receive the corresponding voltage. Manipulate electrical signals.

Step 2: The signal generating circuit applies a pre-operation voltage to the first group of memory cells.

Specifically, a first voltage is applied to a word line WL connected to a row of memory cells in which the first group of memory cells is located, and a first voltage is applied to a plurality of bit lines BL on a plurality of rows of memory cells in which the first group of memory cells are located. Second voltage. The voltage difference between the first voltage and the second voltage can keep the double-terminal gate device in the memory cell turned on, so that the first voltage and the second voltage can be applied to the phase change material, thereby realizing the pre-operation of the first group of memory cells.

In actual use, the amplitudes of the first voltage and the second voltage corresponding to the pre-operation signal may be the same as or different from the amplitude of the effective signal applied when the first group of memory cells is selected. The amplitudes of the two voltages can be set according to the material of the phase change material and the connection device, which are not limited in this application.

It should be understood that if the amplitude of the pre-operation signal is the same as the amplitude of the effective signal applied when the first group of memory cells is selected, the function of step 1 can be realized by applying a pre-operation voltage, further reducing the pre-operation of the first group of memory cells. length of time.

In actual use, in the process of applying the pre-operation voltage to the first group of memory cells, it is necessary to limit the operation current through the first group of memory cells to the target current. Under the action of the electric field constructed by the pre-operation voltage and the target current, the first group of memory cells The cell can enter a pre-crystallized state from its current state.

Step 3: The duration for which the signal generating circuit sends the pre-operation voltage is in a preset interval.

Step 4: The control circuit turns off the row address decoder and the column address decoder, and waits for the next operation instruction.

It should be understood that when the row address decoder and the column address decoder are turned off, the first group of memory cells is disconnected from the first group of memory cells, the first group of memory cells cannot receive any operation signals, and the pre-crystallization state is stored to the first group of memory cells. in a group of storage units.

Step 5: The control circuit applies a write 1 operation signal to the pre-crystallized memory cells in sequence. It should be noted that when the write 1 operation is applied to the memory cell in the pre-crystallized state, the memory cell in the pre-crystallized state needs to be selected first. For the selection method, please refer to step 1, which will not be repeated in this application.

When the above-mentioned phase change memory device is used to apply a pre-operating voltage to the first group of memory cells, the operating current passing through the first group of memory cells needs to be limited to the target current, so that the first group of memory cells can enter the pre-crystallized state from the current state, and When the operating current passing through the first group of memory cells is limited, the power and heat generated during the pre-operation of the first group of memory cells can be reduced to meet the heat dissipation and energy consumption requirements of the phase-change memory device, thereby increasing the pre-operation storage The number of cells further improves the working efficiency of the phase change memory device.

In actual use, multiple current limiting modules 303 may be used to limit the operating current passing through the first group of memory cells as the target current. The working principles of the multiple current limiting modules 303 will be described below.

Specifically, the plurality of current limiting modules 303 may include: a first current limiting module and a second current limiting module.

Wherein, if the first group of memory cells is located in the same column of the memory array 301, the first current limit module in the plurality of current limit modules 303 is connected to the first memory cell in the first group of memory cells, and the first current limit module is also used for Connect a plurality of memory cells located in the same row as the first memory cell; if the first group of memory cells is located in the same column of the memory array 301, the second current limiting module in the plurality of current limiting modules 301 is connected to the memory cells in the first group of memory cells. For the second storage unit, the second current limiting module is further configured to connect a plurality of storage units located in the same column as the second storage unit.

In a possible implementation manner, if the first group of memory cells is located in the same column of the memory array 301, the first current limiting module includes a plurality of first current limiting sub-modules, and the first current limiting sub-module is connected to the first group of memory cells. The multiple word lines connected to the column where the cells are located are in one-to-one correspondence; if the first group of memory cells is located in the same row of the memory array 101 , the second current limiting module includes a plurality of second current limiting sub-modules, and the second current limiting sub-module is connected to the second current limiting sub-module. There is a one-to-one correspondence between a plurality of bit lines connected to a row of a group of memory cells.

Specifically, as shown in FIG. 5 , one end of each first current-limiting sub-module is connected to the row address decoder 305 , and the other end of each first current-limiting sub-module is connected to a corresponding word line. One end of each second current limiting sub-module is connected to the data selector, and the other end of each second current limiting module is connected to the corresponding bit line.

When the above-mentioned current limiting module is used to limit the operating current passing through the first group of memory cells, if the first group of memory cells is located in the same row of the memory array, the plurality of second current-limiting sub-modules connected to the first group of memory cells can be controlled to work, each The second current limiting sub-module can perform current limiting processing on one storage unit connected in the first group of storage units. Similarly, if the first group of memory cells are located in the same column of the memory array, the plurality of first current-limiting sub-modules connected to the first group of memory cells can be controlled to work, and each first current-limiting sub-module can control the first group of memory cells. A storage unit connected in the current limit processing.

In another possible implementation manner, if the first group of memory cells is located in the same column of the memory array 301, the first group of memory cells includes multiple first storage cells, and the multiple current limiting modules include multiple first current limiting modules module, the first storage unit is in one-to-one correspondence with the first current limiting module; if the first group of storage units is located in the same column of the storage array 301, the first group of storage units includes multiple second storage units, and the multiple current limiting modules include There are a plurality of second current limiting modules, and the second storage units are in one-to-one correspondence with the second current limiting modules.

Specifically, as shown in FIG. 6, one end of each first current limiting module is connected to the row address decoder 305, and the other end of each first current limiting module is connected to the corresponding first storage unit; each second limiting module is connected to the corresponding first storage unit; One end of the current module is connected to the data selector, and the other end of each second current limiting module is connected to the corresponding second storage unit.

When the above-mentioned current limiting module is used to limit the operating current passing through the first group of memory cells, if the first group of memory cells is located in the same row of the memory array, a plurality of second current limiting modules connected to the first group of memory cells can be controlled to work, each The second current limiting module may perform current limiting processing on one storage unit connected in the first group of storage units. Similarly, if the first group of storage cells is located in the same column of the storage array, the plurality of first current limiting modules connected to the first group of storage cells can be controlled to work, and each first current limiting module can be connected to the first group of storage cells. One of the storage units is current-limited.

In a possible implementation manner, if the first group of memory cells is located in the same column of the memory array 301, the plurality of current limiting modules further include a plurality of third current limiting modules, and the third current limiting modules are connected to the first group of memory cells. The other memory cells in the column except the first group of memory cells are connected in one-to-one correspondence; if the first group of memory cells is located in the same row of the memory array 301, the plurality of current limiting modules 303 also include a plurality of fourth current limiting modules, The fourth current limiting module is connected in a one-to-one correspondence with other memory cells except the first group of memory cells in the row where the first group of memory cells is located.

In actual use, the current limiting module can use a variety of devices to limit the operating current through the first group of storage units. Below, the first storage unit and the first current limiting module are connected in one-to-one correspondence, and the second storage unit and the second current limiting module. Take the one-to-one connection as an example to describe several current-limiting frameworks of the current-limiting module.

Example 1

Referring to FIG. 7 , the first current limiting module may include a switch S1. The first electrode of the switch S1 is connected to the row address decoder, and the second electrode of the switch S1 is connected to the first storage unit corresponding to the first current limiting module. Similarly, the second current limiting module may also include a switch S2. The first electrode of the switch S2 is connected to the signal generating circuit, the second electrode of the switch S2 is connected to the data selector, and the second electrode of the switch S2 is connected to the second storage unit corresponding to the second current limiting module.

In actual use, the control electrodes of the switches S1 and S2 can be connected to a signal generation circuit or a control circuit, and the control circuit or the control circuit control signal generation circuit outputs a control signal for the switches S1 and S2 to control the working states of the switches S1 and S2, In order to control the magnitude of the operating current passing through the first storage unit and the second storage unit connected to the switches S1 and S2.

When the above-mentioned current limiting module is used to limit the operating current through the first group of memory cells, if the first group of memory cells is located in the same column of the memory array, the control circuit or the signal generation circuit is used to control the multiple switches S1 connected to the first group of memory cells. The electrode (not shown) outputs a first control signal, the first control signal can control the switch S1 to close, and by controlling the amplitude of the first control signal, adjust the current amplitude through the switch S1, so as to limit the first The operating current of the group memory cells is the target current. Similarly, if the first group of memory cells is located in the same row of the memory array, the control circuit or the signal generation circuit outputs a second control signal for the control electrodes (not shown) of the plurality of switches S2 connected to the first group of memory cells, and the second The control signal can control the switch S2 to close, and adjust the amplitude of the current through the switch S2 by controlling the amplitude of the second control signal, so as to limit the operating current of the first group of connected memory cells to the target current.

It should be understood that in an ideal situation, when the switches S1 and S2 are closed, the voltage across the switches S1 and S2 is zero voltage. Therefore, it is not necessary to consider that during the process of applying the pre-operation voltage, the switches S1 and S2 occupy a part of the pre-operation voltage when they are closed.

Example 2

Referring to FIG. 8 , the first current limiting module may include a switch S3 and a resistor R1. The second current limiting module may include a switch S4 and a resistor R2.

The switch S3 and the resistor R1 are connected in parallel to form a first branch; one end of the first branch is connected to the row address decoder, and the other end of the first branch is connected to the first storage unit corresponding to the first current limiting module; the switch S4 and resistor R2 are connected in parallel to form a second branch; one end of the second branch is connected to the data selector, and the other end of the second branch is connected to the second storage unit corresponding to the second current limiting module.

Specifically, the control electrodes of the switches S3 and S4 can be connected to the signal generation circuit 302 or the control circuit, and the control circuit or the control circuit control signal generation circuit 302 sends corresponding control signals to the switches S3 or S4 to control the working states of S3 and S4 , to control the magnitude of the operating current passing through the first storage unit and the second storage unit connected to the switches S3 and S4.

When the above-mentioned current limiting module is used to limit the operating current passing through the first group of memory cells, if the first group of memory cells is located in the same column of the memory array, the control circuit or the signal generation circuit is used to control the multiple switches S3 connected to the first group of memory cells. The electrode (not shown) outputs a third control signal, and the third control signal can control the switch S3 to be turned off. At this time, the first storage unit is connected with the resistor R1, and the resistor R1 can limit the operating current through the connected first storage unit as the target current. Similarly, if the first group of memory cells is located in the same row of the memory array, the control circuit or the signal generation circuit outputs a fourth control signal for the control electrodes (not shown) of the plurality of switches S4 connected to the first group of memory cells, and the fourth The control signal can control the switch S4 to be turned off. At this time, the second storage unit is connected to the current limiting resistor R2, and the resistor R2 can limit the operating current through the connected second storage unit to the target current.

In specific implementation, when the first current limiting module and the second current limiting module use resistors R1 and R2 for current limiting, both ends of the resistors R1 and R2 will bear a part of the pre-operating voltage. The amplitude of the pre-operation voltage across the two ends of the phase change material in the group of memory cells is reduced, and the pre-crystallization state cannot be entered.

It should be understood that when there is no need to limit the current of the storage unit connected to the first current limiting module or the second current limiting module, the switches S3 and S4 can be controlled to be closed, and at this time, the resistor R1 is short-circuited by the switch S3, and the resistor R2 is short-circuited by the switch S4. Thereby eliminating the power consumption of resistors R1 and R2.

It should be understood that the above description of the structures of the first current limiting module and the second current limiting module is only an example. In practical applications, the first current limiting module and the second current limiting module may also adopt other structures, such as the first current limiting module. The module and the second current limiting module may include current mirrors for limiting the operating current through the first group of memory cells to a target current.

Based on the same inventive concept, an embodiment of the present application provides a control method for a phase change memory device, and the control method can be applied to the phase change memory device shown in FIG. It takes a long time, thereby improving the working efficiency of the phase change memory device.

The following describes a control method for a phase change memory device provided by an embodiment of the present application with reference to FIG. 9 . The method can be applied to the phase change memory device shown in FIG. 3 , and the execution body may be a control circuit, which specifically includes the following steps :

Step 901: Receive a write instruction. The write instruction includes the first address.

Specifically, the phase-change memory device can receive a write command through an input-output port circuit.

Step 902: According to the first address, the control signal generation circuit applies a pre-operation voltage to the first group of memory cells, and limits the operation current passing through the first group of memory cells to a target current through a plurality of current limiting modules. Wherein, the first group of memory cells are located in the same row or the same column of the memory array, and the target current is used to make the first group of memory cells in a pre-crystallized state.

Specifically, the foregoing description of the process of applying the pre-operation voltage to the first group of memory cells and the process of performing current limiting on the first group of memory cells will not be repeated in this application.

Step 903: The control signal generating circuit applies a write operation signal to the first group of memory cells in the pre-crystallized state, so as to perform a write operation on the first group of memory cells in the pre-crystallized state.

When the first address is written in the above manner, a pre-operation voltage can be applied to the first group of memory cells corresponding to the first address in advance, and the operation current passing through the first group of memory cells is limited to the target current. Under the action of the electric field generated by the current limiting, the first group of memory cells is in a pre-crystallized state. In the later stage, a write 0 operation signal is applied to the first group of memory cells in the pre-crystallized state, and the first group of memory cells can quickly enter from the pre-crystallized state. crystalline state, thereby improving the speed of the write 0 operation of the first address and improving the working efficiency of the phase change memory device.

It should be noted that, under the action of the electric pulse corresponding to the pre-operation voltage of the first group of memory cells, the electric pulse of the corresponding duration is required for the phase change material to be converted into the pre-crystalline state. Therefore, the duration of the first voltage and the second voltage requires within the preset range. It should be noted that the durations of the first voltage and the second voltage may be set according to the material of the memory cell and the electrical signal amplitudes of the first voltage and the second voltage. For example, when the absolute value of the voltage difference between the first voltage and the second voltage is 5V, the duration of the first voltage and the second voltage may be 400 nanoseconds (ns).

In the following, taking the phase change memory device shown in FIG. 6 as an example, the process of speeding up the writing operation duration of the memory cell after the pre-operation will be described.

Assume that the voltages on the selected word lines in the memory array are all V1=0V; the bias voltage on the unselected word lines in the memory array is V2=5V; the bias voltage on the unselected bit lines in the memory array is V3=0V; the memory array The bias voltage on the middle selected bit line is V4=-5.0V; the required duration of the pre-operation is 400ns; the electric pulse time of the write operation is 100ns; the electric pulse time of the erase operation is 500ns.

If the first group of memory cells in the memory array corresponding to the first address is a row of memory cells, when the memory cell corresponding to the first address needs to be erased, the control circuit controls the signal generation circuit to generate the first signal and the second signal, and controls the The circuit first sends a start-up signal to the current-limiting switch S2 connected to a plurality of bit lines coupled with the first group of memory cells, the start-up signal controls the switch S2 to close, and the signal generation circuit sends a word line coupled to the first group of memory cells. The first signal is output on the upper side, and the signal generating circuit outputs the second signal to all the bit lines. When the duration of the first signal and the second signal reaches 400ns, the first group of memory cells enters the pre-crystallization state.

The electrical signals on the word lines and bit lines coupled to the first group of memory cells are canceled, and at this time, the word lines and bit lines coupled to the first group of memory cells are in an unselected state. At this time, the pre-crystallized state of the first group of memory cells is stored in the first group of memory cells, and the signal generation circuit sequentially applies an erase operation signal to each memory cell of the first group of memory cells, then each memory cell of the first group of memory cells. The memory cells are sequentially switched from a pre-crystallized state to a crystalline state.

It should be understood that since the memory cell has entered the = pre-crystal state after the write-erase operation, when an erase operation signal is applied to the memory cell, the memory cell can quickly enter the crystalline state from the pre-crystal state, which speeds up erasing. The duration of the operation.

Specifically, the calculation of the required duration of the wipe operation after the pre-operation can refer to the following:

Referring to FIG. 10 , the pre-operation duration t1 = 400 ns; the ordinary erasing operation duration t2 = 500 ns without pre-operation; and the erasing operation duration t3 = 100 ns after the pre-operation. When writing and erasing a row of memory cells, if the row or column size is 1024 bits. The total time consumption of the erase operation after the pre-operation is t4=400ns+100ns*1024=102.8us; the total time consumption of the ordinary write and erase operation=500ns*1024=512us. It can be seen that the wiping operation time after the pre-operation can be reduced to about 1/5.

Based on the same inventive concept as the method embodiment, an embodiment of the present application further provides a memory chip, the memory chip includes a memory array and a control circuit, and the control circuit is configured to execute the method performed by the method embodiment shown in FIG. 9 above. , and the relevant features can be found in the foregoing method embodiments, which will not be repeated here.

The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions. When computer program instructions are loaded or executed on a computer, the procedures or functions according to the embodiments of the present invention result in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device. Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g. coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.) to another website site, computer, server, or data center. A computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains a set of one or more available media. Useful media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media. The semiconductor medium may be a solid state drive (SSD).

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (9)

1. A phase change memory device, comprising:

a memory array comprising a plurality of memory cells;

a signal generating circuit for applying a pre-operation voltage to a first group of memory cells in the plurality of memory cells, the first group of memory cells being located in a same row or a same column of the memory array;

a plurality of current limiting modules connected to the first group of memory cells for limiting an operating current through the first group of memory cells to a target current when the signal generation circuit applies the pre-operating voltage to the first group of memory cells, the target current being for causing the first group of memory cells to be in a pre-crystallized state, one of the plurality of current limiting modules being connected to one of the first group of memory cells;

and the control circuit is used for writing the first group of memory cells in the pre-crystallization state.

2. The phase change memory device as claimed in claim 1, wherein the first group of memory cells are located in a same column of the memory array, and a first current limiting module of the plurality of current limiting modules is connected to a first memory cell of the first group of memory cells, and the first current limiting module is further configured to connect to a plurality of memory cells located in a same row as the first memory cell.

3. The phase change memory device as claimed in claim 1, wherein the first group of memory cells are located in a same row of the memory array, and a second current limiting module of the plurality of current limiting modules is connected to a second memory cell of the first group of memory cells, and the second current limiting module is further configured to be connected to a plurality of memory cells located in a same column as the second memory cell.

4. The phase change memory device as claimed in any one of claims 1 to 3, wherein each of the plurality of current limiting modules comprises any one of: a current mirror, a metal oxide semiconductor field effect transistor MOS, a bipolar junction type tube BJT, an insulated gate bipolar transistor IGBT and a gallium nitride field effect transistor GaN.

5. A method of operating a phase change memory device, comprising:

receiving a write instruction, wherein the write instruction comprises a first address;

controlling a signal generation circuit in a phase change memory device to apply a pre-operation voltage to a first group of memory cells according to the first address, and limiting an operation current passing through the first group of memory cells to a target current through a plurality of current limiting modules, wherein the target current is used for enabling the first group of memory cells to be in a pre-crystallization state, and the phase change memory device comprises a memory array, and the first group of memory cells are located in the same row or the same column of the memory array;

controlling the signal generation circuit to apply a write operation signal to the first group of memory cells in the pre-crystalline state to write the first group of memory cells in the pre-crystalline state.

6. The method of claim 5,

the first group of memory cells are located in the same row of the memory array, and the applying a pre-operation voltage to the first group of memory cells comprises:

applying a first voltage to a row of memory cells in which the first group of memory cells is located, and applying a second voltage to a plurality of columns of memory cells in which the first group of memory cells is located; the absolute value of the voltage difference between the first voltage and the second voltage is greater than or equal to the threshold voltage.

7. The method of claim 5, wherein the first group of memory cells are located in a same column of the memory array, and wherein the applying the pre-operation voltage to the first group of memory cells comprises:

applying a first voltage to a plurality of rows of memory cells in which the first group of memory cells is located and applying a second voltage to a column of memory cells in which the first group of memory cells is located; the absolute value of the voltage difference between the first voltage and the second voltage is greater than or equal to the threshold voltage.

8. The method of claim 6, wherein the duration of the first voltage and the second voltage is within the preset interval.

9. A memory chip, the memory chip comprising: control circuitry to execute instructions to instruct the memory chip to implement the method of any of claims 5 to 8, and a storage array.

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