CN115220661B

CN115220661B - Methods, apparatus and computer equipment for managing mapping tables of DRAM-less solid-state drives

Info

Publication number: CN115220661B
Application number: CN202210914480.7A
Authority: CN
Inventors: 李建; 邱一霄; 赵连庚
Original assignee: Suzhou Yilian Information System Co Ltd
Current assignee: Suzhou Yilian Information System Co Ltd
Priority date: 2022-08-01
Filing date: 2022-08-01
Publication date: 2025-11-04
Anticipated expiration: 2042-08-01
Also published as: CN115220661A

Abstract

This application relates to a mapping table management method, apparatus, computer device, and storage medium for a DRAM-less solid-state drive (SSD). The method includes: managing mapping table units in SSDRAM that are smaller than those in HMB, and the mapping table units in HMB are the same size as those stored in NAND; calculating the mapping table unit number to be accessed based on the logical address to be accessed by the user; loading the corresponding numbered mapping table unit from NAND into the HMB cache, wherein the mapping table unit is divided into multiple mapping table unit fragments; swapping the required mapping table unit fragment from the HMB cache to SSDRAM; and obtaining the required NAND address from the mapping table unit fragment in SSDRAM. This invention can reduce the overhead of mapping table swapping between HMB and SSD internal RAM, improve mapping table access efficiency, and reduce command response latency.

Description

Mapping table management method and device for DRAM-less solid state disk and computer equipment

Technical Field

The present invention relates to the field of solid state disks, and in particular, to a mapping table management method and apparatus for a DRAM-less solid state disk, a computer device, and a storage medium.

Background

SSD (Solid STATE DRIVE, solid state disk) is used as a novel storage medium, NAND particles are used as data storage, and the storage medium is widely applied to various fields such as PCs, notebooks and servers and gradually replaces HDD (HARD DISK DRIVE, mechanical hard disk) to become a main stream application product in the storage field.

At present, a DRAM-less SSD typically uses HMB (Host Memory Buffer ) to cache the mapping table, and the mapping table units managed in HMB and the mapping table units managed in the internal RAM of the SSD are identical in size to the mapping table units stored in the NAND. When the mapping table unit stored in the NAND is large, the time taken to swap the mapping table from the HMB to the internal RAM of the SSD is also large, which has an adverse effect on the command response delay.

Disclosure of Invention

Based on this, it is necessary to provide a mapping table management method, device, computer equipment and storage medium for a DRAM-less solid state disk in order to solve the above technical problems.

A mapping table management method of a DRAM-less solid state disk comprises the following steps:

the mapping table unit managed in the SSD RAM is smaller than the mapping table unit managed in the HMB, and the mapping table unit managed in the HMB is consistent with the mapping table unit stored in the NAND in size;

Calculating the number of the mapping table unit to be accessed according to the logical address to be accessed by the user;

loading corresponding numbered mapping table units from the NAND into the HMB cache, the mapping table units being partitioned into a plurality of mapping table unit slices;

The mapping table unit fragments which need to be accessed are exchanged from the HMB cache to the SSD RAM;

And acquiring the NAND address to be accessed from the mapping table unit fragments in the SSD RAM.

In one embodiment, the mapping table unit managed in the SSD RAM is smaller than the mapping table unit managed in the HMB, and the step of the mapping table unit managed in the HMB conforming to the mapping table unit size stored in the NAND further includes:

the HMB map cache contains map caches in all SSD RAMs.

In one embodiment, the method further comprises:

When the dirty mapping fragments in the SSD RAM reach a certain threshold value, the process of writing back the NAND by the dirty mapping table is triggered.

In one embodiment, the step of triggering the process of writing back the NAND from the dirty map table when the dirty map slice in the SSD RAM reaches a certain threshold value includes:

updating the dirty mapping fragments in the SSD RAM to the mapping table caches corresponding to the HMB, and writing the corresponding dirty mapping pages in the HMB into the NAND.

A mapping table management device of a DRAM-less solid state disk comprises:

The management module is used for enabling the mapping table units managed in the SSD RAM to be smaller than the mapping table units managed in the HMB, and enabling the mapping table units managed in the HMB to be consistent with the mapping table units stored in the NAND;

The calculation module is used for calculating the mapping table unit number to be accessed according to the logical address to be accessed by the user;

the loading module is used for loading the mapping table units with corresponding numbers from the NAND into the HMB cache, and the mapping table units are divided into a plurality of mapping table unit fragments;

The exchange module is used for exchanging the mapping table unit fragments which need to be accessed from the HMB cache to the SSD RAM;

the acquisition module is used for acquiring the NAND addresses to be accessed from the mapping table unit fragments in the SSD RAM.

In one embodiment, the management module is further configured to:

the HMB map cache contains map caches in all SSD RAMs.

In one embodiment, the apparatus further includes a write-back module, where the write-back module is configured to:

In one embodiment, the write-back module is further configured to:

A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the methods described above when the computer program is executed.

A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.

The mapping table management method, the mapping table management device, the mapping table management computer device and the mapping table units managed by the storage medium in the SSD RAM are smaller than the mapping table units managed in the HMB, the mapping table units managed in the HMB are consistent with the mapping table units stored in the NAND, the mapping table unit numbers needing to be accessed are calculated according to the logical addresses required to be accessed by the user, the mapping table units with the corresponding numbers are loaded into the HMB cache from the NAND, the mapping table units are divided into a plurality of mapping table unit fragments, the mapping table unit fragments needing to be accessed are exchanged from the HMB cache to the SSD RAM, and the NAND addresses required to be accessed are obtained from the mapping table unit fragments in the SSD RAM. The mapping table unit of the RAM cache in the SSD is smaller than the mapping table unit of the HMB cache, so that the cost of exchanging the mapping table between the HMB and the RAM in the SSD can be reduced, the access efficiency of the mapping table is improved, and the response delay of commands is reduced.

Drawings

FIG. 1 is a flowchart of a mapping table management method of a DRAM-less solid state disk in one embodiment;

FIG. 2 is a flowchart of a mapping table management method of a DRAM-less solid state disk according to another embodiment;

FIG. 3 is a diagram illustrating address mapping relationships in one embodiment;

FIG. 4 is a diagram of a mapping table load access in one embodiment;

FIG. 5 is a schematic diagram of a dirty map write NAND in one embodiment;

FIG. 6 is a diagram of a state after a dirty map is written to NAND in one embodiment;

FIG. 7 is a block diagram illustrating a mapping table management apparatus for a DRAM-less solid state disk according to one embodiment;

FIG. 8 is a block diagram illustrating a mapping table management apparatus for a DRAM-less solid state disk according to another embodiment;

fig. 9 is an internal structural diagram of a computer device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Currently, in the prior art scheme, the DRAM-less SSD typically uses HMB (HostMemory Buffer ) to cache the mapping table, and the mapping table units managed in HMB and the mapping table units managed by the internal RAM of the SSD are both identical in size to the mapping table units stored in the NAND. When the mapping table unit stored in the NAND is large, the time taken to swap the mapping table from the HMB to the internal RAM of the SSD is also large, which has an adverse effect on the command response delay.

Based on the above, the invention provides a mapping table management method of a DRAM-less solid state disk, which aims to improve the access efficiency of the mapping table and reduce the response delay of commands.

In one embodiment, as shown in fig. 1, there is provided a mapping table management method of a DRAM-less solid state disk, the method comprising:

Step 102, the mapping table unit managed in the SSD RAM is smaller than the mapping table unit managed in the HMB, and the mapping table unit managed in the HMB is consistent with the mapping table unit stored in the NAND;

104, calculating the number of the mapping table unit to be accessed according to the logical address to be accessed by the user;

step 106, loading the mapping table units with corresponding numbers from the NAND into the HMB cache, wherein the mapping table units are divided into a plurality of mapping table unit fragments;

step 108, the mapping table unit fragments which need to be accessed are exchanged from the HMB cache to the SSD RAM;

Step 110, obtaining the NAND address to be accessed from the mapping table unit in the SSD RAM.

In the embodiment, a mapping table management method of a DRAM-less solid state disk is provided, in the method, a mapping table unit cached by a RAM in an SSD is smaller than a mapping table unit cached by an HMB, and the cost of exchanging the HMB mapping table into the SSD RAM is reduced, so that command response delay is reduced. The specific implementation process is as follows:

In one embodiment, the HMB map cache contains map caches in all SSD RAM.

Specifically, referring to fig. 3, the relationship between the user address and the primary mapping table (L2P table), the secondary mapping table (M2P) table is described, and the configuration in the schematic diagram is lpn=lbn/8, mpn=lpn/1024. The L2P table records the mapping of LPNs to NAND addresses, and the M2P table records the mapping of MPNs to NAND addresses. In a DRAM-less SSD, the L2P table is too large to reside in RAM, typically using HMB cache and swapping from HMB to SSD internal RAM when access is needed.

In the scheme, the mapping table unit managed in the SSD RAM is smaller than the mapping table unit managed in the HMB, and the mapping table unit managed in the HMB is consistent with the mapping table unit stored in the NAND. And the HMB map cache is a superset of the map cache in SSD RAM, i.e., the former contains the latter.

Then, when the mapping table to be accessed is not in the cache, the mapping table is loaded from the NAND to the HMB cache, and then the part to be accessed is exchanged from the HMB to the SSD RAM.

Specifically, referring to fig. 4, a loading diagram of a mapping table is described:

First, the mapping table unit number to be accessed is calculated according to the logical address to be accessed by the user. The corresponding mapping table unit is then loaded from the NAND to the HMB Cache. Next, the slices of the map units that need to be accessed are swapped into SSD RAM (each map unit is divided into 2 slices in the example). And finally, acquiring the NAND addresses to be accessed from the mapping table unit fragments in the SSD RAM.

In the embodiment, the mapping table units managed in the SSD RAM are smaller than the mapping table units managed in the HMB, the mapping table units managed in the HMB are consistent with the mapping table units stored in the NAND, the mapping table unit numbers needing to be accessed are calculated according to the logical addresses needing to be accessed by the user, the mapping table units with the corresponding numbers are loaded into the HMB cache from the NAND and divided into a plurality of mapping table unit fragments, the mapping table unit fragments needing to be accessed are exchanged from the HMB cache to the SSD RAM, and the NAND addresses needing to be accessed are obtained from the mapping table unit fragments in the SSD RAM. The mapping table unit of the RAM cache in the SSD is smaller than the mapping table unit of the HMB cache, so that the cost of exchanging the mapping table between the HMB and the RAM in the SSD can be reduced, the access efficiency of the mapping table is improved, and the response delay of commands is reduced.

In one embodiment, as shown in fig. 2, a mapping table management method of a DRAM-less solid state disk is provided, and the method further includes:

step 202, triggering a process of writing back the NAND of a dirty mapping table when a dirty mapping slice in an SSD RAM reaches a certain threshold value;

In step 204, the dirty mapping fragments in the SSD RAM are updated to the mapping table caches corresponding to the HMBs, and then the corresponding dirty mapping pages in the HMBs are written into the NAND.

In this embodiment, a mapping table management method for a DRAM-less solid state disk is provided, where when a dirty mapping slice in an SSD RAM reaches a specified threshold, a dirty mapping table write-back NAND process is triggered.

Specifically, referring to fig. 5, in this process, the dirty map slices in the SSD RAM are updated to the map table caches corresponding to the HMBs, and then the corresponding dirty map pages in the HMBs are written into the NAND. FIG. 6 depicts the map cache and map state in NAND after write-back is completed.

In this embodiment, the overhead of exchanging the mapping table between the HMB and the RAM in the SSD may be reduced, so as to improve the access efficiency of the mapping table, and further achieve the purpose of reducing the response delay of the command.

It should be understood that, although the steps in the flowcharts of fig. 1-6 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-6 may include multiple sub-steps or phases that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or phases are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or phases of other steps or other steps.

In one embodiment, as shown in fig. 7, there is provided a mapping table management apparatus 700 of a DRAM-less solid state disk, the apparatus comprising:

A management module 701, where the mapping table unit managed in the SSD RAM is smaller than the mapping table unit managed in the HMB, and the mapping table unit managed in the HMB is identical to the mapping table unit stored in the NAND in size;

The computing module 702 is configured to compute a mapping table unit number to be accessed according to a logical address to be accessed by a user;

a loading module 703, configured to load, from the NAND, a mapping table unit of a corresponding number into the HMB cache, where the mapping table unit is divided into a plurality of mapping table unit slices;

The exchange module 704 is configured to exchange the mapping table unit fragments that need to be accessed from the HMB cache to the SSD RAM;

and the acquiring module 705 is configured to acquire the NAND address to be accessed from the mapping table unit slice in the SSD RAM.

In one embodiment, the management module 701 is further configured to:

the HMB map cache contains map caches in all SSD RAMs.

In one embodiment, as shown in fig. 8, there is provided a mapping table management apparatus 700 of a DRAM-less solid state disk, and the apparatus further includes a write-back module 706, configured to:

In one embodiment, the write-back module 706 is further configured to:

For specific limitation of the mapping table management device of the DRAM-less solid state disk, reference may be made to the limitation of the mapping table management method of the DRAM-less solid state disk hereinabove, and the description thereof will not be repeated here.

In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 9. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by the processor, implements a mapping table management method for a DRAM-less solid state disk.

It will be appreciated by persons skilled in the art that the architecture shown in fig. 9 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting as to the computer device to which the present inventive arrangements are applicable, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method embodiments above when executing the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the above method embodiments.

Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A mapping table management method of a DRAM-less solid state disk comprises the following steps:

obtaining the NAND address to be accessed from the mapping table unit fragments in the SSD RAM;

When the dirty mapping fragments in the SSD RAM reach a certain threshold value, triggering a process of writing back the NAND by the dirty mapping table;

when the dirty mapping fragments in the SSD RAM reach a certain threshold value, triggering the process of writing back the NAND by the dirty mapping table, wherein the process comprises the steps of updating the dirty mapping fragments in the SSD RAM into the mapping table caches corresponding to the HMB, and writing the corresponding dirty mapping pages in the HMB into the NAND.

2. The mapping table management device of the DRAM-less solid state disk is characterized by comprising the following components:

The acquisition module is used for acquiring the NAND address to be accessed from the mapping table unit fragments in the SSD RAM;

the management module is also used for the HMB mapping table cache to contain mapping table caches in all SSD RAMs;

the device also comprises a write-back module, wherein the write-back module is used for triggering the write-back NAND process of the dirty mapping table when the dirty mapping fragments in the SSD RAM reach a certain threshold value;

The write-back module is further used for updating the dirty mapping fragments in the SSD RAM to the mapping table caches corresponding to the HMB, and then writing the corresponding dirty mapping pages in the HMB into the NAND.

3. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of claim 1 when executing the computer program.

4. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of claim 1.