CN115206970A - Capacitor, semiconductor device, electronic device, and manufacturing method thereof - Google Patents

Abstract

The application relates to a capacitor structure comprising: a semiconductor substrate; a plurality of storage node contacts on the semiconductor substrate; each storage node contact part is provided with a lower electrode of a semi-surrounding structure, and each two opposite lower electrodes of the semi-surrounding structure form a pair of lower electrode pairs surrounding the upper electrode; the two opposite lower electrodes and the upper electrodes of the lower electrode pair are separated by a dielectric layer. The capacitor and the semiconductor device obtained by the manufacturing method can effectively reduce the difficulty of the manufacturing process on the premise of ensuring the performance of devices such as the storage capacity of a capacitor storage unit, and the like, and break through the limitation of the traditional 6F2 groove process mode on the basis of simplifying the process, so that the gap between the capacitors is reduced, the size of the prepared capacitor is smaller than that of the existing capacitor, and the integration level of the semiconductor device is improved.

Description

Capacitor, semiconductor device, electronic device, and manufacturing method thereof

technical field

The present application relates to a capacitor and a method of manufacturing the same, and also relates to a semiconductor device, an electronic device including the capacitor, and a method of manufacturing the same.

Background technique

In recent years, as semiconductor users require semiconductor devices to have low power consumption, high storage capacity, and high-speed characteristics, semiconductor manufacturers have increasingly researched high-integration, high-speed semiconductor devices. In particular, Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory) is widely used as a semiconductor memory unit because of its free data input and output capability and large storage capacity.

However, in order to rapidly improve the integration and expandability of memories, the integration density of semiconductor devices has been continuously increased, and the design size standards of semiconductor devices have also been continuously reduced. For example, in general, a DRAM is a collection of cells, and each cell has a MOS (Metal Oxide Semiconductor) transistor and a storage capacitor. As the integration level increases, the size of the semiconductor chip decreases, and the size of the capacitor will inevitably decrease, and the decrease in the size of the capacitor will gradually reduce the spacing between the electrodes and accordingly reduce the capacitance of the capacitor, thereby reducing the size of the capacitor. Capacitor storage capacity. However, even in view of the increased integration of semiconductor memories, it is necessary to make the capacitors have sufficient capacitance to ensure smooth operation and performance of the semiconductor memory device.

There are two main types of DRAM memories in use: one is a DRAM memory with an area of 8F2 memory cells; the other is a DRAM memory with an area of 6F2 memory cells. Among them, DRAM memory with 8F2 memory cells is widely used in DRAM memory due to improved signal-to-noise ratio, but consumes more memory cell area compared to memory with 6F2 memory cells because of its many free areas. While the memory with 6F2 memory cells provides some improvements in reducing the memory cell area, there are still some problems in production using this technology, for example, the process difficulties associated with smaller memory cells.

Therefore, how to propose a method for manufacturing a capacitor storage unit with a simpler manufacturing process to achieve a smaller storage unit area and a higher charge storage capacity has become an important technical problem to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of this application is achieved through the following technical solutions:

According to one or more embodiments, the present application discloses a capacitor structure comprising:

semiconductor substrate;

a plurality of storage node contacts on the semiconductor substrate;

Each of the storage node contact portions is provided with a lower electrode of a semi-surrounding structure, and every two opposite lower electrodes of the half-surrounding structure form a pair of lower electrodes surrounding the upper electrode;

The two opposite lower electrodes of the lower electrode pair and the upper electrodes are separated from each other by a dielectric layer.

According to one or more embodiments, the present application also discloses a method for manufacturing a capacitor structure, which includes the following process steps:

providing a semiconductor substrate having storage node contacts thereon;

forming a sacrificial mold layer on a semiconductor substrate;

etching the sacrificial mold layer to form a plurality of lower electrode grooves, exposing the surfaces of two adjacent storage node contact portions in each of the lower electrode grooves;

depositing a lower electrode layer to fill the lower electrode groove, and then performing chemical mechanical planarization or etchback to expose the sacrificial mold layer;

etching the lower electrode layer and the sacrificial mold layer to form an upper electrode groove, and the upper electrode groove divides the lower electrode layer into a pair of opposite lower electrodes of a half-enclosed structure;

A dielectric layer and an upper electrode are formed in the upper electrode groove.

According to one or more embodiments, the present application also discloses semiconductor devices, electronic devices, and the like that include the above capacitor structure, or include the capacitor structure prepared by the above manufacturing method.

Other features and advantages of the present application will be set forth in the description which follows, and, in part, will become apparent from the description, or may be inferred or unambiguously determined from the description, or may be implemented by practice of the present application. example to understand. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description, claims, and drawings.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for purposes of illustrating preferred embodiments only and are not to be considered limiting of the application. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

1a-1h are schematic diagrams of a fabrication process of a capacitor structure according to an embodiment of the present application.

2 is a cross-sectional plan view of a capacitor structure according to an embodiment of the present application.

FIG. 3 is a pattern used when forming a lower electrode groove in an embodiment of the present application.

4a-4c are the patterns used in forming the upper electrode grooves in the embodiments of the present application.

FIG. 5 is a diagram showing the corresponding positional relationship between the upper electrode groove and the lower electrode groove.

Detailed ways

The application will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that they will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numerals identify like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing the embodiments in detail only and is not intended to limit the application. As used herein, the singular forms "a," "the," and "the" and the like include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" used in the specification describes the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude one or more other features, integers, steps, operations, elements The presence or addition of , components, and/or combinations thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extending directly into the other element or intermediate elements are present. In contrast, when an element is referred to as being "directly on" or "extending directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections are not limited by these terms . These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.

Furthermore, relative terms such as "below" or "bottom" and "above" or "top" are used herein to describe one element's relationship to another element as illustrated in the figures. It should be understood that relative terms include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being below other elements would then be above the other elements. The exemplary term "below" thus includes both "below" and "above" directions according to the particular orientation of the figures. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would be oriented over the other elements. Thus, the exemplary terms "below" or "under" include both an orientation of above and below.

Embodiments of the application are described herein with reference to cross-sectional illustrations (and/or plan views) that are schematic illustrations of idealized embodiments of the application. Likewise, deviations from the schematic shape due to, for example, manufacturing process and/or tolerances, can be expected. Thus, the embodiments of the present application are not to be considered as limitations on the specific shapes of the regions described herein, but rather to include deviations in shapes resulting from, for example, manufacturing. For example, an etched region illustrated or described as a rectangle typically has rounded or curvilinear features. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not represent the precise shape of a region of a device and do not limit the scope of the present application.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be construed to be consistent with the meanings in the related art literature, and not to be construed as idealized or excessively formal, unless expressly defined herein. It will be understood by those skilled in the art that a reference to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.

The present application discloses a capacitor structure and a manufacturing method thereof. Each storage node of the capacitor has a lower electrode with a semi-circumferential structure that can be, for example, a semi-cylindrical shape, and the lower electrodes of the two opposite semi-circumferential structures form a pair of lower electrodes surrounding the upper electrode, and through the techniques in the art any suitable shape obtained. The following embodiments take a capacitor formed by a lower electrode having a semi-cylindrical semi-enclosed structure as an example, but the present application is not limited to this. The specific capacitor structure and manufacturing process are as follows:

As shown in FIG. 1h and FIG. 2 , a semiconductor device including a capacitor structure is exemplified in the embodiments of the present application, and the semiconductor device can be used in, for example, a certain electronic device, and the electronic device can be a smart phone, a computer, a tablet computer, a wearable Smart devices, artificial intelligence devices, power banks, etc. The semiconductor device includes a semiconductor substrate, such as a semiconductor substrate of a circuit element of a MOS (MetalOxide Semiconductor) transistor, on which functional components (not shown) such as gate, source/drain, and bit lines are formed, for example. An interlayer insulating layer 201 (Interlayer Insulation) is formed on the semiconductor substrate; a storage node contact portion 202 (Storage Node) is formed on the interlayer insulating layer 201 . A lower electrode 209 may be formed on the upper portion of each storage node contact portion 202. In this embodiment, the lower electrode 208 has, for example, a semi-cylindrical C-shaped opening and semi-surrounding structure, and is located at two adjacent storage nodes. The upper two lower electrodes 209A and the C-shaped openings of the lower electrodes 209B are mirror images opposite to each other, forming a lower electrode pair, which surrounds the peripheral side of the upper electrode 210, and the lower electrode 209A, the lower electrode 209B and the upper electrode 219. A dielectric layer 210 is formed therebetween to separate the three from each other. In this way, the lower electrode 209A and the upper electrode 211 and the lower electrode 209B and the upper electrode 211 form two independent capacitor storage units. Viewed as a whole, on a cross section parallel to the semiconductor substrate, all the lower electrodes may be linearly arranged in parallel along the first direction, and these linearly arranged lower electrodes are staggered on two adjacent lines; at the same time, all the upper electrodes It can also be linearly arranged in parallel along a second direction perpendicular to the first direction, and these linearly arranged upper electrodes are also staggered on two adjacent lines. In other embodiments, on a cross section parallel to the semiconductor substrate, the upper electrodes on the same line can be connected to each other to form a whole, or all the upper electrodes on the same line can be connected to each other to form a whole. A whole.

Next, referring to FIGS. 1a-1h, the process technology and materials used for the above-mentioned semiconductor device disclosed according to an embodiment of the present application will be described in further detail:

The process technology of the present application can first provide a semiconductor substrate on which circuit elements such as BCAT (Buried Channel Array Transistor) transistors have been formed, and on the semiconductor substrate, for example, functional components such as gates, source/drain, and bit lines are formed (not shown). icon).

As shown in FIG. 1a, an interlayer insulating layer 201 (InterlayerInsulation) may be formed on the semiconductor substrate; a storage node 202 (Storage Node) may be formed on the interlayer insulating layer 201, and the storage node 202 (Storage Node) may be composed of W or Co and other materials.

Then, a sacrificial mold layer 203 (Mold) can be formed on the surface of the interlayer insulating layer 201 and the storage node 202 , and the sacrificial mold layer 203 is usually made of oxide, that is, an oxide sacrificial mold layer (Mold Oxide). May contain doped oxides, for example, SiO2, SiOH, PSG (Phosphosilicate glass, phosphosilicate glass), BPSG (Borophosphosilicate glass, borophosphosilicate glass), SiCOH, TEOS (Tetraethylorthosilicate, ethyl orthosilicate) Any one or a combination of two or more of the above; the sacrificial mold layer can also adopt a layered structure of multiple layers, such as the layered structure of TEOS. The sacrificial mold layer can be formed by a suitable process such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

Subsequently, a hard mask layer 204 (HM, Hard Mask) may be formed on the surface of the oxide sacrificial mold layer 203, and the hard mask layer may include polysilicon (Poly-Si), doped silicon (Dope-Si) formed by a CVD process , Amorphous carbon (ACL), spin-on silicon (SOH) layers and other common hard mask materials. In other embodiments, a photoresist layer may be directly used for patterning and subsequent etching without forming a hard mask layer.

Subsequently, a photoresist layer 205 (PR, PhotoResist) may be formed on the surface of the hard mask layer 204, and the photoresist layer may be formed by, for example, a spin coating process; then, the photoresist layer 205 may be patterned by a developing process to The surface of the hard mask layer 204 is exposed. The mask pattern for removing the photoresist part is shown in Figure 3. The mask pattern is composed of a plurality of rectangular lower electrode groove mask pattern units. The plurality of lower electrode groove mask pattern units can be The parallel cross-section of the substrate is in parallel linear arrangement along the first direction, and is staggered on two adjacent lines; the projection of each lower electrode groove mask pattern unit on the cross-section parallel to the semiconductor substrate substantially covers two Adjacent storage nodes are standard (reference is shown in conjunction with the structure in Figure 2).

As shown in FIG. 1b, then, conventional etching methods can be used to etch the hard mask layer 204 and the sacrificial mold layer 203 on the photoresist layer 205 patterned according to the mask pattern shown in FIG. 3 . In order to obtain the lower electrode groove 206, the cross-sectional structure of the top view of the lower electrode groove 206 can be combined as shown in FIGS. 2 and 3, wherein the rectangular frame of the lower electrode groove mask pattern unit basically corresponds to the position of the lower electrode groove, that is, the lower electrode groove. The etching of the electrode grooves 206 may be based on the fact that the bottoms of the grooves substantially expose the entire surfaces of the two adjacent storage nodes 202 . The etching can use a conventional dry etching process, for example, a dry etching process using a fluorine-containing gas of CH ₂ F ₂ /O ₂ /Ar/CHF ₃ ; a conventional wet etching process can also be used, such as , including a mixed buffer solution of HF and NH4F, eg, a LAL solution of HF:NH4F mixed in a ratio of about ₁ : ₆ to 1:10.

Subsequently, the hard mask layer 204 and the photoresist layer 205 may be removed, for example, using conventional ashing processes and other removal means.

As shown in FIG. 1c, subsequently, a lower electrode material may be deposited in the lower electrode groove 206 to fill the lower electrode groove 206 and cover the sacrificial mold layer 203 to form a lower electrode layer 207 (Bottom Electrode); Dielectric materials of dielectric constant, such as Ta ₂ O ₅ , Al ₂ O ₃ and/or HfO ₂ , etc. are used as the dielectric layers of capacitors, and the quality of the interface between the dielectric materials and the polysilicon electrodes may be degraded. In particular, the quality of the interface between the dielectric material and the polysilicon electrode may decrease as the dielectric constant increases, therefore, metals with high work function such as _TiNx , _TaNx , _WNx can be used Any one or a combination of two or more refractory metal materials is used as the lower electrode to replace the traditional polysilicon electrode. The deposition process may adopt common CVD, PECVD, ALD (atomic layer vapor deposition) and other processes.

As shown in FIG. 1d, then, the surface of the lower electrode layer may be subjected to chemical mechanical planarization (Chemical Mechanical Polish, CMP) treatment until the top surface of the sacrificial mold layer 203 is exposed, so that the lower electrode layers may be isolated from each other. Of course, other processes can also be used to etch back the surface of the lower electrode layer, so as to expose the top surface of the sacrificial mold layer 203 to isolate the lower electrode layers from each other. The etch back process is, for example, reactive ions Dry etching process (RIE).

As shown in FIG. 1e, subsequently, a hard mask layer 204' (HM, Hard Mask) may be formed on the surfaces of the lower electrode layer 207 and the sacrificial mold layer 203, and the hard mask layer may include polysilicon (Poly-Si) formed by a CVD process. ), doped silicon (Dope-Si), amorphous carbon (ACL), spin-on silicon (SOH) layers and other common hard mask materials. In other embodiments, a photoresist layer may be directly used for patterning and subsequent etching without forming a hard mask layer.

As shown in FIG. 1f, subsequently, a photoresist layer 205' (PR, PhotoResist) can be formed on the surface of the hard mask layer 204', and the photoresist layer can be formed by, for example, a spin coating process; The photoresist layer 205 ′ is exposed to expose the surface of the hard mask layer 204 ′. For example, the patterning can be performed by a double patterning technique or a multi-patterning technique. The mask pattern for removing the photoresist part is shown in Figure 4a, the mask pattern is composed of a plurality of upper electrode groove mask pattern units crossed by "+", and the plurality of upper electrode groove mask pattern units It can be in a parallel linear arrangement along a second direction perpendicular to the first direction on a cross-section parallel to the semiconductor substrate, and in a staggered distribution on two adjacent lines; as shown in FIG. 5, the upper electrode groove mask The pattern units may be in one-to-one correspondence with the lower electrode groove mask pattern units, and the intersections of the "+" crosses of the projections of each upper electrode groove mask pattern unit on a cross-section parallel to the semiconductor substrate are aligned to align The center of the projection of the corresponding lower electrode groove mask pattern unit on the cross-section parallel to the semiconductor substrate is the criterion, so that the projection of the pattern extending in the first direction of the "+" cross all falls into the lower electrode The inside of the projection of the groove mask pattern unit to be mainly used to form the deposition grooves of the dielectric layer and the upper electrode in the lower electrode layer, and the projection of the pattern extending in the second direction extends to the lower electrode groove mask pattern unit The outside of the projection is used to "cut" each lower electrode layer unit into two independent lower electrodes to form a lower electrode pair surrounding the upper electrode; in this embodiment, with the lower electrode groove mask The pattern unit is similar to a rectangle, and the pattern of the upper electrode groove mask pattern unit extending in the first direction and the pattern of the upper electrode groove mask pattern unit extending in the second direction are all rectangular, and in order to achieve their respective functions, The width of the lower electrode groove mask pattern unit is greater than the width of the pattern extended along the first direction by the upper electrode groove mask pattern unit (so as to ensure that all the patterns of the upper electrode groove mask pattern unit extending along the first direction fall into the lower Inside the electrode groove mask pattern), the width of the pattern extended in the first direction by the upper electrode groove mask pattern unit is greater than the width of the pattern extended in the second direction by the upper electrode groove mask pattern unit (the upper electrode groove mask pattern unit is extended in the second direction). The pattern of the mold pattern unit extending in the second direction can achieve a "separation" effect), and at the same time, the length of the pattern extended in the second direction by the upper electrode groove mask pattern unit is at least slightly larger than that of the lower electrode groove mask pattern. The width of the cells (thereby ensuring that the pattern of the upper electrode groove mask pattern cells extending in the second direction extends outside the lower electrode groove mask pattern to ensure "spaced apart"). In other embodiments, as shown in FIG. 4b, adjacent “+” crosses on the same line may be connected two by two, which can make the patterning process simpler and easier, without affecting the performance of the device. On the premise, the difficulty of the process is reduced; and further in other embodiments, as shown in FIG. 4c , all “+” crosses on the same line may be connected to each other to further simplify the pattern and process.

Then, conventional etching methods can be used to etch the hard mask layer 204 ′ and the lower electrode layer 207 according to the patterned photoresist layer 205 ′ to obtain the upper electrode groove 208 and the upper electrode groove 208 4a, 4b or 4c, the bottom of the upper electrode groove 208 is based on the exposed surface of the two adjacent storage nodes 202. After etching, each lower electrode layer 207 The lower electrodes 209A and 209B are divided to form two semi-cylindrical C-shaped openings with a semi-surrounding structure. The etching can use a conventional dry etching process, for example, a dry etching process using a fluorine-containing gas of CH ₂ F ₂ /O ₂ /Ar/CHF ₃ ; a conventional wet etching process can also be used, such as , including a mixed buffer solution of HF and NH4F, eg, a LAL solution of HF:NH4F mixed in a ratio of about ₁ : ₆ to 1:10.

Subsequently, the hard mask layer 204' and the photoresist layer 205' may be removed, for example, using conventional ashing processes and other removal means.

As shown in FIG. 1g, subsequently, a high dielectric material may be deposited on the inner wall of the upper electrode groove 208 and the lower electrode (including all the lower electrodes of 209A and 209B) and the surface of the sacrificial mold layer 203 to form a dielectric layer 210; The electrical material can be any one or a combination of two or more of AlO _x , HfO _x , ZrO _x , TaO _x , etc. The deposition process is, for example, an ALD process.

As shown in FIG. 1h, subsequently, an upper electrode material can be deposited on the surface of the dielectric layer 210 to cover the dielectric layer 210 and fill the upper electrode groove 208 to form the upper electrode 211; the upper electrode material is metal W or doped silicon, etc. . The deposition process may be CVD, PECVD, or the like. In this way, as shown in the cross-sectional plan view in FIG. 2 , it can be obtained that a lower electrode 209 is formed on the upper part of each storage node 202 . The lower electrode 209 has a semi-cylindrical C-shaped semi-enclosed structure, and the semi-cylindrical shape is The C-shaped openings are mirrored opposite, so that the two lower electrodes 209A and 209B located on the two adjacent storage nodes form a lower electrode pair that surrounds the peripheral side of the upper electrode 211, and A dielectric layer 210 is formed between the electrode 209A, the lower electrode 209B and the upper electrode 211 to separate the three from each other. The lower electrode 209A and the upper electrode 211 and the lower electrode 209B and the upper electrode 211 form two independent capacitors storage unit. Of course, based on the difference in patterning, it is also possible to obtain a capacitor in which the adjacent upper electrodes on the same line along the second direction are connected in pairs in the vertical direction to the semiconductor substrate to form a whole, that is, equivalent to four lower electrodes (two A pair of lower electrodes) corresponds to the upper electrode that is integrated in the entire vertical direction to the semiconductor substrate; it is also possible to make all the upper electrodes on the same line along the second direction to be connected to each other in the entire vertical direction to the semiconductor substrate. , that is, all the lower electrode pairs on the same column correspond to the upper electrodes that are integrated in the vertical direction to the semiconductor substrate.

The capacitor and semiconductor device obtained by the manufacturing method in the present application can effectively reduce the difficulty of the manufacturing process on the premise of ensuring the device performance such as the storage capacity of the capacitor storage unit, and on the basis of simplifying the process, break through the traditional 6F2 trench process method Therefore, the gap between the capacitors is reduced, the size of the capacitor is smaller than that of the existing capacitor, and the integration degree of the semiconductor device is improved.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (15)

1. A capacitor structure, comprising:

a semiconductor substrate;

a plurality of storage node contacts on the semiconductor substrate;

each storage node contact part is provided with a lower electrode of a semi-surrounding structure, and each two opposite lower electrodes of the semi-surrounding structure form a pair of lower electrode pairs surrounding the upper electrode;

the two opposite lower electrodes and the upper electrodes of the lower electrode pair are separated by a dielectric layer.

2. The capacitor structure of claim 1, wherein:

on a cross section parallel to the semiconductor substrate, the lower electrodes are linearly arranged in parallel along a first direction, and the upper electrodes are linearly arranged in parallel along a second direction perpendicular to the first direction.

3. A capacitor structure according to claim 2, characterized in that:

the lower electrodes in linear arrangement are in staggered distribution on two adjacent lines; or, the lower electrodes arranged linearly are distributed in a staggered manner on two adjacent lines, and the upper electrodes arranged linearly are distributed in a staggered manner on two adjacent lines.

4. A capacitor structure according to claim 2, characterized in that:

the upper electrodes on the same line are connected into a whole in pairs; alternatively, all the upper electrodes on the same line are connected to each other as a single body.

5. The capacitor structure of any one of claims 1-4, wherein:

and on a section parallel to the semiconductor substrate, each two opposite lower electrodes of the semi-surrounding structure are in opposite C shapes.

6. A method for manufacturing a capacitor structure comprises the following process steps:

providing a semiconductor substrate, wherein a storage node contact part is arranged on the semiconductor substrate;

forming a sacrificial mold layer on a semiconductor substrate;

etching the sacrificial mold layer to form a plurality of lower electrode grooves, and exposing the surfaces of two adjacent storage node contact parts in each lower electrode groove;

depositing a lower electrode layer to fill the lower electrode groove, and then carrying out chemical mechanical planarization treatment or back etching treatment to expose the sacrificial mold layer;

etching the lower electrode layer and the sacrificial mold layer to form an upper electrode groove, wherein the upper electrode groove divides the lower electrode layer into a pair of opposite lower electrodes with a semi-surrounding structure;

and forming a dielectric layer and an upper electrode in the upper electrode groove.

7. The manufacturing method according to claim 6, characterized in that:

when the sacrificial film layer is etched to form a plurality of lower electrode grooves, the adopted plurality of lower electrode groove mask pattern units are linearly arranged on the section parallel to the semiconductor substrate along the first direction in a parallel mode, and the lower electrode groove mask pattern units are distributed in a staggered mode on two adjacent lines.

8. The manufacturing method according to claim 7, characterized in that:

when the lower electrode layer and the sacrificial mold layer are etched to form the upper electrode groove, a plurality of upper electrode groove mask pattern units which correspond to the lower electrode groove mask pattern units one by one are adopted, the upper electrode groove mask pattern units are linearly arranged in parallel along a second direction perpendicular to the first direction on a cross section parallel to the semiconductor substrate, each upper electrode groove mask pattern unit is approximately in a cross shape of a plus sign, the cross point of the projection of each upper electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate of the plus sign is aligned with the center of the projection of the corresponding lower electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate, the projections of the patterns extending along the first direction of the plus sign all fall into the projection of the lower electrode groove mask pattern units, and the projections of the patterns extending along the second direction extend to the outside of the projection of the lower electrode groove mask pattern units.

9. The manufacturing method according to claim 8, characterized in that:

every two adjacent pattern units which are crossed in a plus shape and are on the same line in the second direction are connected; alternatively, all pattern units crossing at a "+" cross on the same line in the second direction are connected to each other.

10. The manufacturing method according to claim 8, characterized in that:

the pattern of the lower electrode groove mask pattern unit, the pattern of the upper electrode groove mask pattern unit extending along the first direction and the pattern of the upper electrode groove mask pattern unit extending along the second direction are rectangular, and the width of the pattern of the upper electrode groove mask pattern unit extending along the first direction is larger than the width of the pattern of the upper electrode groove mask pattern unit extending along the second direction.

11. The manufacturing method according to claim 6, characterized in that:

the etching is carried out according to the patterned photoresist layer and the mask layer; alternatively, the etching is performed only on the basis of a patterned photoresist layer.

12. The manufacturing method according to claim 11, characterized in that:

the patterning is performed by double patterning (double patterning) or multiple patterning (multiple patterning) techniques.

13. A semiconductor device comprising a capacitor structure according to any one of claims 1 to 5 or a capacitor structure produced by the method of manufacture according to any one of claims 6 to 12.

14. An electronic device comprising the semiconductor device according to claim 13.

15. The electronic device of claim 14, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

Images