CN115206902B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN115206902B CN115206902B CN202211133572.8A CN202211133572A CN115206902B CN 115206902 B CN115206902 B CN 115206902B CN 202211133572 A CN202211133572 A CN 202211133572A CN 115206902 B CN115206902 B CN 115206902B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 129
- 230000004888 barrier function Effects 0.000 claims abstract description 76
- 239000003822 epoxy resin Substances 0.000 claims abstract description 71
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 71
- 230000000903 blocking effect Effects 0.000 claims description 103
- 238000003466 welding Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 23
- 238000005476 soldering Methods 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 16
- 229920005989 resin Polymers 0.000 abstract description 15
- 239000011347 resin Substances 0.000 abstract description 15
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000000047 product Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 230000006872 improvement Effects 0.000 description 12
- 239000004593 Epoxy Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002985 plastic film Substances 0.000 description 7
- 229920006255 plastic film Polymers 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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- 230000005496 eutectics Effects 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/46—Filters
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Abstract
本发明揭示了一种芯片封装结构及其制作方法,包括基板、至少一芯片、多个导电结合部和环氧树脂膜,芯片通过导电结合部设置于基板上方;还包括阻挡结构件,设置于导电结合部外侧的基板上表面部分区域,所述阻挡结构件被配置用于阻挡所述环氧树脂膜进入所述阻挡结构件的内侧区域;环氧树脂膜包覆芯片的上表面和侧表面以及阻挡结构件的外侧表面,并沿芯片侧表面和阻挡结构件的外侧表面延伸至基板上表面,环氧树脂膜、芯片、基板和阻挡结构件之间形成空腔。在覆膜工艺中,该阻挡结构件能够有效阻挡环氧树脂膜溢出的树脂材料进入芯片与基板之间的空腔区域,防止污染导电结合部和空腔区域。
The invention discloses a chip packaging structure and a manufacturing method thereof, including a substrate, at least one chip, a plurality of conductive joints and an epoxy resin film, the chip is arranged above the substrate through the conductive joints; and a barrier structure is also included In the partial area of the upper surface of the substrate outside the conductive joint, the barrier structure is configured to prevent the epoxy resin film from entering the inner area of the barrier structure; the epoxy resin film covers the upper surface and the side surface of the chip and the outer surface of the barrier structure, extending along the side surface of the chip and the outer surface of the barrier structure to the upper surface of the substrate, and a cavity is formed between the epoxy resin film, the chip, the substrate and the barrier structure. During the coating process, the barrier structure can effectively prevent the resin material overflowing from the epoxy resin film from entering the cavity area between the chip and the substrate, so as to prevent the conductive junction and the cavity area from being polluted.
Description
技术领域technical field
本发明涉及半导体封装技术领域,尤其涉及一种芯片封装结构及其制作方法。The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof.
背景技术Background technique
如图1所示,为现有的滤波器芯片封装结构,芯片2的功能面通过金属球柱倒装焊于基板1上,环氧树脂膜4整面覆盖于基板1部分上表面和芯片2的非功能面,使得芯片2与基板1以及环氧树脂膜4之间形成空腔。As shown in Figure 1, it is an existing filter chip packaging structure, the functional surface of the
但是,现有封装结构存在以下两个问题:第一,当环氧树脂膜4和基板1表面压合时,环氧树脂膜4中溢出的树脂很容易进入腔体污染球柱和芯片有效区域,降低滤波器产品性能;第二,产品工作中由于封装结构的内外压差,存在侧面环氧树脂膜4被冲掉的风险。However, the existing packaging structure has the following two problems: first, when the
发明内容Contents of the invention
本发明的目的在于提供一种芯片封装结构及其制作方法,以阻挡环氧树脂膜溢出的树脂材料进入芯片与基板之间的空腔区域,防止污染导电结合部和空腔区域。The object of the present invention is to provide a chip packaging structure and its manufacturing method, so as to prevent the resin material overflowing from the epoxy resin film from entering the cavity area between the chip and the substrate, and prevent the conductive junction and the cavity area from being polluted.
为实现上述发明目的之一,本发明一实施方式提供一种芯片封装结构,包括基板、至少一芯片、多个导电结合部和环氧树脂膜,所述基板上表面设置多个焊接区域,所述芯片通过所述导电结合部设置于所述基板上方,所述导电结合部与所述焊接区域对应设置,其中,所述芯片封装结构还包括一阻挡结构件,所述阻挡结构件设置于所述导电结合部外侧的基板上表面部分区域,所述阻挡结构件被配置用于阻挡所述环氧树脂膜进入所述阻挡结构件的内侧区域;In order to achieve one of the objectives of the above invention, an embodiment of the present invention provides a chip packaging structure, including a substrate, at least one chip, a plurality of conductive joints, and an epoxy resin film. The upper surface of the substrate is provided with a plurality of soldering regions. The chip is disposed above the substrate through the conductive joint, and the conductive joint is disposed corresponding to the welding area, wherein the chip packaging structure further includes a blocking structure, and the blocking structure is disposed on the A partial area of the upper surface of the substrate outside the conductive joint, the barrier structure is configured to prevent the epoxy resin film from entering the inner area of the barrier structure;
所述环氧树脂膜包覆所述芯片的上表面和侧表面以及所述阻挡结构件的外侧表面,并沿所述芯片侧表面和所述阻挡结构件的外侧表面延伸至所述基板上表面,所述环氧树脂膜、所述芯片、所述基板和所述阻挡结构件之间形成空腔。The epoxy resin film covers the upper surface and the side surface of the chip and the outer surface of the barrier structure, and extends along the side surface of the chip and the outer surface of the barrier structure to the upper surface of the substrate , a cavity is formed among the epoxy resin film, the chip, the substrate and the barrier structure.
作为本发明一实施方式中的进一步改进,所述阻挡结构件环绕设置于所述导电结合部外侧的基板上表面区域。As a further improvement in an embodiment of the present invention, the barrier structure surrounds the upper surface area of the substrate disposed outside the conductive joint.
作为本发明一实施方式中的进一步改进,所述阻挡结构件的内侧面不超过所述芯片边缘区域。As a further improvement in an embodiment of the present invention, the inner surface of the barrier structure does not exceed the edge area of the chip.
作为本发明一实施方式中的进一步改进,所述阻挡结构件包括阻挡部和引流部,所述阻挡部被配置用于阻挡所述环氧树脂膜进入所述空腔,所述引流部被配置用于朝远离所述导电结合部方向引流所述环氧树脂膜。As a further improvement in an embodiment of the present invention, the blocking structure includes a blocking part and a drainage part, the blocking part is configured to prevent the epoxy resin film from entering the cavity, and the drainage part is configured It is used for draining the epoxy resin film away from the conductive joint.
作为本发明一实施方式中的进一步改进,所述阻挡结构件为L型结构,所述引流部设置于所述基板上表面,所述阻挡部沿所述引流部靠所述导电结合部的一端朝所述基板上方凸起。As a further improvement in one embodiment of the present invention, the blocking structure is an L-shaped structure, the drainage part is arranged on the upper surface of the substrate, and the blocking part is close to one end of the conductive joint along the drainage part. protruding upward from the substrate.
作为本发明一实施方式中的进一步改进,所述基板上表面部分区域向内凹陷形成一凹槽,所述凹槽设置于所述阻挡结构件远离所述导电结合部一侧。As a further improvement in an embodiment of the present invention, a part of the upper surface of the substrate is recessed inward to form a groove, and the groove is disposed on a side of the barrier structure away from the conductive joint.
作为本发明一实施方式中的进一步改进,所述凹槽的内侧面与所述阻挡结构件远离所述导电结合部的一侧面设置处于同一竖直线上。As a further improvement in an embodiment of the present invention, the inner surface of the groove is arranged on the same vertical line as the side of the blocking structure away from the conductive joint.
作为本发明一实施方式中的进一步改进,所述凹槽围绕所述阻挡结构件。As a further improvement in an embodiment of the present invention, the groove surrounds the blocking structure.
作为本发明一实施方式中的进一步改进,所述凹槽底部设置为一台阶结构,朝远离所述阻挡结构件方向上,所述凹槽深度逐渐增加。As a further improvement in one embodiment of the present invention, the bottom of the groove is configured as a stepped structure, and the depth of the groove increases gradually toward a direction away from the blocking structure.
本发明一实施方式还提供一种芯片封装结构的制作方法,包括步骤:One embodiment of the present invention also provides a method for manufacturing a chip packaging structure, including the steps of:
提供一基板,所述基板上表面设置有多个焊接区域,于所述焊接区域外侧的基板上表面部分区域处,设置有阻挡结构件;A substrate is provided, the upper surface of the substrate is provided with a plurality of welding areas, and a blocking structure is provided at a part of the upper surface of the substrate outside the welding areas;
提供至少一芯片,将所述芯片通过导电结合部对应所述焊接区域设置于所述基板上方;providing at least one chip, and disposing the chip above the substrate corresponding to the welding area through a conductive joint;
提供环氧树脂膜,挤压所述环氧树脂膜使其包覆于所述芯片上表面和侧表面以及所述阻挡结构件的外侧表面,并沿所述芯片侧表面和所述阻挡结构件的外侧表面延伸至所述基板上表面,所述环氧树脂膜、所述芯片、所述基板和所述阻挡结构件之间形成空腔。providing an epoxy resin film, extruding the epoxy resin film to cover the upper surface and the side surface of the chip and the outer surface of the barrier structure, and along the side surface of the chip and the barrier structure The outer surface of the outer surface extends to the upper surface of the substrate, and a cavity is formed among the epoxy resin film, the chip, the substrate and the blocking structure.
作为本发明一实施方式中的进一步改进,所述提供一基板,所述基板上表面设置有多个焊接区域,于所述焊接区域外侧的基板上表面部分区域处,设置有阻挡结构件,具体包括:As a further improvement in one embodiment of the present invention, a substrate is provided, the upper surface of the substrate is provided with a plurality of welding areas, and a blocking structure is provided at a part of the upper surface of the substrate outside the welding areas, specifically include:
围绕所述焊接区域的外侧的基板上表面处设置阻挡结构件;A blocking structure is provided on the upper surface of the substrate around the outer side of the welding area;
将所述阻挡结构件与其最近的所述焊接区域间隔至少30μm设置,且所述阻挡结构件的内侧面不超过所述芯片边缘区域设置;The blocking structure is arranged at least 30 μm apart from the nearest welding area, and the inner surface of the blocking structure does not exceed the edge area of the chip;
将所述阻挡结构件的高度不超过所述导电结合部高度的1/2设置。The height of the barrier structure is set not to exceed 1/2 of the height of the conductive joint.
作为本发明一实施方式中的进一步改进,所述提供一基板,所述基板上表面设置有多个焊接区域,于所述焊接区域外侧的基板上表面部分区域处,设置有阻挡结构件,具体还包括:As a further improvement in one embodiment of the present invention, a substrate is provided, the upper surface of the substrate is provided with a plurality of welding areas, and a blocking structure is provided at a part of the upper surface of the substrate outside the welding areas, specifically Also includes:
所述阻挡结构件为L型结构设置,包括阻挡部和引流部,将所述引流部设置于所述基板上表面,将所述阻挡部沿所述引流部靠所述导电结合部的一端朝所述基板上方凸起设置。The blocking structure is set in an L-shaped structure, including a blocking portion and a draining portion, the draining portion is arranged on the upper surface of the substrate, and the blocking portion is moved toward the A protrusion is arranged above the substrate.
作为本发明一实施方式中的进一步改进,在所述提供至少一芯片之前,还包括步骤:As a further improvement in one embodiment of the present invention, before the at least one chip is provided, further steps are included:
于所述阻挡结构件远离所述导电结合部一侧,在所述基板上表面部分区域处向内凹陷形成一凹槽。On the side of the barrier structure away from the conductive joint part, a groove is recessed inwardly at a part of the upper surface of the substrate.
作为本发明一实施方式中的进一步改进,所述于所述阻挡结构件远离所述导电结合部一侧,在所述基板上表面部分区域处向内凹陷形成一凹槽,具体包括:As a further improvement in an embodiment of the present invention, on the side of the barrier structure away from the conductive joint part, a groove is formed inwardly recessed at a partial area of the upper surface of the substrate, which specifically includes:
将所述凹槽围绕所述阻挡结构件设置,并将所述凹槽的内侧面与所述阻挡结构件远离所述导电结合部的一侧面设置处于同一竖直线上;The groove is arranged around the blocking structure, and the inner side of the groove is arranged on the same vertical line as the side of the blocking structure away from the conductive joint;
将所述凹槽底部形成为一台阶结构,朝远离所述阻挡结构件方向上,所述凹槽深度逐渐增加。The bottom of the groove is formed into a stepped structure, and the depth of the groove gradually increases in a direction away from the blocking structure.
本发明的有益效果在于:通过在导电结合部外侧的基板上表面部分区域设置阻挡结构件,并且该阻挡结构件不超过所述芯片边缘区域,在覆膜工艺中,该阻挡结构件能够有效阻挡环氧树脂膜溢出的树脂材料进入芯片与基板之间的空腔区域,防止污染导电结合部和空腔区域。The beneficial effects of the present invention are: by setting a blocking structure on the upper surface of the substrate outside the conductive joint, and the blocking structure does not exceed the edge area of the chip, in the film coating process, the blocking structure can effectively block The resin material overflowed from the epoxy resin film enters the cavity area between the chip and the substrate, preventing contamination of the conductive junction and the cavity area.
附图说明Description of drawings
图1为常用技术中芯片封装结构示意图。FIG. 1 is a schematic diagram of a chip package structure in a common technology.
图2为本发明一实施方式中的一种芯片封装结构的制作方法流程示意图。FIG. 2 is a schematic flowchart of a manufacturing method of a chip packaging structure in an embodiment of the present invention.
图3~7为本发明一实施方式中的对应芯片封装结构制作方法的工艺步骤图。3 to 7 are process steps diagrams of a method for manufacturing a corresponding chip packaging structure in an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚,下面将结合本发明具体实施方式及相应的附图对本发明技术方案进行清楚、完整地描述。显然,所描述的实施方式仅是本发明一部分实施方式,而不是全部的实施方式。基于本发明中的实施方式,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式,都属于本发明保护的范围。In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and corresponding drawings. Apparently, the described embodiments are only some, not all, embodiments of the present invention. Based on the implementation manners in the present invention, all other implementation manners obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.
下面详细描述本发明的实施方式,实施方式的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
为方便说明,本文使用表示空间相对位置的术语来进行描述,例如“上”、“下”、“后”、“前”等,用来描述附图中所示的一个单元或者特征相对于另一个单元或特征的关系。空间相对位置的术语可以包括设备在使用或工作中除了图中所示方位以外的不同方位。例如,如果将图中的装置翻转,则被描述为位于其他单元或特征“下方”或“上方”的单元将位于其他单元或特征“下方”或“上方”。因此,示例性术语“下方”可以囊括下方和上方这两种空间方位。For the convenience of description, terms representing relative positions in space are used herein for description, such as "upper", "lower", "rear", "front", etc., which are used to describe the relative position of one unit or feature shown in the drawings relative to another. A unit or feature relationship. Spatially relative terms may encompass different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
如图7所示,本发明一实施方式提供一种芯片封装结构,包括基板1、至少一芯片2、多个导电结合部3和环氧树脂膜4。As shown in FIG. 7 , an embodiment of the present invention provides a chip packaging structure, including a
基板1具有上表面及与上表面相背的下表面,基板1上表面设置有多个焊接区域11。The
示例性的,在本实施方式中,设置有一块芯片2,芯片2设置于基板1上表面,与基板1电性连接,具体的,芯片2具有设置有焊盘的功能面以及与功能面相对的非功能面,芯片2功能面朝向基板1设置,通过焊盘电性连接于基板1。在本发明其他实施方式中,也可在基板1上表面设置两个或是多个芯片,实现对应于产品的不同要求。Exemplarily, in this embodiment, a
更具体的,芯片2通过导电结合部3设置于基板1上方,导电结合部3与基板1上表面的焊接区域11以及芯片2功能面上的焊盘对应设置。在本实施方式中,导电结合部3为金属球柱,金属球柱可以为锡球、金球共晶焊等。本发明对金属球柱的具体设置高度不作限制,可根据产品的不同要求或后续对于制作形成的空腔高度要求来进行调整。More specifically, the
进一步的,芯片封装结构还包括一阻挡结构件5,阻挡结构件5设置于导电结合部3外侧的基板1上表面部分区域,阻挡结构件5被配置用于阻挡环氧树脂膜4进入阻挡结构件5的内侧区域,即阻挡环氧树脂膜4进入阻挡结构件5靠近导电结合部3一侧区域。Further, the chip packaging structure also includes a
环氧树脂膜4包覆芯片2的上表面和侧表面以及阻挡结构件5的外侧表面,并沿芯片2侧表面和阻挡结构件5的外侧表面延伸至基板1上表面,环氧树脂膜4、芯片2、基板1和阻挡结构件5之间形成空腔6。环氧树脂膜4在高温条件下烘烤后会呈现硬化状态,将芯片2和基板1牢牢粘结在一起,形成空腔6,对芯片2的功能面起到一定的保护作用,但是在环氧树脂膜4和芯片2及基板1压合的过程中,环氧树脂膜4溢出的树脂材料很容易对导电结合部3和空腔6造成污染,所以,本发明中设置的阻挡结构件5就可以很好的阻挡住环氧树脂膜4溢出的树脂材料,防止其对导电结合部3和空腔6造成污染。The
当然,在本发明其他实施方式中,也可选用DAF(Die Attachment Film)膜代替环氧树脂膜4,同样能够将基板1和芯片2固定结合形成空腔6,且其在高温条件下烘烤后呈硬化状态,对封装结构一样能起到固定、保护作用。Of course, in other embodiments of the present invention, a DAF (Die Attachment Film) film can also be used instead of the
具体的,阻挡结构件5环绕设置于导电结合部3外侧的基板1上表面区域,即阻挡结构件5绕导电结合部3外侧围成一方形或环形结构,或是围设形成其他形状的结构,本发明在此不作限制,只需保证阻挡结构件5设置的位置位于导电结合部3的外侧,且不超过芯片2边缘区域即可。Specifically, the
更具体的,阻挡结构件5的内侧面,即阻挡结构件5朝导电结合部3的一侧面不超过芯片2边缘区域设置,进一步降低环氧树脂膜4进入空腔6的可能性。同时考虑到实际贴装芯片2的机器精度,阻挡结构件5与其最近的导电结合部3之间至少间隔30μm,防止封装结构制作工艺中机器在贴装芯片2时撞击到阻挡结构件5,对芯片2造成损伤。More specifically, the inner side of the
在本发明的最优实施方式中,阻挡结构件5的上表面与芯片2的下表面接触,能够完全阻挡后续工艺中环氧树脂膜4溢出的树脂材料进入到芯片2和基板1之间的空腔区域。但是考虑到在实际制作工艺中,比如导电结合部3在回流焊等工艺过程中,其会呈现融化状态,很难保证最终制作形成的产品中芯片2下表面和基板1上表面之间的高度差稳定,即很难确定实际产品制作中阻挡结构件5的具体高度。若阻挡结构件5的高度设置过高,当回流焊工艺中导电结合部3融化致使芯片2高度降低,则阻挡结构件5很容易损坏芯片2的功能面,所以在本发明具体实施方式中,将阻挡结构件5的高度不超过导电结合部3回流焊成型前高度的1/2设置。同时,阻挡结构件5的高度也不能设置过低,若阻挡结构件5的高度设置过低,则很难保证阻挡结构件5是否能够有效阻挡环氧树脂膜4溢出的树脂材料进入芯片2和基板1之间的空腔区域。本发明对阻挡结构件5高度的具体设置值不作限制,只需保证后续工艺中阻挡结构件5的上表面不会对芯片2的功能面造成破坏的同时,又能起到有效阻挡环氧树脂膜4溢出的树脂材料的效果即可。In the best embodiment of the present invention, the upper surface of the blocking
具体的,阻挡结构件5包括阻挡部51和引流部52,阻挡部51被配置用于阻挡环氧树脂膜4进入空腔6,引流部52被配置用于朝远离导电结合部3的方向引流环氧树脂膜4。Specifically, the blocking
阻挡结构件5具体为一L型结构,引流部52设置于基板1上表面,阻挡部51沿引流部52靠导电结合部3的一端朝基板1上方凸起,阻挡部51在靠近导电结合部3的一侧面不超过芯片2边缘区域设置。具体的,引流部52远离导电结合部3的一侧面与芯片2侧表面对齐设置,阻挡部51的凸起高度满足上述对于阻挡结构件5的具体高度设置要求即可,对于阻挡部51和引流部52的其他尺寸设置,本发明在此不作限制,可根据实际产品设计需求进行调整。当然,在本实施方式中,环氧树脂膜4包覆阻挡部51远离导电结合部3的一侧面,并沿该侧面延伸至引流部52的上表面及基板1的上表面。The blocking
优选的,阻挡结构件5的制作材料为油墨,制作成本较低。当然,在本发明其他实施方式中,阻挡结构件5的制作材料也可以为铜或其他耐高温的材料。Preferably, the blocking
进一步的,基板1上表面部分区域向内凹陷形成一凹槽12,凹槽12设置于阻挡结构件5远离导电结合部3一侧,具体的,凹槽12设置于引流部52远离导电结合部3一侧的基板内,环氧树脂膜4通过引流部52引流可延伸填充至凹槽12内,增强环氧树脂膜4与基板1之间的结合力,提升产品性能。凹槽12的具体形状和尺寸,本发明对此不作限制,可根据实际需求设计。Further, part of the upper surface of the
在本发明具体实施方式中,凹槽12的内侧面与阻挡结构件5远离导电结合部3的一侧面设置处于同一竖直线上,即凹槽12的内侧面与引流部52远离导电结合部3的一侧面处于同一竖直线上,具体的,凹槽12的内侧面和引流部52远离导电结合部3的一侧面与芯片2的侧表面对齐设置,环氧树脂膜4通过引流部52上表面直接延伸填充至凹槽12内部。In a specific embodiment of the present invention, the inner side of the
更具体的,凹槽12围绕阻挡结构件5形成一方形或环形结构,进一步增强环氧塑封膜4与基板1之间的结合力。本发明对凹槽12围设形成的具体形状结构和尺寸不作限制,只需保证阻挡结构件5围成的区域完全落在凹槽12围成的区域内即可。More specifically, the
为进一步增强环氧塑封膜4与基板1之间的结合力,凹槽12底部设置为一台阶结构,朝远离阻挡结构件5方向上,凹槽12的深度逐渐增加,当然,本实施方式中对台阶结构的台阶数不作具体要求,台阶数越多,环氧树脂膜4与凹槽12内表面的摩擦力越大,则环氧树脂膜4与基板1的结合力越大,所以台阶结构的台阶数可根据实际需求进行设计调整。当然,在本发明其他实施方式中,凹槽12底部也可以为波浪形或是其他形状,或者朝远离阻挡结构件5方向上,凹槽12的深度逐渐减小。凡是在此结构基础上对凹槽12内结构和尺寸上的变化,均在本发明的保护范围之内。In order to further enhance the bonding force between the
如图2所示,本发明一实施方式还提供一种芯片封装结构的制作方法,包括步骤:As shown in FIG. 2, an embodiment of the present invention also provides a method for manufacturing a chip packaging structure, including steps:
S1:提供一基板,基板上表面设置有多个焊接区域,于焊接区域外侧的基板上表面部分区域处,设置有阻挡结构件。S1: A substrate is provided, the upper surface of the substrate is provided with a plurality of welding areas, and a blocking structure is arranged at a part of the upper surface of the substrate outside the welding areas.
S2:提供至少一芯片,将芯片通过导电结合部对应所述焊接区域设置于基板上方。S2: providing at least one chip, and disposing the chip on the substrate corresponding to the welding area through the conductive joint.
S3:提供环氧树脂膜,挤压环氧树脂膜使其包覆于芯片上表面和侧表面以及阻挡结构件的外侧表面,并沿芯片侧表面和阻挡结构件的外侧表面延伸至基板上表面,环氧树脂膜、芯片、基板和阻挡结构件之间形成空腔。S3: Provide an epoxy resin film, extrude the epoxy resin film to cover the upper surface and side surface of the chip and the outer surface of the barrier structure, and extend along the side surface of the chip and the outer surface of the barrier structure to the upper surface of the substrate , A cavity is formed between the epoxy resin film, the chip, the substrate, and the barrier structure.
如图3,对应于在步骤S1中,提供一基板1,基板1上表面设置有多个焊接区域11,于焊接区域11外侧的基板1上表面部分区域处,设置有阻挡结构件5,具体包括:As shown in Figure 3, corresponding to step S1, a
阻挡结构件5的具体设置要求与后续贴装的芯片不同、制作产品工艺不同有关。根据后续产品所需求的芯片2的具体尺寸来设置阻挡结构件5位于基板1上表面的具体位置,具体的,阻挡结构件5设置于焊接区域11外侧的基板1上表面部分区域处,且阻挡结构件5的内侧面不超过后续需要贴装的芯片2的边缘区域。The specific setting requirements of the
具体的,阻挡结构件5环绕设置于焊接区域11外侧的基板1上表面区域,即阻挡结构件5绕焊接区域11外侧围成一方形或环形结构,或是围设形成其他形状的结构,本发明在此不作限制,只需保证阻挡结构件5设置的位置位于焊接区域11的外侧,且阻挡结构件5的内侧面不超过后续贴装的芯片2边缘区域即可。Specifically, the blocking
更具体的,考虑到后续制作工艺中实际贴装芯片2的机器精度,阻挡结构件5与其最近的焊接区域11之间至少间隔30μm,防止封装结构制作工艺中机器在贴装芯片2时撞击到阻挡结构件5,对芯片2造成损伤。More specifically, considering the machine accuracy of actually mounting the
在本发明的最优实施方式中,设置的阻挡结构件5的上表面与芯片2的下表面接触,能够完全阻挡后续工艺中环氧树脂膜4溢出的树脂材料进入到芯片2和基板1之间的空腔区域。但是考虑到在实际制作工艺中,比如在步骤S2中设置的导电结合部3在回流焊等工艺过程中,其会呈现融化状态,很难保证最终制作形成的产品中芯片2下表面和基板1上表面之间的高度差稳定,即很难确定实际产品制作中阻挡结构件5的具体高度。若阻挡结构件5的高度设置过高,当回流焊工艺中导电结合部3融化致使芯片2高度降低,则阻挡结构件5很容易损坏芯片2的功能面,所以在本发明具体实施方式中,将阻挡结构件5的高度不超过导电结合部3回流焊成型前高度的1/2设置。同时,阻挡结构件5的高度也不能设置过低,若阻挡结构件5的高度设置过低,则很难保证阻挡结构件5是否能够有效阻挡环氧树脂膜4溢出的树脂材料进入芯片2和基板1之间的空腔区域。本发明对阻挡结构件5高度的具体设置值不作限制,只需保证后续工艺中阻挡结构件5的上表面不会对芯片2的功能面造成破坏的同时,又能起到有效阻挡环氧树脂膜4溢出的树脂材料的效果即可。In the best embodiment of the present invention, the upper surface of the
具体的,继续参照图3,设置的阻挡结构件5包括阻挡部51和引流部52,阻挡部51被配置用于阻挡步骤S3中的环氧树脂膜4进入空腔6,引流部52被配置用于朝远离导电结合部3的方向引流步骤S3中的环氧树脂膜4。Specifically, continue referring to FIG. 3 , the
阻挡结构件5具体为一L型结构,引流部52设置于基板1上表面,阻挡部51沿引流部52靠导电结合部3的一端朝基板1上方凸起,具体的,将引流部52远离导电结合部3的一侧面与待贴装的芯片2侧表面对齐设置,阻挡部51的凸起高度满足上述对于阻挡结构件5的具体高度设置要求即可,对于阻挡部51和引流部52的其他尺寸设置,本发明在此不作限制,可根据实际产品设计需求进行调整。当然,在本实施方式中,在步骤S3中,环氧树脂膜4包覆阻挡部51远离导电结合部3的一侧面,并沿该侧面延伸至引流部52的上表面及基板1的上表面。The blocking
优选的,阻挡结构件5的制作材料为油墨,制作成本较低。当然,在本发明其他实施方式中,阻挡结构件5的制作材料也可以为铜或其他耐高温的材料。Preferably, the blocking
进一步的,在步骤S2之前,还包括步骤:于阻挡结构件5远离导电结合部3一侧,在基板1上表面部分区域处向内凹陷形成一凹槽12。Further, before the step S2 , a step is further included: forming a
如图4所示,具体的,于引流部52远离导电结合部3一侧的基板上表面部分区域处,利用激光或是掩膜等工艺形成凹槽12,在步骤S3中环氧树脂膜4通过引流部52引流可延伸填充至凹槽12内,增强环氧树脂膜4与基板1之间的结合力,提升产品性能。凹槽12具体形成的形状和尺寸,本发明对此不作限制,可根据实际需求设计。As shown in FIG. 4 , specifically,
将凹槽12围绕阻挡结构件5形成一方形或环形结构,并将凹槽12的内侧面与阻挡结构件5远离所述导电结合部3的一侧面设置处于同一竖直线上,即凹槽12的内侧面与引流部52远离导电结合部3的一侧面处于同一竖直线上,具体的,将凹槽12的内侧面和引流部52远离导电结合部3的一侧面与待贴装的芯片2的侧表面对齐设置,步骤S3中环氧树脂膜4通过引流部52上表面直接延伸填充至凹槽12内部。本发明对凹槽12围设形成的具体形状结构和尺寸不作限制,只需保证阻挡结构件5围成的区域完全落在凹槽12围成的区域内即可。The
为进一步增强环氧塑封膜4与基板1之间的结合力,将凹槽12底部制作形成为一台阶结构,朝远离阻挡结构件5方向上,凹槽12的深度逐渐增加,当然,本实施方式中对形成的台阶结构的台阶数不作具体要求,台阶数越多,环氧树脂膜4与凹槽12内表面的摩擦力越大,则环氧树脂膜4与基板1的结合力越大,所以台阶结构的台阶数可根据实际需求及加工精度进行设计调整。当然,在本发明其他实施方式中,凹槽12底部也可以为波浪形或是其他形状,或者朝远离阻挡结构件5方向上,凹槽12的深度逐渐减小,可根据实际制作工艺和加工精度具体调整。In order to further enhance the bonding force between the
如图5所示,为对应于步骤S2中的制作工艺步骤,在芯片2的功能面设置相对应的导电结合部3,在本实施方式中,导电结合部3设置为金属球柱,金属球柱可以为锡球、金球共晶焊等。本发明对金属球柱的具体设置高度不作限制,可根据产品的不同要求或后续对于制作形成的空腔高度要求来进行调整。As shown in Figure 5, in order to correspond to the manufacturing process steps in step S2, the corresponding
进一步的,将芯片2的功能面朝向基板1上表面方向,将芯片2功能面上的导电结合部3对应焊接至基板1上表面的焊接区域11处,与基板1之间形成电性连接。Further, the functional surface of the
进一步的,将芯片2贴装至基板1上表面之后进行回流焊工艺,由于导电结合部3在回流焊工艺中会处于融化状态,导致原先形成的空腔6的空腔高度减小,阻挡结构件5的上表面与芯片2的下表面距离减小,如图6所示。在本实施方式中,将阻挡结构件5的高度不超过导电结合部3回流焊成型前高度的1/2设置,所以在回流焊工艺后,阻挡结构件5的上表面和芯片2的下表面之间还存在一定空隙,保证阻挡结构件5不会对芯片2的功能面造成伤害的同时,又能起到有效阻挡后续塑封工艺中环氧树脂膜4溢出的树脂材料进入阻挡结构件5的内侧面即可。Further, after the
如图7所示,对应于步骤S4中制作工艺步骤,挤压环氧树脂膜4使其包覆芯片2的上表面和侧表面以及阻挡结构件5的外侧表面,并沿芯片2侧表面和阻挡结构件5的外侧表面延伸至基板1上表面,环氧树脂膜4、芯片2、基板1和阻挡结构件5之间形成空腔6。具体的,挤压环氧树脂膜4使其包覆阻挡部51远离导电结合部3的一侧面,并沿该侧面延伸至引流部52的上表面、凹槽12内以及基板1的上表面。As shown in Figure 7, corresponding to the manufacturing process step in step S4, the
在本发明其他实施方式中,也可选用DAF(Die Attachment Film)膜代替环氧树脂膜4,同样能够将基板1和芯片2固定结合形成空腔6,且其在高温条件下烘烤后呈硬化状态,对封装结构一样能起到固定、保护作用,最终制作形成的封装产品结构能够有效阻挡环氧塑封膜4中溢出的树脂材料进入芯片2与基板1之间的空腔区域,防止污染导电结合部3和芯片2的功能面区域。In other embodiments of the present invention, a DAF (Die Attachment Film) film can also be used instead of the
综上所述,本发明通过在导电结合部外侧的基板上表面部分区域设置阻挡结构件,并且该阻挡结构件不超过所述芯片边缘区域,在覆膜工艺中,该阻挡结构件能够有效阻挡环氧树脂膜溢出的树脂材料进入芯片与基板之间的空腔区域,防止污染导电结合部和空腔区域。另外,在基板上表面侧朝内设置凹槽,使得环氧塑封膜能够延伸填充至凹槽内,增强环氧塑封膜与基板之间的结合力,降低环氧塑封膜脱落的风险,提升产品性能。To sum up, in the present invention, a blocking structure is provided on the upper surface of the substrate outside the conductive joint, and the blocking structure does not exceed the edge area of the chip. In the coating process, the blocking structure can effectively block The resin material overflowed from the epoxy resin film enters the cavity area between the chip and the substrate, preventing contamination of the conductive junction and the cavity area. In addition, a groove is provided on the upper surface of the substrate facing inward, so that the epoxy plastic film can be extended and filled into the groove, the bonding force between the epoxy plastic film and the substrate is enhanced, the risk of the epoxy plastic film falling off is reduced, and the product is improved. performance.
应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施方式中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。It should be understood that although this description is described according to implementation modes, not each implementation mode only contains an independent technical solution, and this description in the description is only for clarity, and those skilled in the art should take the description as a whole, and each The technical solutions in the embodiments can also be properly combined to form other embodiments that can be understood by those skilled in the art.
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明,它们并非用以限制本发明的保护范围,凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。The series of detailed descriptions listed above are only specific descriptions for feasible implementations of the present invention, and they are not intended to limit the protection scope of the present invention. Any equivalent implementation or implementation that does not depart from the technical spirit of the present invention All changes should be included within the protection scope of the present invention.
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