CN115204088A - Chip thermal performance optimization method and device based on current density and storage medium - Google Patents
Chip thermal performance optimization method and device based on current density and storage medium Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000003860 storage Methods 0.000 title claims abstract description 18
- 238000005457 optimization Methods 0.000 title claims description 14
- 238000004088 simulation Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims description 18
- 238000009826 distribution Methods 0.000 claims description 14
- 238000004590 computer program Methods 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 238000004220 aggregation Methods 0.000 description 6
- 230000002776 aggregation Effects 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
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- 230000003287 optical effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/373—Design optimisation
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- G—PHYSICS
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Abstract
The application discloses a method and a device for optimizing the thermal performance of a chip based on current density and a storage medium. The method for optimizing the thermal performance of the chip based on the current density comprises the following steps: establishing an initial structure model according to a chip configured on a circuit board, and performing a thermal simulation program on the initial structure model; when the thermal simulation result of the initial structure model does not meet a first preset condition, acquiring information of a power supply circuit of the chip; carrying out a current density simulation program on the initial structure model, and identifying whether a current concentration area exists on the power supply circuit or not based on the information of the power supply circuit and a second preset condition; when the current concentration area exists, modifying the initial structure model, and repeatedly executing the steps until the current concentration area does not exist on the power supply circuit is identified; outputting an optimized structure model after identifying that no current concentration area exists on the power supply circuit; and carrying out thermal simulation optimization program on the optimized structure model, so that the thermal simulation result of the optimized structure model meets a first preset condition.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a method and an apparatus for optimizing thermal performance of a chip based on current density, and a storage medium.
Background
In response to the light, thin, short, small and multifunctional requirements of electronic products, the chip has the characteristics of small volume and high integration density. However, due to the characteristics of small size and high integration density, the chip may not easily dissipate heat generated during operation, which may cause the chip to be overheated and fail. Therefore, it is becoming increasingly important to optimize the design of chips to improve their thermal performance.
The existing method for optimizing the thermal performance of the chip uses thermal simulation software to perform a thermal simulation optimization program, but the setting of substrate parameters during gridding in the thermal simulation optimization program is normalized, so that the distribution of thermal aggregation points on a single power supply circuit of the chip cannot be seen, and the internal structure of the chip cannot be improved aiming at the thermal aggregation points, which easily causes damage to the power supply circuit of the chip.
Disclosure of Invention
The main purpose of the present application is to provide a method and an apparatus for optimizing a thermal performance of a chip based on current density, and a storage medium, which solve the problem that a thermal aggregation point on a single power supply circuit of the chip cannot be located in the existing method for optimizing the thermal performance of the chip, and there is no way to improve the internal structure of the chip with respect to the thermal aggregation point.
In order to achieve the above object, the present application is realized by:
in a first aspect, a method for optimizing thermal performance of a chip based on current density is provided, which includes the following steps: step a, establishing an initial structure model according to a chip configured on a circuit board, and performing a thermal simulation program on the initial structure model to obtain a thermal simulation result of the initial structure model; step b, when the thermal simulation result of the initial structure model does not meet a first preset condition, acquiring information of a power supply circuit of the chip; c, carrying out a current density simulation program on the initial structure model, and identifying whether a current concentration area exists on the power supply circuit or not based on the information of the power supply circuit and a second preset condition; d, when the current concentration area exists on the power supply circuit, modifying the initial structure model based on the current concentration area, and repeatedly executing the step c until the current concentration area does not exist on the power supply circuit; step e, outputting an optimized structure model after identifying that no current concentration area exists on the power supply circuit; and f, carrying out thermal simulation optimization program on the optimized structure model to enable the thermal simulation result of the optimized structure model to meet a first preset condition.
In a second aspect, there is provided an apparatus for optimizing thermal performance of a chip based on current density, comprising: the present invention relates to a chip thermal performance optimization method based on current density, and more particularly, to a memory, a processor, and a computer program stored on the memory, the computer program being configured to implement the current density based chip thermal performance optimization method of the embodiments of the present application when invoked by the processor.
In a third aspect, a computer-readable storage medium is provided, in which a computer program is stored, where the computer program is configured to implement the current density based chip thermal performance optimization method of the embodiments of the present application when the computer program is called by a processor.
In the embodiment of the application, the power supply circuit of the chip can be analyzed by utilizing current density simulation, the current concentration area has the characteristic of relatively concentrated heat, the heat concentration point on a single power supply circuit is positioned, the initial structure model is modified by improving the current density mode, and finally the heat dissipation capacity of the chip is increased by combining the thermal simulation optimization mode.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of one embodiment of a method for thermal performance optimization of a chip based on current density according to the present application; and
fig. 2 is a block diagram of an embodiment of a current density based chip thermal performance optimization apparatus according to the present application.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar components or method flows.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operations, components, and/or components, but do not preclude the presence or addition of further features, values, method steps, operations, components, and/or groups thereof.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Please refer to fig. 1, which is a flowchart illustrating a method for optimizing thermal performance of a chip based on current density according to an embodiment of the present disclosure. As shown in fig. 1, the method for optimizing the thermal performance of the chip based on the current density comprises the following steps: establishing an initial structure model according to a chip configured on a circuit board, and performing a thermal simulation program on the initial structure model to obtain a thermal simulation result of the initial structure model (step 110); when the thermal simulation result of the initial structure model does not meet a first preset condition, acquiring information of a power supply circuit of the chip (step 120); performing a current density simulation program on the initial structure model, and identifying whether a current concentration area exists on the power supply circuit based on the information of the power supply circuit and a second preset condition (step 130); when the current concentration area on the power supply circuit is identified, modifying the initial structure model based on the current concentration area, and repeatedly executing the step 130 until the current concentration area on the power supply circuit is identified (step 140); after identifying that no current concentration area exists on the power supply circuit, outputting an optimized structure model (step 150); and performing a thermal simulation optimization program on the optimized structure model to enable a thermal simulation result of the optimized structure model to meet a first preset condition (step 160).
In this embodiment, the thermal simulation program in step 110 may use thermal simulation software, such as: and (4) carrying out thermal simulation analysis on the initial structure model by using FlothERM software or ICEPAK software to obtain a thermal resistance value and thermal distribution data (namely a thermal simulation result).
In an embodiment, the step 110 of establishing an initial structure model according to a chip configured on a circuit board and performing a thermal simulation procedure on the initial structure model includes: establishing a chip model according to the packaging structure and the substrate structure of the chip; establishing a circuit board model according to a substrate structure of the circuit board; integrating the chip model and the circuit board model to establish an initial structure model; and setting the thermal conductivity and the heat exchange conditions of various materials of the chip and the circuit board so as to perform a thermal simulation program on the initial structure model.
Specifically, the establishing of the chip model according to the packaging structure and the substrate structure of the chip includes: obtaining parameters of a packaging structure of a chip and parameters of a substrate structure, and establishing a chip model according to the parameters, wherein the parameters of the packaging structure of the chip include but are not limited to: the geometry (e.g., thickness) and geometry of each structure, and the parameters of the substrate structure of the chip include, but are not limited to: the geometric dimension and the geometric shape of each layer of the substrate structure and the copper coating proportion.
The establishing of the circuit board model according to the substrate structure of the circuit board comprises the following steps: obtaining parameters of a substrate structure of a circuit board, and establishing a circuit board model according to the parameters, wherein the parameters of the substrate structure of the circuit board include but are not limited to: the geometric dimension and the geometric shape of each layer of the substrate structure and the copper coating proportion. The substrate structure of the circuit board may be, but is not limited to, a standard four-layer 2S2P circuit board.
The integrating of the chip model and the circuit board model to establish an initial structure model includes: combining the chip model and the circuit board model based on the circuit layout of the circuit board and the chip to establish an initial structure model.
The heat exchange conditions may be, but are not limited to: the radiation mode is used for heat dissipation, the natural convection mode is used for heat dissipation, or the forced convection mode is used for heat dissipation.
In this embodiment, the first preset condition in step 120 may be, but is not limited to, a temperature condition that the chip can normally operate (i.e., a temperature range that the chip can normally operate), and the information of the power supply circuit may include, but is not limited to, a path of the power supply circuit, a name of a power supply, and a voltage value and a current value correspondingly provided by the power supply circuit. In an embodiment, when the thermal distribution data of the thermal simulation result does not meet the temperature condition that the chip can normally operate (i.e. part of the thermal distribution data exceeds the temperature range that the chip can normally operate), the information of the power supply circuit of the chip is acquired.
Further, the number of power supply circuits acquired may be, but is not limited to, one; when the number of the obtained power supply circuits can be multiple, the subsequent steps 130 to 140 can be performed for each power supply circuit until the optimal structure model is output after the current concentration area does not exist on each power supply circuit is identified. In the present embodiment, a single power supply circuit is obtained for the following description.
In an embodiment, the acquiring information of the power supply circuit of the chip in step 120 includes: and acquiring a power supply with a current value larger than a preset current value, which is provided on the chip, so as to acquire information of the power supply circuit, wherein the preset current value can be adjusted according to actual requirements. In other words, the power supply circuit that acquires the relevant information provides a large current output to the power supply circuit having a large current, i.e., the power supply of the acquired power supply circuit. When the number of the power supplies with the current values larger than the preset current value provided on the chip is multiple, only the power supply with the maximum current value can be obtained, and then the information of the corresponding power supply circuit is obtained.
In this embodiment, the second predetermined condition in step 130 can be, but is not limited to, a predetermined current density value. Specifically, the current density simulation program described in step 130 may employ current density simulation software, such as: ANSYS software, performing current density simulation analysis on the initial structure model to obtain current density distribution data (namely current density simulation results) on the power supply circuit; then, it is determined whether a part of the current density distribution data is larger than the preset current density value based on the power supply circuit obtained in step 120, and when a part of the current density distribution data is larger than the preset current density value, it represents that a current concentrated region exists on the power supply circuit. The number of the current concentration regions may be, but is not limited to, one, that is, the number of the current concentration regions may be plural.
In one embodiment, step 130 includes: and after the current density simulation is carried out on the initial structure model, whether a current concentrated region exists on the power supply circuit is identified layer by layer on the initial structure model based on the path of the power supply circuit and a second preset condition. Specifically, after the current density simulation software is used to perform the current density simulation on the initial structure model, the current density distribution data of each layer of substrate in the substrate structures of the chip and the circuit board can be obtained, so that whether the current density distribution data on the power supply circuit path is greater than the preset current density value (i.e., the second preset condition) can be identified layer by layer on the initial structure model based on the path of the power supply circuit, and whether a current concentration area exists on the power supply circuit path is further judged.
In another embodiment, step 130 includes: carrying out current density simulation on the initial structure model to obtain a current density distribution map; and identifying whether a current concentration area exists in the current density distribution diagram based on the path of the power supply circuit and a second preset condition. Specifically, after the current density simulation is performed on the initial structure model by using the current density simulation software, the current density distribution map of each layer of substrate in the substrate structures of the chip and the circuit board can be obtained, so that the current density distribution map can be analyzed and judged based on the path of the power supply circuit and a second preset condition, and whether a current concentration area exists on the path of the power supply circuit is further judged.
In this embodiment, step 140 is to optimize the initial structure model such that there is no current concentration area on the power supply circuit. When a plurality of current concentration regions exist on the power supply circuit, the initial structure model needs to be modified based on each current concentration region, and step 130 is repeatedly executed until no current concentration region exists on the power supply circuit.
In one embodiment, the step 140 of modifying the initial structural model based on the current concentration region includes: and modifying the part of the initial structure model corresponding to the current concentration area in a manner of increasing the copper coating area and/or increasing the through hole. Specifically, the circuit corresponding to the current concentration area is modified by increasing the copper plating area and/or increasing the via hole (modifying the circuit can represent modifying the initial structure model), so as to reduce the current density at the circuit, and further eliminate the current concentration area.
In this embodiment, step 150 is to output an optimized initial structure model (i.e. an optimized structure model) by eliminating all current concentration regions.
In this embodiment, step 160 is performed by using thermal simulation software, such as: and the FloTHERM software or the ICEPAK software is used for carrying out thermal simulation analysis on the optimized structure model to obtain a corresponding thermal simulation result, if the thermal simulation result does not meet the first preset condition, the optimized structure model can be modified, and the thermal simulation analysis is repeatedly carried out until the thermal simulation result of the optimized structure model meets the first preset condition. The thermal simulation optimization program is obtained by modifying the optimized structure model by thermal simulation analysis until the thermal simulation result meets a first preset condition.
Through the steps 110 to 160, the power supply circuit of the chip can be analyzed based on the current density simulation, the current concentration area has the characteristic of relatively concentrated heat, the heat concentration point (i.e., the current concentration area) on a single power supply circuit is positioned, the initial structure model is modified through the current density improving mode (such as increasing the copper coating area and/or increasing the through holes), and finally the final optimized structure model is obtained by combining the thermal simulation optimizing mode, so that the heat dissipation capacity of the chip is increased.
Please refer to fig. 2, which is a block diagram illustrating an exemplary embodiment of a device for optimizing thermal performance of a chip based on current density according to the present application. As shown in fig. 2, the apparatus 200 for optimizing the thermal performance of a chip based on current density includes: the memory 210, the processor 220, and the computer program 230 stored on the memory 210, the processor 220 is connected to the memory 210, and the computer program 230 is configured to implement the method for optimizing the thermal performance of the chip based on current density as shown in fig. 1 when being called by the processor 220, and can achieve the same technical effect, and therefore, for avoiding repetition, the description is omitted here.
In addition to the method for optimizing the thermal performance of the chip based on the current density shown in fig. 1 may be implemented by the apparatus 200 for optimizing the thermal performance of the chip based on the current density shown in fig. 2, in an embodiment, the method for optimizing the thermal performance of the chip based on the current density shown in fig. 1 may be implemented by a computer program product, i.e., a computer-readable storage medium. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing the method for optimizing thermal performance of a chip based on current density shown in fig. 1, where the computer program is configured to implement the method for optimizing thermal performance of a chip based on current density shown in fig. 1 when being invoked by a processor, and achieve the same technical effects, and therefore, in order to avoid repetition, the details are not repeated here. The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing.
The method, the device and the storage medium for optimizing the thermal performance of the chip based on the current density can locate the phenomenon of heat concentration on a single power supply circuit of the chip by combining the characteristics of current density simulation and thermal simulation analysis and the characteristic that a current density dense area is a heat concentration point, and modify the circuit structure of the current density dense area to improve the current density so as to increase the heat dissipation capacity of the chip. Therefore, the problem that in the prior art, the thermal performance of the chip is improved only in a thermal simulation optimization mode, and the thermal aggregation point on the single power supply circuit of the chip cannot be located, so that the internal structure of the chip cannot be improved aiming at the thermal aggregation point is solved.
In general, the various example embodiments of this application may be implemented in hardware or special purpose circuits, software, firmware, logic or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of embodiments of the application may be illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
Although the above-described elements are included in the drawings of the present application, it is not excluded that more additional elements may be used to achieve better technical results without departing from the spirit of the invention.
While the invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. Rather, this invention encompasses modifications and similar arrangements as would be apparent to one skilled in the art. The scope of the claims is, therefore, to be construed in the broadest possible manner to cover all such modifications and similar arrangements.
Claims (8)
1. A method for optimizing the thermal performance of a chip based on current density is characterized by comprising the following steps:
step a, establishing an initial structure model according to a chip configured on a circuit board, and performing a thermal simulation program on the initial structure model to obtain a thermal simulation result of the initial structure model;
b, when the thermal simulation result of the initial structure model does not meet a first preset condition, acquiring information of a power supply circuit of the chip;
c, performing a current density simulation program on the initial structure model, and identifying whether a current concentration area exists on the power supply circuit based on the information of the power supply circuit and a second preset condition;
d, when the current concentration area exists on the power supply circuit, modifying the initial structure model based on the current concentration area, and repeatedly executing the step c until the current concentration area does not exist on the power supply circuit;
step e, outputting an optimized structure model after recognizing that the current concentration area does not exist on the power supply circuit; and
and f, carrying out thermal simulation optimization program on the optimized structure model to enable the thermal simulation result of the optimized structure model to meet the first preset condition.
2. The method for current density-based chip thermal performance optimization of claim 1, wherein said modifying said initial structural model based on said current concentration region in step d comprises:
modifying the portion of the initial structural model corresponding to the current concentration area in a manner that increases the copper plating area and/or increases vias.
3. The method for optimizing thermal performance of a chip based on current density according to claim 1, wherein said obtaining information of a power supply circuit of said chip in step b comprises:
and acquiring the power supply with the current value provided on the chip larger than a preset current value so as to acquire the information of the power supply circuit.
4. The method for current density based chip thermal performance optimization of claim 1, wherein step c comprises:
and after the current density simulation is carried out on the initial structure model, identifying whether the current concentration area exists on the power supply circuit layer by layer on the initial structure model based on the path of the power supply circuit and the second preset condition.
5. The method for current density based chip thermal performance optimization of claim 1, wherein step c comprises:
carrying out current density simulation on the initial structure model to obtain a current density distribution map; and
identifying whether the current concentration region exists in the current density profile based on the path of the power supply circuit and the second preset condition.
6. The method for thermal performance optimization of a current density-based chip according to claim 1, wherein the step a of building an initial structural model based on a chip disposed on a circuit board and performing a thermal simulation procedure on the initial structural model comprises:
establishing a chip model according to the packaging structure and the substrate structure of the chip;
establishing a circuit board model according to the substrate structure of the circuit board;
integrating the chip model and the circuit board model to establish the initial structure model; and
and setting the thermal conductivity and the heat exchange condition of various materials of the chip and the circuit board so as to perform the thermal simulation program on the initial structure model.
7. An apparatus for optimizing thermal performance of a chip based on current density, comprising: a memory, a processor and a computer program stored on the memory, the computer program being configured to implement the current density based chip thermal performance optimization method of any one of claims 1 to 6 when invoked by the processor.
8. A computer-readable storage medium, characterized in that it stores a computer program configured to implement the current density based chip thermal performance optimization method according to any one of claims 1 to 6 when invoked by a processor.
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| CN202110386614.8A CN115204088A (en) | 2021-04-12 | 2021-04-12 | Chip thermal performance optimization method and device based on current density and storage medium |
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