CN115202116A - Array substrate, display device and driving circuit - Google Patents
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- 239000004973 liquid crystal related substance Substances 0.000 description 8
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The application discloses an array substrate, a display device and a driving circuit, wherein the array substrate comprises a substrate, a pixel electrode layer, a first insulating layer, a plurality of data lines, a second insulating layer, a common electrode layer and a plurality of shielding layers, wherein the pixel electrode layer is arranged on the substrate; the first insulating layer is arranged on the substrate and covers the pixel electrode layer; the data line is arranged on the first insulating layer; the second insulating layer is arranged on the first insulating layer and covers the data line; the common electrode layer is arranged on the second insulating layer and comprises a common shielding electrode layer; the shielding layers are arranged in the second insulating layer and located between the common shielding electrode layer and the data lines, and one shielding layer is arranged corresponding to one data line; the voltage signal of the shielding layer is a direct current signal, the voltage value of the shielding layer is greater than the absolute value of the voltage signal of the data line, and the problem that the display panel is prone to have poor phenomena such as horizontal crosstalk or uneven brightness due to voltage change of the data line is solved.
Description
Technical Field
The application relates to the technical field of display panels, in particular to an array substrate, a display device and a driving circuit.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and the like, and are widely used. Such as: liquid crystal televisions, mobile phones, personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.
The conventional liquid crystal panel has a working principle that driving voltages are applied to a pixel electrode and a common electrode to control rotation of liquid crystal molecules of a liquid crystal layer, light of a backlight module is refracted out to generate a picture, a plurality of Data lines (Data) are arranged on an array substrate, voltage change on the Data lines can affect voltage of the common electrode above the Data lines, and voltage of the common electrode above the Data lines is sharply increased or sharply reduced, so that a voltage value of the common electrode on the whole array substrate is deviated from a desired normal voltage value of the common electrode, and thus an electric field required by normal display of the picture cannot be formed between the pixel electrode and the common electrode, and further, adverse phenomena such as horizontal crosstalk (H-crosstalk) or uneven brightness are easily caused.
Disclosure of Invention
The invention aims to provide an array substrate, a display device and a driving circuit, which solve the problem that a display panel is easy to generate undesirable phenomena such as horizontal crosstalk and uneven brightness due to voltage change of data lines.
The application discloses an array substrate, which comprises a substrate, a pixel electrode layer, a first insulating layer, a plurality of data lines, a second insulating layer, a common electrode layer and a plurality of shielding layers, wherein the pixel electrode layer is arranged on the substrate; the first insulating layer is arranged on the substrate and covers the pixel electrode layer; the data line is arranged on the first insulating layer; the second insulating layer is arranged on the first insulating layer and covers the data line; the common electrode layer is arranged on the second insulating layer and comprises a common shielding electrode layer; the shielding layers are arranged in the second insulating layer and located between the common shielding electrode layer and the data lines, and one shielding layer is arranged corresponding to one data line; the voltage signal of the shielding layer is a direct current signal, and the voltage value of the shielding layer is greater than the absolute value of the voltage signal of the data line.
Optionally, the common electrode layer includes a first common electrode located above the pixel electrode layer, the common shielding electrode layer includes a second common electrode located above the data line, and a width of the shielding layer is greater than or equal to a width of the data line and smaller than a width of the second common electrode; and in the direction of the common electrode layer facing the pixel electrode layer, the projection of the second common electrode covers the projection of the shielding layer, and the projection of the shielding layer covers the projection of the data line.
Optionally, in a direction toward the pixel electrode layer along the common electrode layer, a distance between the shielding layer and the common electrode layer is equal to a distance between the shielding layer and the data line.
Optionally, in a direction along the common electrode layer toward the pixel electrode layer, a distance between the shielding layer and the common electrode layer is a, a distance between the shielding layer and the data line is b, and a is greater than b; or said a is less than b.
Optionally, a first auxiliary electrode is disposed on one side of the shielding layer, a second auxiliary electrode is disposed on the other side of the shielding layer, and the shielding layer, the first auxiliary electrode and the second auxiliary electrode are combined to form an inverted U-shaped structure to cover the data line; wherein the first auxiliary electrode, the second auxiliary electrode and the shielding layer are made of the same material.
Optionally, the common electrode layer includes a first common electrode located above the pixel electrode layer and a second common electrode located above the data line, the width of the shielding layer is greater than or equal to the width of the data line, the width of the second common electrode is smaller than the width of the shielding layer, and a central point of the second common electrode coincides with a central point of the shielding layer.
Optionally, in the extending direction of the data line, the length of the shielding layer is the same as the length of the data line, and the material of the shielding layer may be one of ITO, metal, and the like; and the voltage signal of the shielding layer is equal to the voltage signal of the common electrode layer.
The application also discloses a display device, which comprises a color film substrate and the array substrate, wherein the color film substrate and the array substrate are arranged in a box-to-box manner.
Optionally, the common electrode includes a first common electrode located above the pixel electrode layer and a second common electrode located above the data line, the width of the shielding layer is greater than or equal to the width of the data line, the width of the second common electrode is smaller than the width of the shielding layer, and a central point of the second common electrode coincides with a central point of the shielding layer; the color film substrate is provided with a first preset space corresponding to the position of the second common electrode, the color film substrate is provided with two black matrixes, and the two black matrixes are respectively located on two sides of the first preset space.
The application also discloses a drive circuit for the drive as above array substrate, drive circuit includes driver chip, driver chip is last to be equipped with multiunit pin, and is a set of the pin includes first pin and second pin, first pin with the shielding layer is connected, the second pin with the data line is connected, first pin output direct current signal extremely the shielding layer, second pin output data voltage signal extremely the data line, wherein, direct current signal is greater than data voltage signal's absolute value.
According to the display panel, due to the fact that the shielding layer is arranged, the influence of parasitic capacitance formed by the shielding layer and the common electrode on the common electrode is weaker than the influence of parasitic capacitance formed by the data line and the common electrode on the common electrode in a scheme without the shielding layer, the influence of deviation of the voltage of the common electrode caused by the change of the electric signal of the data line is reduced by the shielding layer, and the problem that the display panel is prone to have bad phenomena such as horizontal crosstalk or uneven brightness due to the change of the voltage of the data line is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic structural diagram of an array substrate according to a first embodiment of the present application;
fig. 2 is a schematic structural diagram of an array substrate according to a second embodiment of the present application;
fig. 3 is a schematic structural diagram of an array substrate and a color filter substrate according to a third embodiment of the present application;
fig. 4 is a schematic view of a part of a display device according to a fourth embodiment of the present application;
fig. 5 is a flow chart of steps of a method of making a fifth embodiment of the present application.
100, a substrate; 200. a pixel electrode layer; 300. a first insulating layer; 400. a data line; 500. a second insulating layer; 600. a common electrode layer; 610. a first common electrode; 620. a second common electrode; 700. a shielding layer; 710. a first auxiliary electrode; 720. a second auxiliary electrode; 800. an array substrate; 900. a color film substrate; 910. a black matrix.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.
The present application will now be described in detail with reference to the drawings and alternative embodiments, it being understood that any combination of the various embodiments or technical features described below may form new embodiments without conflict.
In a conventional liquid crystal panel, a plurality of data lines and scan lines are disposed on an array substrate, and a black matrix corresponding to the positions of the data lines is disposed on a color film substrate to shield a region above the data lines due to the fact that voltage changes of the data lines affect liquid crystals in the region, so that the region is abnormal, but the problem that the aperture ratio of the display panel is low is caused; however, the inventor finds that in the Topcom architecture, although the aperture ratio of the display panel can be increased, the voltage variation on the data line may affect the common electrode located above the data line, so that a parasitic capacitance is generated between the data line and the common electrode to cause the voltage offset of the common electrode in the area, which is liable to cause adverse phenomena such as horizontal crosstalk or uneven brightness, and therefore, the inventor considers the problems in the above scheme and obtains an improved scheme of the present application under continuous research and experiment, which is specifically described as follows:
as shown in fig. 1, as a first embodiment of the present application, an array substrate 800 is disclosed, the array substrate 800 includes a substrate 100, a pixel electrode layer 200, a first insulating layer 300, a plurality of data lines 400, a second insulating layer 500, a common electrode layer 600, and a plurality of shielding layers 700, the pixel electrode layer 200 is disposed on the substrate 100, the first insulating layer 300 is disposed on the substrate 100 and covers the pixel electrode layer 200, the data lines 400 are disposed on the first insulating layer 300, the second insulating layer 500 is disposed on the first insulating layer 300 and covers the data lines 400, the common electrode layer 600 is disposed on the second insulating layer 500, the common electrode layer 600 includes a common shielding electrode layer, the shielding layers 700 are disposed in the second insulating layer 500 and between the common shielding electrode layer and the data lines 400, one shielding layer 700 is disposed corresponding to one data line 400, a voltage signal of the shielding layer 700 is a dc signal, and a voltage value of the shielding layer 700 is greater than an absolute value of a voltage signal of the data line 400.
When the electrical signal of the data line 400 changes, that is, suddenly increases or decreases, the data line 400 and the shielding layer 700 located above the data line 400 form a parasitic capacitance, so that the voltage of the shielding layer 700 deviates, and after the voltage of the shielding layer 700 deviates, the shielding layer 700 and the common electrode of the common electrode layer 600 located above the shielding layer 700 form a parasitic capacitance, and the parasitic capacitance formed by the shielding layer 700 and the common electrode has a weaker influence on the common electrode than the parasitic capacitance formed by the data line 400 and the common electrode has on the common electrode, so as to improve the problem that the display panel is prone to have adverse phenomena such as horizontal crosstalk or uneven brightness due to the voltage change of the data line 400.
In order to improve the problem that the display panel is prone to have undesirable phenomena such as horizontal crosstalk or uneven brightness due to voltage changes of the data lines 400 without reducing the aperture ratio of the display panel, the common electrode layer 600 includes a first common electrode 610 located above the pixel electrode layer 200, the common shielding electrode layer includes a second common electrode 620 located above the data lines 400, the width of the shielding layer 700 is greater than or equal to the width of the data lines 400 and smaller than the width of the second common electrode 620, that is, the projection of the second common electrode 620 covers the projection of the shielding layer 700 along the direction from the common electrode layer 600 to the pixel electrode layer 200, the projection of the shielding layer 700 covers the projection of the data lines 400, so that the effect of the shielding layer 700 on improving the problem that the display panel has undesirable phenomena such as horizontal crosstalk or uneven brightness due to voltage changes of the data lines 400 is optimal, and if the width of the shielding layer 700 is greater than the width of the second common electrode 620, the edge area of the shielding layer 700 may cause the undesirable phenomena such as horizontal crosstalk or uneven brightness of the shielding layer 700 may cause the display panel, and if the width of the shielding layer 700 is greater than the width of the second common electrode 620, the problem that the common electrode 700 may cause the undesirable phenomena such as horizontal crosstalk or uneven brightness of the display panel may cause the display panel, and the undesirable phenomena such as horizontal crosstalk may not cause the display panel, and the display panel may cause the undesirable phenomena such as the horizontal crosstalk or the crosstalk of the display panel 700.
The present embodiment will be explained with reference to the formula, in the Topcom architecture, the common voltage offset generated by the common electrode layer 600 affected by the data line 400 is calculated, and the common voltage offset is calculated according to the formula Vcom offset Δ V COM ＝ΔV data *(C dc /C com ) Calculated to give Δ V data Refers to the varying voltage, C, of the data line 400 dc Is a parasitic capacitance generated between the common electrode and the data line 400, and C com Is that the pixel includes C st And the sum of all capacitances including the parasitic capacitance, and in this embodiment, the data line 400 first affects the shielding layer 700, and then affects the second common electrode 620 through the shielding layer 700, applying the formula V Shielding Offset amount DeltaV Shielding ＝ΔV data *(C d shield /C com ) Wherein, C d shield Is the capacitance formed by the data line 400 and the shielding layer 700, C com The sum of all the capacitances is still maintained, and then the voltage offset of the shielding layer 700 after being affected is calculated, and then the shielding layer 700 affects the second common electrode 620 again, according to the formula V com Offset amount DeltaV COM ＝ΔV Shielding *(C Shielding c /C com )，C Shielding c Is the capacitance formed by the shielding layer 700 and the Com electrode, C com Still the sum of all capacitances, the second common electrode 620 is influenced by the data line 400 to be V com Offset amount delta V COM ＝ΔV data *(C d shield /C com )*(C Shielding c /C com )。
In the direction of the common electrode layer 600 toward the pixel electrode layer 200, the distance between the shielding layer 700 and the common electrode layer 600 is equal to the distance between the shielding layer 700 and the data line 400, the shielding layer 700 divides the whole second insulating layer 500 into two parts, and then simulation is performed in the same pixel, the second insulating layer 500 is preset to be 4000 angstroms, the shielding layer 700 is not added above the data line 400, and the offset of the second common electrode 620 is calculated by the formula: v com Offset amount DeltaV COM ＝ΔV data *(143/511.733)≈0.279ΔV data After the shielding layer 700 is added, the distance between the shielding layer 700 and the data line 400 and the distance between the shielding layer 700 and the second common electrode 620 are both 2000 angstroms, the parasitic capacitance between the shielding layer 700 and the data line 400 is 297.71, and the parasitic capacitance between the shielding layer 700 and the second common electrode 620 is 339.622, and the above formula is applied: v com Offset amount DeltaV COM ＝ΔV data *(297.71/1014.609)*(339.622/1014.609)≈0.098ΔV data That is, when the shielding layer 700 is not added, the second common electrode 620 is affected by 0.279 Δ V data And the influence on the second common electrode 620 after the shielding layer 700 is added is 0.098 Δ V data The difference between adding and not adding the shield layer 700 is about 2.8 times.
Certainly, the position of the shielding layer 700 does not need to be set at the center of the second insulating layer 500, and along the direction from the common electrode to the pixel electrode layer 200, the distance between the shielding layer 700 and the common electrode layer 600 is a, the distance between the shielding layer 700 and the data line 400 is b, and a is greater than b; it is also possible that b is greater than a, and a designer may choose the design according to actual requirements, but it is necessary to consider the problem of voltage breakdown of the shielding layer 700 in the second insulating layer 500, and after ensuring that the second insulating layer 500 is not broken down by the voltage breakdown of the shielding layer 700, the position of the shielding layer 700 may be shifted toward the data line 400 or the second common electrode 620.
The above will be explained with reference to the formula, where the distance between the shielding layer 700 and the data line 400 is x, and the shielding layer 700 and the second common electrode 62The distance of 0 is y, and in the case where the opposite areas of the shield layer 700, the data line 400 and the second common electrode 620 are the same, the capacitance formula is that d represents the distance between the two plates, in which formula
Can be simplified into a constant, and the constant is set to be
C com = N/x + N/y + M, M being other than C d shield And C Shielding c The sum of all the remaining capacitances, wherein C d shield Parasitic capacitance, C, generated between the shield layer 700 and the data line 400 Shielding c Is a parasitic capacitance, V, generated between the shielding layer 700 and the second common electrode 620 Shielding Offset amount DeltaV Shielding ＝ΔV data *(C d shield /C com ) Substituting into a simplified capacitance equation to obtain
Get V in the same way com Offset amount DeltaV COM ＝ΔV Shielding *(C Shielding c /C com )，
Substitution into
Is provided with
To pair
M and N are constants, and both are 1,x + y =4000, so that the simplified method can be obtained
When x = y =2000 angstroms, formula
The minimum value is taken, that is, as the shield layer 700 approaches from the center of the second insulating layer 500 toward the data line 400 or toward the second common electrode 620
The smaller the value of (A), i.e. V com Offset amount DeltaV COM However, the film thickness of the second insulating layer 500 may not be too thin in consideration of voltage breakdown between different layers, and the film thickness of the second insulating layer 500 is preferably 2000 angstroms or 3000 angstroms or more.
Further, the length of the shielding layer 700 is the same as that of the data line 400 along the extending direction of the data line 400, so that the shielding layer 700 can improve the problem that the common electrode above the data line 400 in the whole display panel is affected by the data line 400, wherein the material of the shielding layer 700 may be ITO or metal, and the shielding layer 700 is connected to the Vcom signal with the same size as the common electrode at the PCB board in the display device.
The array substrate 800 is further provided with a gate metal layer, a source metal layer, a drain metal layer and a semiconductor layer, the gate metal layer is formed on the substrate 100, the first insulating layer 300 covers the gate metal layer, the semiconductor layer is arranged on the first insulating layer 300, the source metal layer is arranged on the semiconductor layer, the drain metal layer is arranged on the semiconductor layer and is opposite to the source metal layer, the drain metal layer is connected with the data line 400, the second insulating layer 500 is arranged on the drain metal layer and the source metal layer, a via hole is formed in the first insulating layer 300, and the pixel electrode layer 200 is connected with the source metal layer through the via hole.
As shown in fig. 2, as a second embodiment of the present application, which is a further improvement of the first embodiment of the present application, an array substrate 800 is disclosed, wherein a first auxiliary electrode 710 is disposed on one side of the shielding layer 700, a second auxiliary electrode 720 is disposed on the other side of the shielding layer 700, the first auxiliary electrode 710 and the second auxiliary electrode 720 form an inverted U-shaped structure to cover the data line 400, signals of the first auxiliary electrode 710 and the second auxiliary electrode 720 are the same as that of the shielding layer 700, so as to reduce an influence of an electric field at an edge of the data line 400 on a common electrode or a pixel electrode disposed near the data line 400, and materials of the first auxiliary electrode 710, the second auxiliary electrode 720 and the shielding layer 700 are the same.
As shown in fig. 3, as a third embodiment of the present application, which is a further improvement of the first embodiment of the present application, an array substrate 800 is disclosed, a color filter substrate 900 is disposed on an opposite side of the array substrate 800, the color filter substrate being in apposition with the array substrate 800, the common electrode layer 600 includes a first common electrode 610 disposed above the pixel electrode layer 200 and a second common electrode 620 disposed above the data line 400, a width of the shielding layer 700 is greater than or equal to a width of the data line 400, a width of the second common electrode 620 is smaller than a width of the shielding layer 700, a center point of the second common electrode 620 coincides with a center point of the shielding layer 700, that is, the second common electrode 620 does not completely cover the shielding layer 700, a first preset space is disposed on the color filter substrate 900 corresponding to the second common electrode 620, a black matrix 910 is disposed on the color filter substrate 900, the black matrices 910 are disposed on two sides of the first preset space, the two black matrices 910 are disposed on two sides of the first preset space respectively, so as to cover the shielding layer 620 which cannot be covered by the second common electrode 620, thereby preventing the shielding layer 700 from affecting the display of the common electrode 700.
As shown in fig. 4, as a fourth embodiment of the present application, a display device is disclosed, where the display device includes a display panel, the display panel includes a color filter substrate 900 and an array substrate 800 according to any one of the embodiments, the color filter substrate 900 and the array substrate 800 are disposed in a cassette, and the display device can reduce an influence of a signal change of the data line 400 on a display screen.
Further, the common electrode layer 600 includes a first common electrode 610 located above the pixel electrode layer 200 and a second common electrode 620 located above the data line 400, a width of the shielding layer 700 is greater than or equal to a width of the data line 400, a width of the second common electrode 620 is smaller than the width of the shielding layer 700, a center point of the second common electrode 620 coincides with a center point of the shielding layer 700, that is, the second common electrode 620 does not completely cover the shielding layer 700, a first predetermined space is provided on the color filter substrate 900 corresponding to the second common electrode 620, a black matrix 910 is provided on the color filter substrate 900, two black matrices 910 are provided, the two black matrices 910 are respectively located on two sides of the first predetermined space, and the two black matrices 910 shield the shielding layer 700 that cannot be covered by the second common electrode 620, so as to prevent a region where the shielding layer 700 is not covered by the second common electrode 620 from affecting a liquid crystal layer located above the region and disturbing a display image.
As shown in fig. 5, as a fifth embodiment of the present application, a manufacturing method is disclosed, which is applied to the array substrate according to the above embodiment, and the manufacturing method includes the steps of:
s100: forming a pixel electrode layer on a substrate;
s200: forming a first insulating layer on the substrate, wherein the first insulating layer covers the pixel electrode layer;
s300, forming a data line on the first insulating layer;
s400, forming a first sub-insulating layer on the first insulating layer, wherein the first sub-insulating layer covers the data line;
s500: forming a shielding layer on the first sub-insulating layer;
s600: forming a second sub-insulating layer on the first sub-insulating layer, wherein the second sub-insulating layer covers the shielding layer;
s700: forming a common electrode layer on the second sub-insulating layer;
wherein the first sub-insulating layer and the second sub-insulating layer are combined to form a second insulating layer.
As a sixth embodiment of the present application, a driving circuit is disclosed for driving the array substrate 800 according to the above embodiments, the driving circuit includes a driving chip, the driving chip is provided with a plurality of groups of pins, and each group of pins includes a first pin and a second pin, the first pin is connected to the shielding layer 700, the second pin is connected to the data line 400, the first pin outputs a dc signal to the shielding layer 700, the second pin outputs a data voltage signal to the data line 400, wherein the dc signal is greater than an absolute value of the data voltage signal.
It should be noted that, on the premise of not affecting the implementation of the specific embodiment, the limitations of the steps involved in the present disclosure are not considered as limiting the order of the steps, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present disclosure.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.
The foregoing is a further detailed description of the present application in connection with specific alternative embodiments and it is not intended that the present application be limited to these specific details. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. An array substrate, comprising:
a substrate;
a pixel electrode layer disposed on the substrate;
a first insulating layer disposed on the substrate and covering the pixel electrode layer;
a plurality of data lines disposed on the first insulating layer; and
a second insulating layer disposed on the first insulating layer and covering the data line;
characterized in that, the array substrate still includes:
the common electrode layer is arranged on the second insulating layer and comprises a common shielding electrode layer; and (c) a second step of,
the shielding layers are arranged in the second insulating layer and positioned between the common shielding electrode layer and the data lines, and one shielding layer is arranged corresponding to one data line;
the voltage signal of the shielding layer is a direct current signal, and the voltage value of the shielding layer is greater than the absolute value of the voltage signal of the data line.
2. The array substrate of claim 1, wherein the common electrode layer comprises a first common electrode over the pixel electrode layer, the common shielding electrode layer comprises a second common electrode over the data line, and the width of the shielding layer is greater than or equal to the width of the data line and less than the width of the second common electrode;
and in the direction of the common electrode layer facing the pixel electrode layer, the projection of the second common electrode covers the projection of the shielding layer, and the projection of the shielding layer covers the projection of the data line.
3. The array substrate of claim 1 or 2, wherein a distance between the shielding layer and the common electrode layer is equal to a distance between the shielding layer and the data line in a direction from the common electrode layer to the pixel electrode layer.
4. The array substrate according to claim 1 or 2, wherein in a direction toward the pixel electrode layer from the common electrode layer, a is a distance between the shielding layer and the common electrode layer, b is a distance between the shielding layer and the data line, and a is greater than b; or said a is less than b.
5. The array substrate of claim 1 or 2, wherein a first auxiliary electrode is disposed on one side of the shielding layer, a second auxiliary electrode is disposed on the other side of the shielding layer, and the shielding layer, the first auxiliary electrode and the second auxiliary electrode are combined to form an inverted U-shaped structure to cover the data line;
wherein the first auxiliary electrode, the second auxiliary electrode and the shielding layer are made of the same material.
6. The array substrate of claim 1, wherein the common electrode layer comprises a first common electrode over the pixel electrode layer and a second common electrode over the data line, the width of the shielding layer is greater than or equal to the width of the data line, the width of the second common electrode is less than the width of the shielding layer, and a center point of the second common electrode coincides with a center point of the shielding layer.
7. The array substrate of claim 1, wherein the shielding layer has a length equal to that of the data line along the extending direction of the data line, and the material of the shielding layer is one of ITO, metal, and the like; and the voltage signal of the shielding layer is equal to the voltage signal of the common electrode layer.
8. A display device, comprising a color filter substrate and the array substrate according to any one of claims 1 to 7, wherein the color filter substrate and the array substrate are arranged in a cassette-to-cassette manner.
9. The display device according to claim 8, wherein the common electrode comprises a first common electrode over the pixel electrode layer and a second common electrode over the data line, wherein the width of the shielding layer is equal to or greater than the width of the data line, the width of the second common electrode is smaller than the width of the shielding layer, and a center point of the second common electrode coincides with a center point of the shielding layer;
the position, corresponding to the second common electrode, of the color film substrate is provided with a first preset space, the color film substrate is provided with two black matrixes, and the two black matrixes are located on two sides of the first preset space respectively.
10. A driving circuit for driving the array substrate according to any one of claims 1 to 7, wherein the driving circuit comprises a driving chip, the driving chip is provided with a plurality of sets of pins, one set of the pins comprises a first pin and a second pin, the first pin is connected to the shielding layer, the second pin is connected to the data line, the first pin outputs a dc signal to the shielding layer, and the second pin outputs a data voltage signal to the data line;
wherein the DC signal is greater than an absolute value of the data voltage signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116300222A (en) * | 2023-03-21 | 2023-06-23 | 福州京东方光电科技有限公司 | Display panel and electronic equipment |
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| US20100301345A1 (en) * | 2009-05-26 | 2010-12-02 | Au Optronics Corp. | Array substrate and method for manufacturing the same |
| CN104916648A (en) * | 2015-06-11 | 2015-09-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method and display device |
| US20150268528A1 (en) * | 2014-03-19 | 2015-09-24 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
| US20160190178A1 (en) * | 2014-12-29 | 2016-06-30 | Shanghai Tianma Micro-electronics Co., Ltd. | Array substrate, manufacture method thereof, and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100301345A1 (en) * | 2009-05-26 | 2010-12-02 | Au Optronics Corp. | Array substrate and method for manufacturing the same |
| US20150268528A1 (en) * | 2014-03-19 | 2015-09-24 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
| US20160190178A1 (en) * | 2014-12-29 | 2016-06-30 | Shanghai Tianma Micro-electronics Co., Ltd. | Array substrate, manufacture method thereof, and display device |
| CN104916648A (en) * | 2015-06-11 | 2015-09-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method and display device |
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| CN116300222A (en) * | 2023-03-21 | 2023-06-23 | 福州京东方光电科技有限公司 | Display panel and electronic equipment |
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