CN115190187B

CN115190187B - Data conversion method and data processing method

Info

Publication number: CN115190187B
Application number: CN202210824652.1A
Authority: CN
Inventors: 武文雄
Original assignee: Neuron Information Technology Chengdu Co ltd
Current assignee: Neuron Information Technology Chengdu Co ltd
Priority date: 2021-02-19
Filing date: 2021-02-19
Publication date: 2024-06-28
Anticipated expiration: 2041-02-19
Also published as: CN115190187A; CN112968894B; CN112968894A

Abstract

The application relates to a data conversion method and a data processing method. In an embodiment of the present application, the interface conversion device may include: each LIN unit comprises a state machine and a LIN main node, the state machines are respectively connected with the LIN main node, the processor interfaces and the TAXI interfaces, the TAXI interfaces are connected with the state machines and the LIN main node and are simultaneously externally connected with a TAXI bus, and the processor interfaces are respectively connected with the state machines and the LIN main node and are simultaneously externally connected with a CPU. The embodiment of the application realizes the conversion of the Ethernet message and the LIN message through hardware, and can effectively improve the efficiency and save the CPU resource.

Description

Data conversion method and data processing method

The application relates to a division application of 2021, 2, 19, 202110195735.4 and 'interface conversion device and computing device'.

Technical Field

The present application relates to the field of data communication technologies, and in particular, to a data conversion method and a data processing method.

Background

At present, interface conversion between a local interconnect network (LIN, local Interconnect Network) and an ethernet is mostly processed directly by using a CPU, and the architecture is shown in fig. 1, where the CPU parses an ethernet packet and then configures the ethernet packet to a LIN master node (lin_core). Because the LIN interface is slow and the Ethernet is fast, the LIN master node needs to initiate interrupt to the CPU for a plurality of times in the receiving and transmitting process of an Ethernet data packet to perform intermediate processing, and the CPU efficiency is seriously affected.

Disclosure of Invention

In view of the above problems in the prior art, the present application provides an interface conversion device dedicated for conversion between an ethernet interface and a LIN interface, so as to realize conversion between an ethernet message and a LIN message through hardware, without direct processing of a CPU, thereby effectively improving efficiency and saving CPU resources.

To achieve the above object, a first aspect of the present application provides an interface conversion device, including: each LIN unit comprises a state machine and a LIN main node, the state machines are respectively connected with the LIN main node, the processor interfaces and the TAXI interfaces, the TAXI interfaces are connected with the state machines and the LIN main node and are simultaneously externally connected with a TAXI bus, and the processor interfaces are respectively connected with the state machines and the LIN main node and are simultaneously externally connected with a CPU;

Wherein, ethernet message from TAXI bus is received by the said TAXI interface and buffer the effective bearing part in the said Ethernet message according to LIN number therein; the method comprises the steps that an effective bearing part in an Ethernet message enters a state machine in a LIN unit corresponding to the LIN number of the Ethernet message, the state machine configures a LIN main node in the LIN unit by analyzing the effective bearing part in the Ethernet message, the LIN main node returns LIN data corresponding to the Ethernet message to a TAXI interface after completing receiving and transmitting according to the configuration and LIN control information from a processor interface, and the TAXI interface packages the LIN message by using the LIN data and LIN control information corresponding to the LIN number from the processor interface and sends the LIN message to the TAXI bus.

By the method, the conversion from the Ethernet message to the LIN message is realized through hardware, direct processing of a CPU is not needed, the efficiency is effectively improved, and the CPU resource is saved.

In at least some embodiments, the TAXI interface includes: and the first buffer is configured to buffer the effective bearing part in the Ethernet message according to the LIN number.

By the method, parallel receiving and transmitting of multiple LINs are realized, and competition risks caused by simultaneous receiving and transmitting of the multiple LINs are effectively reduced.

In at least some embodiments, the tani interface includes a second buffer configured to buffer the LIN messages according to the LIN number, so as to send the LIN messages of the at least one LIN unit in parallel.

By the method, parallel processing of the multi-path LIN message is realized, and competition risks caused by simultaneous receiving and transmitting of the multi-path LIN are effectively reduced.

In at least some embodiments, the state machine is further configured to receive an interrupt initiated by the LIN master node, send an interrupt message to the CPU through the processor interface when the interrupt indicates an exception, and directly mask the interrupt message when the interrupt indicates normal.

By the method, the influence on CPU efficiency caused by the fact that the LIN master node initiates interruption for a plurality of times in the data receiving and transmitting process is effectively avoided.

In at least some embodiments, the processor interface is further configured to update an error flag to an interrupt reset after receiving an interrupt resume signal from the CPU, such that each of the LIN units continues to enable operation by detecting the error flag bit.

By the above, the hardware reset of the interface conversion device is realized.

In at least some embodiments, each LIN unit further comprises: a judgment logic circuit; the state machine in the LIN unit is connected with the TAXI interface, the processor interface and the LIN master node through the judging logic circuit, and the TAXI interface and the processor interface are respectively connected with the LIN master node in the LIN unit through the judging logic circuit.

By the method, unified management and reasonable branching of data interaction in the interface conversion device are realized.

In at least some embodiments, the state machine is specifically configured to intercept an ID field of a valid bearer portion in the ethernet packet and configure the ID field into an IP of the LIN master node.

By the above, the IP configuration of the LIN host is realized.

In at least some embodiments, the state machine is specifically configured to intercept a data length bit field of an active bearer portion in the ethernet packet and configure the data length bit field into a data length register of the LIN master node.

By the above, the configuration of the LIN master node data length is realized.

In at least some embodiments, the state machine is specifically configured to intercept the data bit field of the active bearer portion in the ethernet packet and configure the data bit field into a corresponding data register in the LIN master node.

By the above, the data configuration of the LIN master node is realized.

A second aspect of the application provides a computing device comprising: the interface conversion device.

Drawings

The various features of the application and the connections between the various features are further described below with reference to the figures. The figures are exemplary, some features are not shown in actual scale, and some features that are conventional in the art to which the application pertains and are not essential to the application may be omitted from some figures, or additional features that are not essential to the application may be shown, and the combination of features shown in the figures is not meant to limit the application. In addition, throughout the specification, the same reference numerals refer to the same. The specific drawings are as follows:

Fig. 1 is a schematic diagram of an interface conversion between an ethernet and a LIN in the related art;

fig. 2 is a schematic structural diagram of an interface conversion device according to an embodiment of the present application;

fig. 3 is a schematic diagram of a LIN-related payload format in an ethernet packet according to an embodiment of the present application;

FIG. 4 is an exemplary hardware structure of an interface conversion device and an external schematic diagram thereof according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a processing state of a state machine in an interface conversion device according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a computing device provided by an embodiment of the present application.

Detailed Description

The terms first, second, third, etc. or module a, module B, module C and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order, and it is to be understood that the specific order or sequence may be interchanged if permitted to implement embodiments of the application described herein in other than those illustrated or described.

The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "a device comprising means a and B" should not be limited to a device consisting of only components a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments as would be apparent to one of ordinary skill in the art from this disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If there is a discrepancy, the meaning described in the present specification or the meaning obtained from the content described in the present specification is used. In addition, the terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

As described above, in the related art, the conversion between the ethernet interface and the LIN interface in the chip is mainly completed by the CPU, which requires that the LIN device initiate interrupts to the CPU multiple times to complete the intermediate processing, which not only has low processing efficiency, but also needs to occupy a large amount of CPU resources to seriously affect the CPU efficiency. Aiming at the technical problem, the basic idea of the embodiment of the application is to provide an interface conversion device realized by hardware, which can realize interface conversion by connecting the interface conversion device among a CPU, an Ethernet and a TAXI interface without direct processing of the CPU, thereby effectively improving the efficiency and saving CPU resources.

Herein, a axi interface, which may also be referred to as an ethernet interface, refers to an interface of a axi bus, which may be configured to transmit ethernet messages between routers. It should be noted that although collectively referred to herein as a TAXI interface, it is understood that the TAXI interface may be replaced with any other interface capable of transmitting ethernet messages.

Fig. 2 illustrates an exemplary structure of an interface conversion apparatus 100 provided in an embodiment of the present application. Referring to fig. 2, the interface conversion device of the embodiment of the present application may include at least one LIN unit 110, a TAXI bus (TAXI) interface 120, and a processor interface 130, where each LIN unit 110 may include a state machine 111 and a LIN master (LIN Core) 112, the state machine 111 is connected to a LIN master 112, the processor interface 130 is connected to the TAXI interface 120, the TAXI interface 120 is connected to the state machine 111 and the LIN master 112, and is externally connected to the TAXI bus, and the processor interface 130 is connected to the state machine 111 and the LIN master 112, and is externally connected to the CPU.

The ethernet packet from the tani bus is received by the tani interface 120 and buffered according to the LIN number therein, the payload in the ethernet packet enters the state machine 111 in the LIN unit 110 corresponding to the LIN number thereof, the state machine 111 configures the LIN master node 112 in the LIN unit 110 by analyzing the payload in the ethernet packet, the LIN master node 112 returns LIN data corresponding to the ethernet packet to the tani interface 120 after completing the transceiving according to the configuration of the state machine and the LIN control information from the processor interface, and the tani interface 120 encapsulates the LIN packet with the LIN data and the LIN control information corresponding to the LIN number from the processor interface 130 and sends the LIN packet to the tani bus. Therefore, the embodiment of the application realizes the conversion from the Ethernet message to the LIN message through hardware, does not need direct processing of a CPU, and can effectively avoid the influence on the CPU efficiency caused by the interrupt initiated for a plurality of times in the LIN receiving and transmitting process, thereby effectively improving the efficiency and saving the CPU resource while realizing the message conversion between the Ethernet and the LIN.

In an embodiment of the present application, the tani interface 120 may be configured to receive an ethernet packet from the tani bus, and buffer a payload in the ethernet packet according to a LIN number in the ethernet packet; and is configured to encapsulate the LIN message with LIN data from the LIN master 112 and LIN control information from the processor interface 130 and send it onto the tani bus.

Referring to fig. 2, a tani interface 120 is connected between each LIN unit 110 and a tani bus, and can receive ethernet messages and return LIN messages to the ethernet through the tani bus, and the tani interface 120 can receive LIN data from each LIN unit 110 in parallel by connecting each LIN unit 110, thereby implementing parallel transmission of multiple LIN messages.

In some embodiments, the tani interface 120 may include a first buffer 121, where the first buffer 121 may be configured to buffer the active bearer portion in the ethernet packet according to the LIN number. Specifically, referring to fig. 2, the first buffer 121 may include first buffer areas 1211 that are differentiated by LIN number, and these first buffer areas 1211 are configured to buffer the active bearer portions that need to be sent to the LIN unit 110 identified by its LIN number. In this embodiment, the tani interface 120 may send the corresponding effective bearer portion into the corresponding first buffer 1211 according to the LIN number in the ethernet packet, and the state machine 111 in the corresponding LIN unit 110 only needs to read the effective bearer portion of the ethernet packet from the first buffer 1211 corresponding to the LIN number. In this way, the multiple LIN units 110 can complete message transceiving in parallel and relatively independently, so as to effectively reduce competition risks caused by simultaneous transceiving of multiple LINs.

In some embodiments, the tani interface 120 may further include a second buffer 122, where the second buffer 122 is configured to buffer LIN messages according to the LIN number, so as to send LIN messages of at least one LIN unit in parallel. Specifically, referring to fig. 2, the second buffer 122 may include second buffer areas 1221 distinguished by LIN numbers, each second buffer area 1221 configured to buffer LIN data from the LIN unit 110 identified by the corresponding LIN number. In this embodiment, LIN data from each LIN unit 110 may be sent to the corresponding second buffer 1221 according to the LIN number, and the tani interface 120 only needs to read LIN data of one LIN number from the second buffer 1221. In this way, LIN messages of the multiple LIN units 110 can be processed in parallel and relatively independently, so as to effectively reduce the risk of competition caused by simultaneous transmission and reception of multiple LINs.

In some embodiments, the axi interface 120 may further store a memory (not shown in fig. 2) for storing ethernet packets, where the memory may be implemented by, for example, a first-in first-out (FIFO), and the ethernet packets are stored according to a first-in first-out principle after reaching the axi interface, and the memory may be full to suspend receiving ethernet packets to avoid packet loss. Referring to the example of fig. 4, the memory may be, but is not limited to, a FIFO of bit width 96 and depth 16, which may be set to 10 for a backpressure pipeline.

Lin is slower, and in order to solve the problem of insufficient transmission, in some examples, the first buffer and the second buffer may be implemented by setting two groups of buffers, where the buffers may be implemented by registers.

Taking the example of multi-way LIN parallelism as shown in fig. 4 below, the active bearer portions for different ways LIN (i.e., ctrl_1-ctrl_6 in fig. 4) will be stored in FIFOs in lin_num, respectively, and each of the active bearer portions enters multiple sets 96bits buffer_1 (an example of a first Buffer zone). In this way, the multi-way LIN units 110 (i.e., ctrl_1-ctrl_6 in fig. 4) can read the corresponding active bearer portions from the tani interface 120 in parallel. When the interface conversion device is in an enabled operational state (e.g., state machine state jumps to hardware processing), one or more of CTRL_1-CTRL_6 (an example of LIN unit 110) will take data from buffer_1 in 96bits wide. Even if the data is less than 96bits, the data needs to be read at 96bits, and the data can be intercepted according to the data_length in one or more of CTRL_1 to CTRL_6 after the data arrives at the data.

In some embodiments, the tani interface 120 may include an identifying module 123 configured to identify a payload in an ethernet packet from the tani bus, extract the payload, and send the payload to the first buffer 1211 in the first buffer 121 corresponding to the LIN number in the ethernet packet.

Fig. 3 shows a schematic diagram of the payload format in an ethernet packet. Referring to the example of fig. 3, the LIN-related payload portion extracted from the ethernet message may include, but is not limited to, the following fields: vld, transmit, RFU, data length (byte_num) [3:0], lin_num [2:0], id [5:0], wakeup, wait for future use (RFU, reserved for used), command maker [5:0], CRC [4:0], RFU [2:0], data.

The bit fields in fig. 3 are illustrated as follows:

lin_num represents the LIN number.

Vld: this bit is high to indicate that the frame is valid, and is to distinguish it from the padding frame when the message is less than 64B. If this bit is low, the frame is not processed for direct transparent transmission.

Wakeup, transmit, id is defined by the LIN protocol, reference may be made to the document LIN-usg-2x21n00s 00. Wakeup indicates that the LIN master node receives or transmits a Wakeup (Wakeup up) signal, transmit is 1 for transmit and 0 for receive. id is an identifier.

Command_markers are used to mark different frames, and the Command_markers for frames in packets from the same TAXI bus may be the same or different.

The CRC is used to CRC5 check the payload field (about 96 bits) of the entire LIN. If the received message CRC5 is in error, the message is not processed any more, and the message is discarded.

In some embodiments, an encapsulation module 124 may be included in the tani interface 120 and configured to encapsulate the LIN message with payload in the ethernet message and LIN data returned by the corresponding LIN master node 112 and send the encapsulated LIN message onto the ethernet via the tani bus. Specifically, the encapsulation module 124 may be configured to obtain the payload of the ethernet packet from a first buffer 1211 in the first buffer 121, and obtain LIN data with the same LIN number from a corresponding second buffer 1221 in the second buffer 122, encapsulate the ethernet packet into a LIN packet according to a predetermined LIN packet format, and send the LIN packet to the tani bus.

In some embodiments, the axi interface 120 may be configured to issue LIN messages of each LIN unit 110 in order of priority. Specifically, the tani interface 120 prioritizes LIN messages of the multiple LIN units 110, and in parallel sending of the multiple LIN messages, the tani interface 120 sends the LIN messages onto the ethernet in sequence according to the priorities.

The processor interface 130 may be configured to provide LIN control information to the axi interface 120 and the LIN master 112, and to send interrupt messages initiated by the LIN master 112 to the CPU.

In some embodiments, the processor interface 130 may include a register (not shown in fig. 2) in which LIN control information of each path may be stored according to the LIN number. These registers in the processor interface 130 may query the LIN master 112 for LIN control information required for transceiving according to the LIN number and other information provided by the state machine 111 and provide the LIN control information to the state machine 111, so that the state machine 111 configures the LIN master 112. In addition, these registers in the processor interface 130 may also query LIN control information required for packaging the LIN message according to the LIN number and other information provided by the axi interface 120, and provide the LIN control information to the axi interface 120, so that the axi interface 120 completes packaging the LIN message.

Here, the LIN control information required for the LIN master node 112 to transmit and receive may include: address and necessary data. Such as message format, content to be returned, identifier, data length, software control state, hardware control state, etc.

Here, the control information required for encapsulating the LIN message may include: control items required for encapsulating each LIN message corresponding to the LIN number include, but are not limited to, medium Access Control (MAC), error type (two broad categories, 3 errors specified by the LIN bus and not conforming to the expected 3 types of the TAXI message), VLAN Tag (VLAN Tag), etc. In some embodiments, control items for respective LIN numbers may be stored by setting registers corresponding to the LIN numbers of the respective paths in the processor interface 130.

The state machine 111 may be configured to parse payload in an ethernet packet from the axi interface 120 corresponding to its own LIN number to intercept LIN related information, and to configure the LIN master node 112 with the LIN related information. For specific details regarding the state machine, see the examples of fig. 4 and 5 below. It should be noted that fig. 5 is only used as an example, and is not intended to limit the specific implementation of the state machine in the embodiment of the present application. It will be appreciated that the specific functions of the state machine 111, and the execution logic and states thereof, etc. may be adjusted according to the actual application scenario, LIN format, and ethernet message format.

In the embodiment of the present application, the LIN master node 112 may be configured to complete data transceiving according to the configuration of the state machine 111, and return corresponding LIN data. Specifically, the LIN master 112 may be configured to complete data transceiving using LIN control information corresponding to its own LIN number from the processor interface 130, and return LIN data to the tani interface 120, according to the configuration of the state machine 111. Here, the data transceiving of the LIN master node 112 may include, but is not limited to, data interaction between the LIN master node 112 and at least one slave node (slave) to which it is connected. In a specific application, when the LIN master node 112 transmits data, the LIN master node 112 transmits the data according to the minimum packet length defined by the LIN protocol as 64B, and if the data length is insufficient, the LIN master node 112 supplements 0 to fill the data to the 64B size and then transmits the data.

In some embodiments, the LIN master node 112 may connect directly or indirectly to the axi interface 120 to return LIN data to the axi interface 120 after completion of data transceiving. For example, LIN master 112 may be connected to a axi interface 120 through decision logic 113.

Here, the LIN data may include, but is not limited to, LIN payload, error prompt information, etc., obtained by the LIN master node interacting with its slave node (slave). The LIN payload may include, among other things, status data, for example. The error prompt information is information for indicating that the LIN equipment side is abnormal. Here, the error prompt information may include two types, one type is the error prompt information specified by the LIN bus, for example, "slave response timeout", "LIN protocol bit error", "LIN protocol checksum error", etc.; the other type is error prompt information indicating error action, for example, "length information in a TAXI message is out of range or LIN number is out of range", "TAXI message CRC check error", "CPU command state forced jump in case of error", etc.

In some embodiments, each LIN unit 110 may further include a decision logic 113, where the decision logic 113 may be configured to connect the state machine 111 to the tani interface 120, the processor interface 130, and the LIN master node 112, respectively. In addition, the decision logic 113 may be further configured to connect the LIN master 112 with the axi interface 120 to return LIN data to the axi interface 120.

Here, the decision logic 113 may determine the actions (e.g., wake up, transmit, receive, etc.) that the LIN master 112 needs to perform and notify the LIN master 112 based on the state of the axi interface 120 and the state of the state machine 111.

In some examples, the decision logic 113 also has a branching function. Specifically, the determination logic 113 may send data addressed to the LIN master 112 to the data terminal of the LIN master 112, and send address information of the LIN master 112 to the address terminal of the LIN master 112.

In addition, the decision logic 113 may be further configured to send status bits of the state machine 111 (e.g., flag bits corresponding to various states shown in fig. 5 below) to the processor interface 130 or the LIN master 112, so that the processor interface 130 and the tani interface 120 can timely learn the state of the state machine 111 and the state of the LIN master 112.

In some embodiments, each LIN unit 110 may further include a memory (not shown) therein, which may be configured to store a payload from the axi interface 120, LIN control information from the processor interface 130, LIN data required for the axi interface 120, and/or interrupt messages required for the processor interface 130. The memory is accessible to both the decision logic 113 and the state machine 111 in the LIN unit 110. In some examples, the data or information needed to be provided to the LIN master node 112, the data or information from the LIN master node 112, may all be accessed to the memory by the decision logic 113 to complete its access. In practice, the memory may include, but is not limited to, one or more sets of registers.

In the embodiment of the application, each part of the interface conversion device can initiate interruption. The axi interface 120, the processor interface 130, the state machine 111, or the LIN master 112 may initiate an interrupt when an exception error occurs (e.g., LIN protocol error of the LIN master 112, ethernet message error of the axi interface 120, DRC check, etc., timeout (timing) interrupt of the state machine 111, etc.). An interrupt may also be initiated under certain normal conditions, such as a completion (complete) interrupt that the LIN master 112 may initiate after each execution of a transceiver. In some embodiments, the state machine 111 may be further configured to receive an interrupt initiated by the LIN master node 112, send an interrupt message to the CPU through the processor interface 130 when the interrupt indicates an exception, and directly mask the interrupt message (e.g., may be directly discarded or eliminated by the LIN master node) when the interrupt indicates normal (e.g., a complete interrupt initiated by the LIN master node 112). In this way, for the interrupt indicating abnormality, the CPU can process the interrupt, and the state machine 111 controls the corresponding LIN master node 112 to stop working, and for the interrupt message indicating abnormality, the interrupt message can be directly cleared without notifying the CPU, so that the influence on CPU efficiency caused by that the LIN master node initiates the interrupt for multiple times in the data transceiving process can be effectively avoided.

For example, normal interrupts such as "complete" may not be delivered to the CPU to avoid affecting CPU efficiency. Abnormal interrupts such as "slave timeout", "LIN protocol error", "message format illegal", etc., the state machine 111 can send the interrupt message to the CPU through the judgment logic 113 and the processor interface 130, and be processed by the CPU. Thus, after the LIN master 112 or state machine 111 initiates an interrupt, only the abnormal interrupt message is sent to the CPU for further processing.

In some embodiments, after the CPU has processed the interrupt, an interrupt resume signal will be sent to the processor interface 130. The processor interface 130 may also be configured to update the pre-configured error flag to an interrupt reset upon receiving an interrupt resume signal from the CPU so that the LIN units 110 (e.g., state machines in the LIN units) continue to enable operation by detecting the error flag bit.

Taking 6-way LIN as an example, fig. 4 shows an exemplary specific structure of an interface conversion device 100 according to an embodiment of the present application. Referring to fig. 4, the interface conversion device 100 includes 6 LIN units 110 (i.e., ctrl_1 to ctrl_6), a axi interface 120 (i.e., axi_if), a processor interface 130 (i.e., cpu_if), a cpu_if external to a CPU, a CPU external to a serial peripheral interface (SPI, serial Peripheral Interface), an advanced high Performance Bus (AHB, advanced High Performance Bus), etc., the axi_if external to a axi_i Bus, where the axi_i Bus is connected to a SWITCH CORE, each LIN unit 110 includes a state machine 111, a determination logic 113, and a LIN master node LIN-CORE 112, where each LIN master node 112 is externally connected to at least one slave node (slave) through the determination logic 113.

In the example of fig. 4, a flow pressure countercontrol module may also be included in the TAXI interface 120, and the flow pressure countercontrol module may be configured to report to the TAXI bus when buffer_1 (example of the first Buffer 121) and/or buffer_2 (example of the second Buffer 122) exceeds a predetermined waterline. The reverse flow control module may be further configured to report to the TAXI bus when the FIFO exceeds a predetermined waterline.

Referring to fig. 4, in the interface conversion apparatus 100, the tani_if receives an ethernet packet (data_1) from a tani_i bus (an example of a tani bus), determines whether the packet should be processed by using a port number (port_num) of the ethernet packet, and IF so, the tani_if sends the ethernet packet to a FIFO (an example of a memory for storing ethernet packets in the tani interface 120) of 96 bits. Then, for each ethernet packet in the FIFO, the tani_if extracts the destination LIN number from its LIN number (lin_num) bit field, and then sends the payload portion in the ethernet packet into the partition of the corresponding LIN number in buffer_1 of 96bits×6 according to the destination LIN number.

The LIN units 110 may transmit and receive in parallel. In each LIN unit 110, the state machine 111 acquires payload of its own LIN number from buffer_1, extracts relevant information therein by bit field (for example, extracts information of LIN number and id field according to message format), and configures the relevant information to LIN-Core (an example of a LIN master node) by the judging logic circuit 113 according to the current state to control the LIN-Core to transmit and receive data. LIN control information required for LIN-Core data transmission and reception is transmitted to the LIN-Core by the cpu_if through the judgment logic circuit 113. After the LIN-Core completes data transmission and reception, the corresponding LIN data is returned to the tani_if through the judgment logic circuit 113.

In the working process of the interface conversion device, the flow control back pressure module in the TAXI_IF can detect whether each Buffer and each FIFO exceed the waterline in real time, and report the notification that the Ethernet data cannot be continuously received to the front-stage module when the Buffer or the FIFO exceeds the preset waterline.

For LIN data returned by each line of LIN units, the tani_if can be processed in parallel. The encapsulation module in the taii_if compiles LIN messages (including Data, LIN number and id) in message format and buffers in 96bits x 6 buffers at the egress, encapsulates these LIN messages as ethernet messages (data_0) by adding headers or other means before them, and sends them onto the taii bus when appropriate, for example, by a counter to control when they are sent. Here, the ethernet messages of the multiple LINs may be prioritized, and when the ethernet messages of the multiple LINs are sent in parallel, the ethernet messages of the multiple LINs are sequentially sent to the taxi_i bus according to the priority, so as to be sent to the ethernet. Here, LIN control information required for the axi_if to perform LIN packet is transmitted to the axi_if by the cpu_if through the judgment logic circuit 113.

After an interrupt is initiated by the LIN-Core or other parts of the LIN unit, the interrupt may be directly masked against the indication of normal. For interrupts indicating exceptions, the state machine sends a corresponding interrupt message to the CPU through the cpu_if, which continues processing, while the state machine 111 may jump to a software processing state, described below, and the hardware switching function of the interface switching device stops. After the CPU processes the interrupt, an interrupt reset signal is returned, the CPU_IF decodes the interrupt reset signal, and an error flag in the interrupt reset signal is reset to be interrupt reset, so that the reset of the interrupt signal is completed. The interface conversion means (e.g. state machine) continues to enable operation after detecting error recovery by monitoring the error flag.

Fig. 5 shows an exemplary process of state machine 111. Referring to fig. 5, the operating states of the state machine 111 may include a software processing state, a waiting state, an id state, a byte_num state, a Data state, a transfer (Transmit) state, a Req state, a transceiving state, and a splicing (enCAP) state.

In the software processing state, the state machine 111 and its LIN master 112 stop working, and interface conversion between the ethernet interface and the LIN interface is completed by the CPU. In this state, the process of interface conversion can be seen in fig. 1. In practical applications, in the event of an abnormal interrupt, the interface conversion may be completed by the CPU by switching to a software processing state to stop the interface conversion of the hardware.

For example, in the case where the CPU configuration Hardw flag is high, the state machine 111 jumps to a wait state where the state machine 111 and its LIN master 112 may be in a standby state.

After the tani interface 120 receives the ethernet packet and sends the payload thereof to the corresponding first buffer 1211 of the first buffer 121 according to the LIN number therein, the state machine 111 in the LIN unit 110 corresponding to the LIN number enters an ID state, where the state machine 111 may be configured to intercept the ID field of the payload in the ethernet packet and configure the IP of the corresponding LIN master node 112.

After the IP configuration is completed, the state machine 111 jumps to the byte_num state. In the byte_num state, the state machine 111 may be configured to intercept the byte_num bit field of the payload in the ethernet packet, calculate and configure the data length of the LIN master node 112 (DATA LENGTH registers).

After DATA LENGTH register configuration is complete, state machine 111 enters the Transmit state. In the Transmit state, the state machine 111 configures a Transmit bit of the corresponding LIN master node 112 according to the count N of the byte counter, where the Transmit bit is used to indicate the transmission state of the LIN master node 112, and when 0 is taken, it indicates that the LIN-Core is in the receiving state, and when 1 is taken, it indicates that the LIN-Core is in the transmitting state. When n=0, the state machine 111 configures the Transmit bit of the LIN master node 112 to be 0, that is, configures the LIN master node 112 to be in the receiving state, and when N is greater than 0, configures the Transmit bit of the LIN master node 112 to be 1, that is, configures the LIN master node 112 to be in the transmitting state.

When LIN master 112 is in the transmit state, state machine 111 enters the Data state. In the Data state, the state machine 111 may be configured to intercept the Data bit field of the payload in the ethernet packet, configure the Data in each Data bit field into the corresponding Data register of the LIN master node 112, and set n=n+1, where N represents the count value of the byte counter.

When n=0 in the Transmit bit, state machine 111 enters the Req state. In the Req state, the state machine 111 configures a transceiving flag bit (start Req) of the LIN master node 112, where the start Req is used to instruct the LIN master node 112 to perform transceiving actions. The LIN master 112 starts transceiving when the start req bit is set.

N= DATA LENGTH-1, the state machine 111 enters the transmit-receive state. In the transmit-receive state, the state machine 111 waits for the LIN master 112 to return an interrupt message, and enters the assembled state after receiving the interrupt message returned by the LIN master 112.

In the assembled (enCAP) state, the state machine 111 may be configured to assemble LIN data from the interrupt message returned by the LIN master 112 and feed the LIN data into the corresponding buffer 1221 in the second buffer 122 in the axi interface 120. If the interrupt message indicates normal, the state machine 111 forwards the payload splice of the interaction between the LIN master 112 and its slave (slave) to the axi interface 120. If the interrupt message indicates an exception, state machine 111 assembles error indication information from LIN master node 112 to be sent to TAXI interface 120, the error indication information indicating the exception.

In some examples, state machine 111 may be controlled to switch to a software processing state by setting a force bit (e.g., force_soft). State machine 111 jumps from the current state to the software processing state when the force bit is high. Thus, the hardware of the interface conversion device can be controlled to stop operating.

Referring to the examples of fig. 4 and 5, another exemplary operation of the interface conversion device in the embodiment of the present application is as follows:

the initialization configuration of the respective registers in the interface conversion apparatus can be performed only in the initial state and the software processing state of the state machine 111, and is not allowed to be configured at other times.

The processing state of the software, namely the LIN_CORE is controlled by the CPU, and the master node, the slave node, the rate, the check type and the like need to be configured first. In the software processing state, the state machine 111 cannot operate registers, and the CPU controls operations.

In the hardware processing state, the state machine 111 controls the judging logic circuit to read payload from buffer of the axi_if, extract relevant LIN configuration information from the corresponding position of payload, and configure lin_core so that lin_core performs data transceiving.

When the CPU configuration hardw is high, a wait state is entered. In wait state, when receiving data from TAXI_IF, it enters configuration state, and stores 96 bits of data into CTRL module register, so that the judgement logic circuit can read data from said register according to the instruction of state machine, process the data and send the processed data to LIN_CORE. Meanwhile, IF the non_empty of the TAXI_IF is received to be high in the wait state, the payload is retrieved from the buffer of the TAXI_IF, and then the payload is decomposed into flag bit information such as id, data_ length, transmit, data and the like, and the flag bit information is sequentially sent to the IP port. Then, the configuration state is entered.

In the configuration state, the state machine 111 intercepts the control fields in a message format (see fig. 3) and sequentially configures them into the LIN-Core in sequence. Here, the registers in the LIN-Core are generally 8bits, the registers support hardware control, set continuous message formats, and store flag bit information such as id, data_ length, transmit, data, etc.

In the configuration state, the LIN-Core corresponding registers are sequentially configured as shown in fig. 5, until the start_req is configured, and then the state machine 111 enters the transmit-receive state, at which time it waits for the LIN Core to return an interrupt.

If the LIN-Core interrupt is pulled high, the LIN-Core status register is read.

If the Error flag bit (Error) is high and the Error encapsulation flag bit (err_ena) of the LIN CORE Register (error_register) is high, which indicates that the Error information is encapsulated in the ethernet message, and the flag bit is low, which indicates that the Error information is not encapsulated in the ethernet message), the LIN-CORE Error Register (Error Register) is read (for storing the LIN-CORE Error information) and stored in the internal Register lin_err (i.e., the Register in the state machine 111). When err_ena is low, no read is needed.

If the completion flag (complete) is high and data is read from the interface between the LIN-Core and its slave node (i.e., transmit is 0), then the state machine 111 controls the decision logic module to read the data data_length of the LIN-Core multiple times. If complex is high and is sending data to the interface between LIN-Core and its slave node (i.e., transmit is 1), then no data need be read.

Whether the LIN-Core receives or transmits from the interface between the nodes, the state machine composes a 3-beat 32bits data and returns the data to the TAXI_IF after receiving the complete for the convenience of unified processing. Here, when the interface between the LIN-Core and its slave node is in a state of transmitting data, IF there is no return data, the data bit in the LIN payload will be filled with 0 and then transmitted to the tani_if.

After the completion of the splicing, if there is no error (i.e. the interrupt message indicates normal), the message (including the data and the corresponding LIN number and id) can be edited according to the message format (see 3.1). And (3) a packaging process: data read from the internal registers of the state machine or from the memory in the LIN unit (one of ctrl_1 to ctrl_6 in fig. 4), and lin_ NUM, complete, LIN _err, id as additional information, are sent in message format one and to the tani_if. The lin_num is a LIN number, and may also be used to identify a LIN unit, and take a fixed value. id is the bit field that is truncated from the payload from the TAXI_IF when sent to the LIN-Core. When in transmission, the information is transmitted to the TAXI_IF in parallel, and no matter which way of complex flag is set high, the message packaged in the current LIN unit is edited and transmitted to the TAXI_IF. Finally, the CRC5 value of the whole LIN payload frame is calculated, and the LIN payload frame header is put in.

IF there is an error (i.e., the interrupt message indicates an exception), the corresponding LIN unit (one of ctrl_1 to ctrl_6 in fig. 4) pulls up the wr interface signal (the wr interface signal is a flag signal for entering the software processing state) and sends the wr interface signal to the tani_if, and at the same time enters the software processing state, and the LIN-CORE is controlled by the software to process the error.

After the LIN data is sent to the axi_if, the registers in each LIN unit (ctrl_1 to ctrl_6 in fig. 4) or the state registers of the state machine therein are reset.

Fig. 6 is a schematic diagram of a computing device 500 provided by an embodiment of the application. The computing device 500 includes: the interface conversion device 100 described above. In addition, the computing device may also include a processor 510, a memory 520, a communication interface 530, and a bus 540.

It should be appreciated that the communication interface 530 in the computing device 500 shown in fig. 6 may be used to communicate with other devices.

Wherein the processor 510 may be coupled to a memory 520. The memory 520 may be used to store the program codes and data. Accordingly, the memory 520 may be a storage unit internal to the processor 510, an external storage unit independent of the processor 510, or a component including a storage unit internal to the processor 510 and an external storage unit independent of the processor 510.

Optionally, computing device 500 may also include a bus 540. The memory 520 and the communication interface 530 may be connected to the processor 510 via a bus 540. Bus 540 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, a axi bus, or the like. The bus 540 may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, only one line is shown in fig. 6, but not only one bus or one type of bus.

It should be appreciated that in embodiments of the present application, the processor 510 may employ a central processing unit (central processing unit, CPU). The processor may also be other general purpose processors, digital Signal Processors (DSP), application SPECIFIC INTEGRATED Circuits (ASIC), off-the-shelf programmable gate arrays (field programmable GATE ARRAY, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 510 may employ one or more integrated circuits for executing associated routines to perform processing such as interrupts or the like, for example, in accordance with some of the technical details of the present application.

The memory 520 may include read only memory and random access memory, and provides instructions and data to the processor 510. A portion of the processor 510 may also include non-volatile random access memory. For example, processor 510 may also store information of the device type.

In the several embodiments provided in the present application, it should be understood that the disclosed system and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

Computer program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

Note that the above is only a preferred embodiment of the present application and the technical principle applied. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, while the application has been described in connection with the above embodiments, the application is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the application, which fall within the scope of the application.

Claims

1. A method of data conversion, comprising:

receiving an Ethernet message from a TAXI bus, wherein the Ethernet message comprises a LIN number;

identifying and extracting an effective bearing part in the Ethernet message;

Storing the effective bearing part in the Ethernet message in a corresponding first buffer area according to the LIN number in the Ethernet message, so that the corresponding LIN unit can read the stored effective bearing part in the Ethernet message from the first buffer area corresponding to the LIN number.

2. The method of claim 1, wherein the first buffer comprises a plurality of buffers corresponding to LIN numbers for a plurality of corresponding LIN units to read, in parallel, the active bearer portion in the stored ethernet packet to the first buffer corresponding to the respective LIN number.

3. A method of data conversion, comprising:

receiving LIN data from a LIN unit, the LIN data comprising a LIN number;

receiving LIN control information corresponding to the LIN number from a processor interface;

Encapsulating the LIN data by using the LIN control information to obtain an LIN message; and storing the LIN message in a corresponding second buffer for transmission to a TAXI bus.

4. A method according to claim 3, characterized in that the second buffer comprises a plurality of buffers corresponding to LIN numbers for storing a plurality of LIN messages corresponding to a plurality of LIN units, respectively, according to LIN numbers for parallel transmission to a tani bus.

5. The method of claim 3 or 4, wherein the LIN data comprises at least one of:

LIN payload, error prompt;

Wherein the LIN payload comprises LIN cell state data; the error prompt information includes information indicating abnormality of the LIN unit and error prompt information indicating erroneous operation.

6. A method of data processing, comprising:

The LIN unit reads an effective bearing part in an Ethernet message stored in a first buffer area from a first buffer area of a TAXI interface; each buffer area in the first buffer area corresponds to the LIN number of the LIN unit;

the state machine of the LIN unit configures an LIN master node in the LIN unit by analyzing an effective bearing part in the Ethernet message;

and the LIN master node completes receiving and transmitting according to the configuration and LIN control information from the processor interface, and returns LIN data corresponding to the Ethernet message to the TAXI interface.

7. The method as recited in claim 6, further comprising:

determining actions to be executed by the LIN master node according to the state of a state machine;

wherein the actions include a wake-up action, a send action, and/or a receive action.

8. The method as recited in claim 7, further comprising:

and sending the state of the state machine to the LIN master node.

9. A computer readable storage medium having stored thereon program instructions, which when executed by a computer cause the computer to perform the data conversion method of any one of claims 1-2 or the data conversion method of any one of claims 3-5 or the data processing method of any one of claims 6-8.

10. A computing device, comprising:

A communication interface;

at least one processor coupled to the communication interface; and

At least one memory coupled to the processor and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform the data conversion method of any one of claims 1-5 or the data processing method of any one of claims 6-8.