CN115189339A - ESD Protection Circuit - Google Patents

Abstract

The invention provides an electrostatic protection circuit, which includes a silicon controlled rectifier element and a transistor. The thyristor rectifier includes a first end, a second end and a third end. The first end of the thyristor is coupled to the first pad. The second end of the thyristor is coupled to the second pad. The transistor includes a first terminal, a second terminal and a control terminal. The first end of the transistor is coupled to the first pad. The second end of the transistor is coupled to the second pad. The control terminal of the transistor is coupled to the third terminal of the thyristor rectifier.

Description

ESD Protection Circuit

technical field

The present invention relates to an electronic circuit, in particular to an electrostatic discharge protection circuit.

Background technique

In order to protect the integrated circuit from being damaged by electrostatic discharge phenomenon, the electrostatic protection circuit constructed on the chip has become a necessary element in the chip. In the prior art, an electrostatic protection circuit including a silicon controlled rectifier usually requires a trigger element to trigger the operation of the silicon controlled rectifier, so as to provide a path for the discharge of electrostatic charges when an electrostatic discharge event occurs, and to protect the integrated circuit. In the prior art, there are many layout ways to realize the circuit structure of the electrostatic protection circuit with the trigger element and the thyristor rectifier element. However, in these circuit structures, the transistor, which is a trigger element, usually cannot be used as a path for discharging electrostatic charges, so as to improve the electrostatic protection effect.

SUMMARY OF THE INVENTION

The invention provides an electrostatic protection circuit, which can provide a good electrostatic protection effect.

The electrostatic protection circuit of the present invention includes a silicon controlled rectifier element and a first transistor. The thyristor rectifier includes a first end, a second end and a third end. The first end of the thyristor is coupled to the first pad. The second end of the thyristor is coupled to the second pad. The first transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor is coupled to the first pad. The second terminal of the first transistor is coupled to the second pad. The control terminal of the first transistor is coupled to the third terminal of the silicon controlled rectifier element.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

FIG. 1 shows a schematic circuit diagram of an electrostatic protection circuit according to an embodiment of the present invention;

FIG. 2 shows a schematic circuit diagram of an electrostatic protection circuit according to another embodiment of the present invention.

Explanation of reference numerals

100, 200: electrostatic protection circuit;

300, 400: solder pad;

Cgd: parasitic capacitance;

I1, I2, I3, I4: current;

MN1, MP1, Q2, Q3: transistors;

R: resistor element;

SCR: silicon controlled rectifier element;

VDD, VSS: system voltage;

VG: Voltage.

Detailed ways

A number of embodiments are presented below to illustrate the present invention, however, the present invention is not limited to the exemplified embodiments. Appropriate combinations are also permitted between embodiments.

FIG. 1 shows a schematic circuit diagram of an electrostatic protection circuit according to an embodiment of the present invention. The electrostatic protection circuit 100 of this embodiment includes a silicon controlled rectifier element SCR, a first transistor MN1 and a resistor element R.

The first transistor MN1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor MN1 is coupled to the first pad 300 . The second terminal of the first transistor MN1 is coupled to the second pad 400 . The control terminal of the first transistor MN1 is coupled to the silicon controlled rectifier element SCR. The voltage of the control terminal of the first transistor MN1 is denoted as VG in FIG. 1 . The first pad 300 may be coupled to the first system voltage VDD. The second pad 400 may be coupled to the second system voltage VSS. The first system voltage VDD is greater than the second system voltage VSS. In one embodiment, the second system voltage VSS is, for example, a ground voltage.

In this embodiment, the first transistor MN1 is an N-type metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and the first terminal, the second terminal and the control terminal are respectively the drain of the transistor. pole, source and gate. A parasitic capacitance Cgd exists between the first terminal and the control terminal.

The silicon controlled rectifier element SCR includes a first end, a second end and a third end. The first end of the silicon controlled rectifier element SCR is coupled to the first pad 300 . The second end of the silicon controlled rectifier element SCR is coupled to the second pad 400 . The third terminal of the silicon controlled rectifier element SCR is coupled to the control terminal of the first transistor MN1. The silicon controlled rectifier element SCR includes a second transistor Q2 and a third transistor Q3. The second transistor Q2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor Q2 is coupled to the first pad 300 . The second terminal of the second transistor Q2 is coupled to the control terminal of the first transistor MN1. The control terminal of the second transistor Q2 is coupled to the third transistor Q3. The third transistor Q3 includes a first terminal, a second terminal and a control terminal. The first terminal of the third transistor Q3 is coupled to the control terminal of the second transistor Q2. The second terminal of the third transistor Q3 is coupled to the second pad 400 . The control terminal of the third transistor Q3 is coupled to the control terminal of the first transistor MN1.

In this embodiment, the first end of the second transistor Q2 is used as the first end of the silicon controlled rectifier element SCR. The second terminal of the third transistor Q3 serves as the second terminal of the silicon controlled rectifier element SCR. The control terminal of the third transistor Q3 serves as the third terminal of the silicon controlled rectifier element SCR. In this embodiment, the second transistor Q2 is a PNP bipolar junction transistor (Bipolar Junction Transistor, BJT), and its first terminal, second terminal and control terminal are the emitter, collector and base of the transistor, respectively . The third transistor Q3 is an NPN bipolar junction transistor, and its first terminal, second terminal and control terminal are the collector, emitter and base of the transistor, respectively.

The resistor element R includes a first end and a second end. The first terminal of the resistor element R is coupled to the control terminal of the first transistor MN1. The second end of the resistor element R is coupled to the second pad 400 .

In this embodiment, the ESD protection circuit 100 can operate in a normal operation mode and an ESD protection mode. In the normal operation mode, the first pad 300 is coupled to the first system voltage VDD, and the second pad 400 is coupled to the second system voltage VSS, such as a ground voltage. The collector and base of the third transistor Q3 are in a reverse biased state, so the second transistor Q2 is not turned on. Since the second transistor Q2 is not turned on and the voltage VG of the control terminal of the first transistor MN1 is grounded, the third transistor Q3 and the first transistor MN1 are not turned on, and no current flows through the silicon controlled rectifier SCR and the first transistor MN1 .

When an ESD event occurs, the ESD protection circuit 100 can operate in an ESD protection mode. The electrostatic discharge event includes an electrostatic discharge pulse (ESD pulse) appearing on the first bonding pad 300 , so a large amount of electrostatic charge is accumulated on the first bonding pad 300 . In the ESD protection mode, when an ESD event occurs, according to the response of the resistor element R and the parasitic capacitance Cgd, the voltage VG of the control terminal of the first transistor MN1 rises to trigger the operation of the silicon controlled rectifier SCR. That is, a potential difference occurs across the resistor element R according to the response of the resistor element R and the parasitic capacitance Cgd. When the second system voltage VSS is the ground voltage, the potential difference between the two ends of the resistor element R is the voltage VG of the control terminal of the first transistor MN1 , which is used to trigger the operation of the silicon controlled rectifier SCR.

Specifically, when the voltage VG of the control terminal of the first transistor MN1 rises, the first current I1 is generated at the control terminal of the third transistor Q3. The first current I1 flows into the control terminal of the third transistor Q3 to turn on the third transistor Q3. When the third transistor Q3 is turned on, a second current I2 is generated at the control terminal of the second transistor Q2. The second current I2 flows out of the control terminal of the second transistor Q2 to turn on the second transistor Q2. When the second transistor Q2 and the third transistor Q3 are turned on, the silicon controlled rectifier SCR is turned on, and the electrostatic charge is transferred from the first pad 300 to the second pad 400 through the silicon controlled rectifier SCR.

On the other hand, when the electrostatic charge is transferred from the first pad 300 to the second pad 400 through the silicon controlled rectifier SCR, the voltage VG of the control terminal of the first transistor MN1 continues to rise to turn on the first transistor MN1. When the first transistor MN1 is turned on, the electrostatic charge can also be transferred from the first pad 300 to the second pad 400 through the first transistor MN1 . Therefore, in this embodiment, when an electrostatic discharge event occurs, the electrostatic protection circuit 100 provides at least two transmission paths of electrostatic charges, which can provide a good electrostatic protection effect.

FIG. 2 shows a schematic circuit diagram of an electrostatic protection circuit according to another embodiment of the present invention. The electrostatic protection circuit 200 of this embodiment includes a silicon controlled rectifier element SCR, a first transistor MP1 and a resistor element R.

The first transistor MP1 includes a first terminal, a second terminal and a control terminal. The first terminal of the first transistor MP1 is coupled to the first pad 300 . The second terminal of the first transistor MP1 is coupled to the second pad 400 . The control terminal of the first transistor MP1 is coupled to the silicon controlled rectifier element SCR. In this embodiment, the first transistor MP1 is a P-type metal oxide semiconductor field effect transistor, and the first terminal, the second terminal and the control terminal thereof are the source, drain and gate of the transistor, respectively. There is a parasitic capacitance Cgd between the second terminal and the control terminal.

The silicon controlled rectifier element SCR includes a first end, a second end and a third end. The first end of the silicon controlled rectifier element SCR is coupled to the first pad 300 . The second end of the silicon controlled rectifier element SCR is coupled to the second pad 400 . The third terminal of the silicon controlled rectifier element SCR is coupled to the control terminal of the first transistor MP1. The silicon controlled rectifier element SCR includes a second transistor Q2 and a third transistor Q3. The second transistor Q2 includes a first terminal, a second terminal and a control terminal. The first terminal of the second transistor Q2 is coupled to the first pad 300 . The second terminal of the second transistor Q2 is coupled to the control terminal of the third transistor Q3. The control terminal of the second transistor Q2 is coupled to the control terminal of the first transistor MP1. The third transistor Q3 includes a first terminal, a second terminal and a control terminal. The first terminal of the third transistor Q3 is coupled to the control terminal of the second transistor Q2. The second terminal of the third transistor Q3 is coupled to the second pad 400 . The control terminal of the third transistor Q3 is coupled to the second terminal of the second transistor Q2.

In this embodiment, the first end of the second transistor Q2 is used as the first end of the silicon controlled rectifier element SCR. The second terminal of the third transistor Q3 serves as the second terminal of the silicon controlled rectifier element SCR. The control terminal of the second transistor Q2 serves as the third terminal of the silicon controlled rectifier element SCR. In this embodiment, the second transistor Q2 is a PNP type bipolar junction transistor, and its first terminal, second terminal and control terminal are the emitter, collector and base of the transistor, respectively. The third transistor Q3 is an NPN bipolar junction transistor, and its first terminal, second terminal and control terminal are the collector, emitter and base of the transistor, respectively.

The resistor element R includes a first end and a second end. The first end of the resistor element R is coupled to the first pad 300 . The second terminal of the resistor element R is coupled to the control terminal of the first transistor MP1.

In the ESD protection mode, when an ESD event occurs, according to the response of the resistor element R and the parasitic capacitance Cgd, the voltage VG of the control terminal of the first transistor MP1 drops to trigger the operation of the silicon controlled rectifier SCR. That is, a potential difference occurs across the resistor element R according to the response of the resistor element R and the parasitic capacitance Cgd. The potential difference between the two ends of the resistor element R is the difference between the first system voltage VDD and the voltage VG of the control terminal of the first transistor MP1 , which is used to trigger the operation of the silicon controlled rectifier element SCR.

Specifically, when the voltage VG of the control terminal of the first transistor MP1 drops, the third current I3 is generated at the control terminal of the second transistor Q2. The third current I3 flows out of the control terminal of the second transistor Q2 to turn on the second transistor Q2. When the second transistor Q2 is turned on, a fourth current I4 is generated at the control terminal of the third transistor Q3. The fourth current I4 flows into the control terminal of the third transistor Q3 to turn on the third transistor Q3. When the second transistor Q2 and the third transistor Q3 are turned on, the silicon controlled rectifier SCR is turned on, and the electrostatic charge is transferred from the first pad 300 to the second pad 400 through the silicon controlled rectifier SCR.

On the other hand, when the electrostatic charge is transferred from the first pad 300 to the second pad 400 through the silicon controlled rectifier SCR, the voltage VG of the control terminal of the first transistor MP1 continues to drop to turn on the first transistor MP1. When the first transistor MP1 is turned on, the electrostatic charge can also be transferred from the first pad 300 to the second pad 400 through the first transistor MP1 . Therefore, in this embodiment, when an electrostatic discharge event occurs, the electrostatic protection circuit 100 provides at least two transmission paths of electrostatic charges, which can provide a good electrostatic protection effect.

To sum up, in the embodiments of the present invention, when an electrostatic discharge event occurs, the electrostatic protection circuit can provide at least two electrostatic charge transfer paths, one of which is a transfer path including a thyristor rectifier, and the other is Include the transfer path of the trigger transistor. The silicon-controlled rectifier element is turned on by the response of the parasitic capacitance and the resistor element. The trigger transistor is turned on by generating a voltage across the resistor element due to the large current generated after the silicon controlled rectifier element is turned on. Therefore, the control voltage at the control end of the trigger transistor can trigger the thyristor rectifier element and its self to conduct, providing two transfer paths of electrostatic charge, so as to improve the effect of electrostatic protection.

It will be understood by those skilled in the art that various modifications and changes can be made in the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that this invention covers modifications and variations of this invention provided that they fall within the scope of the appended claims and their equivalents.

Claims (14)

1. An electrostatic protection circuit, comprising: The thyristor rectifier element includes a first end, a second end and a third end, wherein the first end of the thyristor rectifier element is coupled to the first pad, and the thyristor rectifier element has a the second end is coupled to the second pad; and A first transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the first pad, and the second terminal of the first transistor is coupled to connected to the second pad, and the control terminal of the first transistor is coupled to the third terminal of the silicon controlled rectifier element. 2. The electrostatic protection circuit according to claim 1, further comprising: A resistor element, the potential difference between its two ends is used to trigger the operation of the silicon-controlled rectifier element, wherein the first transistor provides a parasitic capacitance, when an electrostatic discharge event occurs, according to the resistor element and the parasitic capacitance In response, the potential difference is generated across the resistor element. 3. The electrostatic protection circuit according to claim 2, wherein the resistor element is coupled between the second end and the third end of the thyristor rectifier element, and the thyristor Rectifier components include: The second transistor includes a first end, a second end and a control end, wherein the first end of the second transistor, as the first end of the silicon-controlled rectifier element, is coupled to the first end a bonding pad, and the second terminal of the second transistor is coupled to the control terminal of the first transistor; and A third transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the second transistor, and the The second end is used as the second end of the silicon controlled rectifier element, and is coupled to the second pad, and the control end of the third transistor is used as the second end of the silicon controlled rectifier element. The third terminal is coupled to the control terminal of the first transistor. 4 . The ESD protection circuit of claim 3 , wherein when an ESD event occurs, according to the response of the resistor element and the parasitic capacitance, the voltage of the control terminal of the first transistor rises to trigger the ESD protection circuit of claim 3 . The operation of the thyristor rectifier element. 5. The ESD protection circuit according to claim 4, wherein when the voltage of the control terminal of the first transistor rises, a first current is generated at the control terminal of the third transistor and flows into the third transistor the control terminal of the transistor to turn on the third transistor. 6. The electrostatic protection circuit according to claim 5, wherein when the third transistor is turned on, a second current is generated at the control terminal of the second transistor and flows out of the control of the second transistor terminal to turn on the second transistor, wherein when the second transistor and the third transistor are turned on, the silicon controlled rectifier is turned on, and the electrostatic charge passes through the first pad through the The thyristor rectifier is transmitted to the second pad. 7. The electrostatic protection circuit of claim 6, wherein when electrostatic charge is transferred from the first pad to the second pad through the thyristor The voltage of the control terminal rises to turn on the first transistor, wherein when the first transistor is turned on, electrostatic charge is transferred from the first pad through the first transistor to the second pad. 8. The ESD protection circuit of claim 3, wherein the first transistor is an N-type metal oxide semiconductor field effect transistor, the second transistor is a PNP-type bipolar junction transistor, and the third transistor is a The transistor is an NPN type bipolar junction transistor. 9 . The electrostatic protection circuit according to claim 2 , wherein the resistor element is coupled between the first end and the third end of the thyristor rectifier element, and the thyristor Rectifier components include: The second transistor includes a first end, a second end and a control end, wherein the first end of the second transistor, as the first end of the silicon-controlled rectifier element, is coupled to the first end a bonding pad, and the control terminal of the second transistor is used as the third terminal of the silicon-controlled rectifier element, and is coupled to the control terminal of the first transistor; and A third transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the second transistor, and the The second end is used as the second end of the silicon controlled rectifier element, and is coupled to the second pad, and the control end of the third transistor is coupled to the second end of the second transistor. second end. 10. The ESD protection circuit of claim 9, wherein when an ESD event occurs, the voltage of the control terminal of the first transistor drops according to the response of the resistor element and the parasitic capacitance to trigger a The operation of the thyristor rectifier element. 11. The ESD protection circuit of claim 10, wherein when the voltage of the control terminal of the first transistor drops, a third current is generated at the control terminal of the second transistor and flows out of the second transistor the control terminal of the transistor to turn on the second transistor. 12. The electrostatic protection circuit according to claim 11, wherein when the second transistor is turned on, a fourth current is generated at the control terminal of the third transistor, and flows into the control terminal of the third transistor terminal to turn on the third transistor, wherein when the second transistor and the third transistor are turned on, the thyristor is turned on, and the electrostatic charge passes through the first pad through the The thyristor rectifier is transmitted to the second pad. 13. The electrostatic protection circuit of claim 12, wherein when electrostatic charge is transferred from the first pad to the second pad through the thyristor The voltage of the control terminal drops to turn on the first transistor, wherein when the first transistor is turned on, electrostatic charge is transferred from the first pad to the second pad through the first transistor. 14. The electrostatic protection circuit of claim 9, wherein the first transistor is a P-type metal oxide semiconductor field effect transistor, the second transistor is a PNP-type bipolar junction transistor, and the third transistor The transistor is an NPN type bipolar junction transistor.

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