CN115188769B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN115188769B CN115188769B CN202210734198.0A CN202210734198A CN115188769B CN 115188769 B CN115188769 B CN 115188769B CN 202210734198 A CN202210734198 A CN 202210734198A CN 115188769 B CN115188769 B CN 115188769B
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- 239000000758 substrate Substances 0.000 title claims abstract description 101
- 239000010410 layer Substances 0.000 claims abstract description 245
- 239000002346 layers by function Substances 0.000 claims abstract description 117
- 239000003990 capacitor Substances 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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Abstract
The application relates to an array substrate, a display panel and a display device, wherein the array substrate comprises a first functional layer, a second functional layer and an insulating layer arranged between the first functional layer and the second functional layer in an insulating way, the array substrate is provided with a plurality of transistors and a plurality of capacitors, each capacitor is electrically connected with at least one transistor, each capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is formed on the first functional layer and is arranged on at least part of the same layer as the transistors, the second electrode plate is formed on the second functional layer and is arranged on at least part of the same layer as the transistors, and the thickness of an area between the insulating layer and the second electrode plate is smaller than that of the insulating layer in the transistor area. The capacitor of the array substrate provided by the embodiment of the application can meet the capacitance requirement of the capacitor, and is simple in manufacturing process and low in cost.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel and a display device.
Background
In the prior art, an array substrate generally includes a plurality of transistors and a capacitor, and in general, for Micro LEDs, a light emitting element is controlled by using a transistor and a capacitor, a pixel circuit for driving the light emitting element generally includes a switching transistor, a driving transistor and a capacitor, and when the array substrate is in operation, the capacitor is mainly used for storing energy, when the switching transistor is selected by a Scan signal line (Scan line), a Data voltage on a Data signal line (Data line) is transferred to a gate electrode of the driving transistor, and simultaneously charges the capacitor, and when the Scan signal does not select the switching transistor, the switching transistor is turned off, and a voltage stored by the capacitor is used for driving the transistor, so as to ensure brightness of the light emitting element.
In order to ensure the capacitance requirement of the capacitor, an existing array substrate is generally provided with a metal layer for forming the polar plate of the capacitor between the layer structures of the formed transistors.
Therefore, a new array substrate, display panel and display device are needed.
Disclosure of Invention
The embodiment of the application provides an array substrate, a display panel and a display device, wherein a capacitor of the array substrate can meet the capacitance requirement of the capacitor, and the manufacturing process is simple and the cost is low.
According to the embodiment of the application, an array substrate is provided, which comprises a first functional layer, a second functional layer and an insulating layer arranged between the first functional layer and the second functional layer in an insulating way, wherein the array substrate is provided with a plurality of transistors and a plurality of capacitors, each capacitor is electrically connected with at least one transistor, each capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is formed on the first functional layer and is arranged at least partially in the same layer as the transistor, the second electrode plate is formed on the second functional layer and is arranged at least partially in the same layer as the transistor, and the thickness of an area between the first electrode plate and the second electrode plate is smaller than that of the insulating layer in the transistor area.
In another aspect, an embodiment of the present application provides a display panel, including the above array substrate, and a light emitting layer stacked on the array substrate, where the light emitting layer includes a plurality of light emitting elements, and each light emitting element is electrically connected to at least one transistor.
In still another aspect, according to an embodiment of the present application, there is provided a display device including the above display panel.
The array substrate comprises a first functional layer, a second functional layer and an insulating layer arranged between the first functional layer and the second functional layer in an insulating way, the array substrate is provided with a plurality of transistors and a plurality of capacitors, each capacitor is electrically connected with at least one transistor, each capacitor comprises a first electrode plate and a second electrode plate, and the first electrode plate is formed on the first functional layer and is arranged on at least part of the same layer as the transistors, and the second electrode plate is formed on the second functional layer and is arranged on at least part of the same layer as the transistors. That is, the first electrode plate and the second electrode plate of the capacitor are arranged in the same layer with the corresponding layer structure of the transistor, and no additional new metal layer is needed for independently forming the electrode plates of the capacitor, so that the whole manufacturing process of the array substrate is simple, and the cost is low.
And, through the thickness that makes the insulating layer be located the region between first electrode plate and the second electrode plate be less than the insulating layer and be located the regional thickness of transistor for the distance between first electrode plate and the second electrode plate is less, with the electric capacity between increase first electrode plate and the second electrode plate, simultaneously, makes the insulating layer be located the regional thickness of transistor great, can enough simplify the technology, simultaneously, can also avoid the mutual influence between the different layer structure of transistor, guarantees the performance of transistor.
Drawings
Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art pixel circuit;
FIG. 2 is a cross-sectional view of an array substrate according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a pixel circuit according to one embodiment of the application;
FIG. 4 is a cross-sectional view of an array substrate according to another embodiment of the present application;
fig. 5 is a cross-sectional view of an array substrate according to still another embodiment of the present application;
fig. 6 is a cross-sectional view of an array substrate according to still another embodiment of the present application;
fig. 7 is a cross-sectional view of an array substrate according to still another embodiment of the present application;
fig. 8 is a cross-sectional view of an array substrate according to still another embodiment of the present application;
FIG. 9 is a top view of a display panel according to one embodiment of the present application;
FIG. 10 is a cross-sectional view taken along the direction A-A in FIG. 9;
Fig. 11 is a partial cross-sectional view of a display panel of another embodiment of the present application.
Wherein:
100-an array substrate;
10-a first functional layer, 20-a second functional layer, 30-an insulating layer, 31-a groove, 40-an inorganic film layer, 50-a third functional layer and 60-a planarization layer;
110-transistor, 111-active region, 112-gate, 113-source, 114-drain;
120-capacitor, 121-first electrode plate, 122-second electrode plate;
200-light emitting layer, 210-light emitting element, X-thickness direction.
In the drawings, like parts are designated with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.
In the related art, an array substrate of a display panel generally includes a plurality of pixel circuits, each for driving at least one light emitting element to ensure a light emission requirement. In the prior art, the array substrate generally includes a plurality of transistors and capacitors, and in general, for Micro LEDs, the light emitting elements are controlled by using the transistors and the capacitors.
As shown in fig. 1, fig. 1 is a schematic diagram of a pixel circuit in the prior art.
Fig. 1 is a simplified pixel circuit, the array substrate includes a plurality of driving circuits, each pixel driving is used for driving a light emitting element, the pixel circuit includes at least two transistors, a switching transistor T2, a driving transistor T1 and a capacitor Cst, when the array substrate 100 is in operation, the capacitor Cst is mainly used for storing energy, when the switching transistor T2 is selected by a Scan signal line (Scan line), a Data voltage Vdata on a Data signal line (Data line) is transferred to a gate of the driving transistor Data, and simultaneously charges the capacitor Cst, when the Scan signal does not select the switching transistor T2, the switching transistor T2 is turned off, and a voltage stored by the capacitor T2 is used for driving the transistor T1, so as to ensure brightness of the light emitting element 210.
Transistors typically include an active region, a gate, and source and drain electrodes, the source and drain electrodes being co-layered, the active region, gate, and source electrode being layered. In order to ensure the capacitance requirement of the capacitor, an existing array substrate generally has a metal layer for forming the electrode plate of the capacitor between the layer structures of the formed transistor, for example, a metal layer is formed between the layer structures for forming the gate electrode and the source electrode and the drain electrode and used for forming one electrode plate of the capacitor.
In order to solve the technical problems, the embodiment of the application provides a novel array substrate, a capacitor of the array substrate can meet the capacitance requirement of the capacitor, and the manufacturing process is simple and the cost is low.
As shown in fig.2, fig.2 is a cross-sectional view of an array substrate according to an embodiment of the present application. The array substrate 100 provided in the embodiment of the application includes a first functional layer 10, a second functional layer 20, and an insulating layer 30 disposed between the first functional layer 10 and the second functional layer 20 in an insulating manner, the array substrate 100 includes a plurality of transistors 110 and a plurality of capacitors 120, each capacitor 120 is electrically connected to at least one transistor 110, the capacitor 120 includes a first electrode plate 121 and a second electrode plate 122, the first electrode plate 121 is formed on the first functional layer 10 and disposed at least partially on the same layer as the transistor 110, and the second electrode plate 122 is formed on the second functional layer 20 and disposed at least partially on the same layer as the transistor 110. Wherein, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness of the insulating layer 30 in the region of the transistor 110.
Alternatively, the first functional layer 10 may be an active layer and the second functional layer 20 may be a metal layer. Of course, in some embodiments, the first functional layer 10 and the second functional layer 20 may be metal layers.
Alternatively, the number of the transistors 110 included in the array substrate 100 is not particularly limited, alternatively, the number of the transistors 110 may be greater than the number of the capacitors 120, and may be specifically set according to the pixel circuit formed in the array substrate 100, for example, when the pixel circuit formed in the array substrate 100 is a 2T1C circuit, "2T1C circuit" refers to a pixel circuit including 2 transistors 110 (T) and 1 capacitor 120 (C) in the pixel circuit, i.e., the number of the transistors 110 included in the array substrate 100 may be 2 times the number of the capacitors 120 in the structure form shown in fig. 1.
As shown in fig. 3, when the pixel circuit formed on the array substrate 100 is a 7T1C circuit, the "7T1C circuit" refers to a pixel circuit including 7 transistors 110 (T1 to T7) and 1 capacitor 120 (C) among the pixel circuits. The number of the transistors 110 included in the array substrate 100 may be 7 times the number of the capacitors 120, and when T3 and T4 are the double transistors 110, the number of the transistors 110 included in the array substrate 100 may be 9 times the number of the capacitors 120, specifically, may be driven according to the form of the pixel circuit, as long as the driving requirement of the light emitting element can be satisfied.
Alternatively, when the pixel circuit formed on the array substrate 100 may be any one of a 7T2C circuit or a 9T1C circuit, the number of the transistors 110 and the number of the capacitors 120 may be set and arranged according to the form of the pixel circuit, so that the driving requirement of the light emitting element 210 of the array substrate 100 may be satisfied when the array substrate is used in a display panel.
Optionally, the number of insulating layers 30 included between the first functional layer 10 and the second functional layer 20 may be one, or two or more layers, which can satisfy the functional requirements of the capacitor 120 and the transistor 110.
Alternatively, the transistor 110 may include an active region 111, a gate electrode 112, a source electrode 113, and a drain electrode 114, the active region 111 may be formed on the first functional layer 10, the gate electrode 112 is formed on the second functional layer 20, and accordingly, the first electrode plate 121 may be disposed in the same layer as the active region 111, and the second electrode plate 122 may be disposed in the same layer as the gate electrode 112.
Alternatively, in some embodiments, the gate electrode 112 may be formed on the first functional layer 10, the source electrode 113 and the drain electrode 114 may be formed on the second functional layer 20, and accordingly, the first electrode plate 121 may be disposed on the same layer as the gate electrode 112, and the second electrode plate 122 may be disposed on the same layer as the source electrode 113 and the drain electrode 114.
Alternatively, the thickness of the insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 may be smaller than the thickness of the insulating layer 30 in the region of the transistor 110 in the thickness direction X of the array substrate by removing part of the material from the region of the insulating layer 30 corresponding to the two first electrode plates 121 and the second electrode plates 122 of the capacitor 120. Of course, in some embodiments, the thickness of the insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 may be smaller than the thickness in the region of the transistor 110 when the insulating layer is formed, so that the capacitance requirement between the first electrode plate 121 and the second electrode plate 122 and the performance requirement of the transistor 110 can be satisfied.
The array substrate 100 provided in the embodiment of the application includes a first functional layer 10, a second functional layer 20, and an insulating layer 30 insulated between the first functional layer 10 and the second functional layer 20, the array substrate 100 has a plurality of transistors 110 and a plurality of capacitors 120, each capacitor 120 is electrically connected to at least one transistor 110, the capacitor 120 includes a first electrode plate 121 and a second electrode plate 122, and since the first electrode plate 121 is formed on the first functional layer 10 and is disposed at least partially on the same layer as the transistor 110, the second electrode plate 122 is formed on the second functional layer 20 and is disposed at least partially on the same layer as the transistor 110. That is, the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 are arranged in the same layer as the corresponding layer structure of the transistor 110, and no additional new metal layer is needed to be added to form the electrode plates of the capacitor 120 alone, so that the whole manufacturing process of the array substrate 100 is simple and the cost is low.
In addition, in the thickness direction X of the array substrate 100, by making the thickness of the insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 smaller than the thickness of the insulating layer 30 in the region of the transistor 110, the distance between the first electrode plate 121 and the second electrode plate 122 is smaller, so as to increase the capacitance between the first electrode plate 121 and the second electrode plate 122, and at the same time, the thickness of the insulating layer 30 in the region of the transistor 110 is larger, which not only can simplify the process, but also can avoid the mutual influence between different layer structures of the transistor 110, and ensure the performance of the transistor 110.
As an alternative implementation manner, in the array substrate 100 provided in the embodiment of the present application, the polarity of the electric charge on the first electrode plate 121 is opposite to the polarity of the electric charge on the second electrode plate 122.
That is, the first electrode plate 121 and the second electrode plate 122 are only provided with the insulating layer 30, no other metal layer is provided, one of the first electrode plate 121 and the second electrode plate 122 is positively charged, the other is negatively charged, the first electrode plate 121 and the second electrode plate 122 are respectively provided with the same amount of heterogeneous charges, an electric field is generated between the first electrode plate 121 and the second electrode plate 122 after charging, electric energy obtained in the charging process is stored in the capacitor 120, and the discharging process causes the charged capacitor 120 to lose charges and release charges and electric energy.
According to the array substrate 100 provided by the embodiment of the application, the polarity of the charges on the first electrode plate 121 is opposite to the polarity of the charges on the second electrode plate 122, so that no other electrode plate is arranged between the first electrode plate 121 and the second electrode plate 122, and the stability of the capacitance of the first electrode plate 121 and the second electrode plate 122 is improved.
Referring to fig. 4, fig. 4 is a cross-sectional view of an array substrate according to another embodiment of the application. For an alternative implementation, in the array substrate 100 provided in the embodiment of the present application, the insulation layer 30 is provided with a groove 31 matching the shape of the second electrode plate 122, and the second electrode plate 122 is at least partially located in the groove 31.
Alternatively, the grooves 31 on the insulating layer 30 may be formed by a half tone mask process (halftone photo mask), which can satisfy the forming process of the grooves 31, and the manufacturing process is simple, thereby reducing the cost of the array substrate 100.
Alternatively, the second electrode plate 122 may be partially or entirely located in the second recess 31.
Alternatively, the shape of the recess 31 may be a circle, an ellipse, or a polygon, and when the recess is a polygon, the recess may be in a rectangular or other structural form, and may be specifically set according to the shape requirement of the second electrode plate 122.
According to the array substrate 100 provided by the embodiment of the application, the groove 31 matched with the shape of the second electrode plate 122 is formed on the insulating layer 30, so that the second electrode plate 122 can at least partially sink into the groove 31, and the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is smaller than that of the insulating layer 30 in the region where the transistor 110 is located. In the thickness direction X of the array substrate 100, the surface of the second electrode plate 122 facing the first electrode plate 121 is closer to the first electrode plate 121 to effectively increase the capacitance therebetween.
As shown in fig. 5 and 6, fig. 5 is a cross-sectional view of an array substrate according to still another embodiment of the present application, and fig. 6 is a cross-sectional view of an array substrate according to still another embodiment of the present application.
As shown in fig. 5, as an alternative implementation manner, the array substrate 100 provided in the embodiment of the present application has more than two insulating layers 30 stacked.
As shown in fig. 6, alternatively, when the grooves 31 are included, the grooves 31 may be provided in at least one insulating layer 30, and the depth of the grooves 31 may be smaller than the thickness of one insulating layer 30, although in some embodiments, the grooves 31 may be provided through one insulating layer 30, and in some other examples, the grooves 31 may be provided through at least one insulating layer 30 and extend toward the other insulating layers 30.
Alternatively, the number of insulating layers 30 provided between the first functional layer 10 and the second functional layer 20 may be two or more. Two or more insulating layers 30 are stacked on each other.
Alternatively, the grooves 31 may extend through one of the metal layers, although this is an alternative embodiment, and in some examples, the grooves 31 may extend a predetermined length through one metal layer and toward the next.
According to the array substrate 100 provided by the embodiment of the application, the number of the insulating layers 30 is more than two, so that the performance requirement of the transistor 110 can be better met, and the corresponding grooves 31 can be arranged on at least one insulating layer 30, so that the thickness of the residual insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is thinner, and the capacitance requirement between the first electrode plate 121 and the second electrode plate 122 is met.
As an alternative implementation manner, in the array substrate 100 provided in the embodiment of the present application, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms.
Alternatively, in the thickness direction X of the array substrate 100, the total thickness of the region of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms. For example, when the number of layers of the insulating layer 30 is one, the thickness of one insulating layer 30 in the region between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms, and when the number of layers of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 is two or more, the sum of the thicknesses of the respective insulating layers 30 between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms.
Optionally, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 is less than or equal to 2000 angstroms, further optionally less than or equal to 1500 angstroms, in some alternative embodiments, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 may be less than or equal to 800 angstroms, in some embodiments, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 may be less than or equal to 400 angstroms, and in the case that the conditions of the manufacturing process are satisfied and the first electrode plate 121 and the second electrode plate 122 are prevented from being shorted due to the breaking contact of the insulating layer 30, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 may be reduced as much as possible to increase the capacitance between the first electrode plate 121 and the second electrode plate 122.
As an alternative implementation, the array substrate 100 provided in the embodiment of the present application, the insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer.
Alternatively, the insulating layer 30 may include only a silicon oxide layer, and of course, the insulating layer 30 may include only a silicon nitride layer, and in some examples, the insulating layer 30 may include both a stacked silicon oxide layer and a silicon nitride layer.
As shown in fig. 2 to 7, in some alternative embodiments, the array substrate 100 provided in the foregoing embodiments of the present application includes an active region 111, a gate 112, a source 113 and a drain 114, where the active region 111 and the gate 112 are insulated by at least one insulating layer 30, and the source 113 and the drain 114 are insulated by another at least one insulating layer 30 between the gate 112 and the source 112. The gate 112 is formed on one of the first functional layer 10 and the second functional layer 20.
That is, the gate electrode 112 may be formed on the first functional layer 10 or the second functional layer 20.
When the gate electrode 112 is formed on the second functional layer 20, then the second electrode plate 122 may be disposed at the same layer as the gate electrode 112, and the first electrode plate 121 may be disposed at the same layer as the active region 111. When the gate electrode 112 is formed on the first functional layer 10, the first electrode plate 121 may be disposed on the same layer as the gate electrode 112, and then the second electrode plate 122 may be disposed on the same layer as the source electrode 113 and the drain electrode 114.
According to the array substrate 100 provided by the embodiment of the application, the grid electrode 112 is formed on one of the first functional layer 10 and the second functional layer 20, so that the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 can be arranged on the same layer as the active region 111 and the grid electrode 112, or the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 can be arranged on the same layer as the grid electrode 112, the source electrode 113 and the drain electrode 114, multiple choices can be provided for forming the capacitor 120 on the basis of reducing the manufacturing procedure of the array substrate 100, and the first electrode plate 121 and the second electrode plate 122 can be arranged adjacently, so that the distance between the first electrode plate 121 and the second electrode plate 122 is reduced as much as possible, and the capacitance of the capacitor 120 is improved, so that the functional requirement of the array substrate 100 is met.
With continued reference to fig. 2 to 6, as an alternative implementation manner, the array substrate 100 provided in the embodiment of the application has the first functional layer 10 as an active layer, the second functional layer 20 as a metal layer, the active region 111 formed on the first functional layer 10, and the gate 112 formed on the second functional layer 20.
That is, the first electrode plate 121 is disposed at the same layer as the active region 111 of the transistor 110, and the second electrode plate 122 is disposed at the same layer as the gate 112 of the transistor 110.
Alternatively, an insulating layer 30 between the active layer and the metal layer forming the gate electrode 112 is used to separate the active region 111 from the gate electrode 112, and the insulating layer 30 may be made of silicon oxide or silicon nitride material.
As shown in fig. 2, for example, when the first electrode plate 121 is disposed in the same layer as the active region 111 of the transistor 110 and the second electrode plate 122 is disposed in the same layer as the gate 112 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 may be made one.
When the insulating layer 30 is a layer, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be smaller than the thickness of the insulating layer 30 between the active region 111 and the gate 112. Of course, this is an alternative.
As shown in fig. 4, in some embodiments, a groove 31 may also be provided on the one insulating layer 30, such that the second electrode plate 122 is at least partially located within the groove 31,
It is to be understood that, when the first electrode plate 121 is disposed in the same layer as the active region 111 of the transistor 110 and the second electrode plate 122 is disposed in the same layer as the gate 112 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 may be two, and the insulating layer 30 on the side close to the first functional layer 10 may be a silicon oxide layer and the insulating layer 30 on the side close to the second functional layer 20 may be a silicon nitride layer.
As shown in fig. 5, when the insulating layers 30 are two layers, one insulating layer 30 may be formed such that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the active region 111 and the gate 112. Of course, the thickness of the two insulating layers 30 between the first electrode plate 121 and the second electrode plate 122 may be smaller than the thickness between the active region 111 and the gate electrode 112,
As shown in fig. 6, when the insulating layer 30 has two layers, it is of course also possible to provide the grooves 31 on the insulating layer 30 disposed away from the first functional layer 10, and the grooves 31 may penetrate deeply through the thickness of the insulating layer 30, or of course, may be smaller than the thickness of the insulating layer 30, and may further extend to a predetermined thickness toward the insulating layer 30 adjacent to the active region 111 on the basis of penetrating through the insulating layer 30.
Alternatively, when the first electrode plate 121 is disposed in the same layer as the active region 111 of the transistor 110 and the second electrode plate 122 is disposed in the same layer as the gate 112 of the transistor 110, the insulating layer 30 may have a thickness between the first electrode plate 121 and the second electrode plate 122 of less than or equal to 800 angstroms.
It will be appreciated that the above embodiments define that the first electrode plate 121 is disposed in common with the active region 111 of the transistor 110 and the second electrode plate 122 is disposed in common with the gate 112 of the transistor 110 as an alternative example.
Fig. 7 and 8 are cross-sectional views of an array substrate according to still another embodiment of the present application, and fig. 8 is a cross-sectional view of an array substrate according to still another embodiment of the present application. In some embodiments, the first functional layer 10 and the second functional layer 20 may be metal layers, the gate 112 is formed on the first functional layer 10, and the source 113 and the drain 114 are formed on the second functional layer 20.
That is, the first electrode plate 121 may be disposed in the same layer as the gate 112 of the transistor 110, and the second electrode plate 122 may be disposed in the same layer as the source 113 and the drain 114 of the transistor 110.
Optionally, the insulating layer 30 between the metal layer formed with the gate electrode 112 and the metal layer formed with the source electrode 113 and the drain electrode 114 is used to separate the two metal layers, and the insulating layer 30 may be made of a silicon nitride material, and of course, in some embodiments, the insulating layer 30 may also be made of a stacked material of silicon oxide and silicon nitride, so long as the capacitance requirement of the capacitor 120 can be ensured.
Illustratively, when the first electrode plate 121 is disposed in the same layer as the gate 112 of the transistor 110 and the second electrode plate 122 is disposed in the same layer as the source 113 and the drain 114 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 may be one.
As shown in fig. 7, when the insulating layer 30 is a layer, the thickness of the insulating layer 30 between the first electrode plate 121 and the second electrode plate 122 can be smaller than the thickness of the insulating layer 30 between the source electrode 113, the drain electrode 114 and the gate electrode 112. Of course, this is an alternative.
In some embodiments, as shown in fig. 8, a groove 31 may be provided on the insulating layer 30 such that the second electrode plate 122 is at least partially located in the groove 31.
The recess 31 may be formed using a half tone masking process (halftone photo mask).
It is understood that when the first electrode plate 121 is disposed in the same layer as the gate 112 of the transistor 110 and the second electrode plate 122 is disposed in the same layer as the source 113 and the drain 114 of the transistor 110, the number of insulating layers 30 between the first functional layer 10 and the second functional layer 20 may be two, and one of the two insulating layers 30 may be a silicon nitride layer and the other one may be a silicon oxide layer.
When the insulating layers 30 are two layers, one insulating layer 30 can be manufactured such that the thickness between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness between the gate 112 and the source 113 and the drain 114. Of course, the thickness of the two insulating layers 30 between the first electrode plate 121 and the second electrode plate 122 may be smaller than the thickness between the gate 112 and the source 113 and the drain 114.
Of course, when the insulating layer 30 is two layers, the grooves 31 may be further disposed on the insulating layer 30 disposed away from the first functional layer 10, and the grooves 31 may penetrate through the thickness of the insulating layer 30, or of course, may be smaller than the thickness of the insulating layer 30, and may further extend to a predetermined thickness toward the insulating layer 30 near the active region 111 on the basis of penetrating through the insulating layer 30.
Alternatively, when the first electrode plate 121 is disposed in the same layer as the gate 112 of the transistor 110, the second electrode plate 122 is disposed in the same layer as the source 113 and the drain 114 of the transistor 110, and the insulating layer 30 may be less than or equal to 400 angstroms in thickness between the first electrode plate 121 and the second electrode plate 122.
With continued reference to fig. 2 and fig. 4 to fig. 8, as an alternative embodiment, the array substrate 100 provided in the foregoing embodiments of the present application further includes an inorganic film layer 40, a third functional layer 50 and a planarization layer 60, where the third functional layer 50 is a metal layer, the inorganic film layer 40 is disposed between the second functional layer 20 and the third functional layer 50 in an insulating manner, and the planarization layer 60 is disposed on a side of the third functional layer 50 facing away from the second functional layer 20.
Alternatively, the planarization layer 60 may be an organic film layer.
Optionally, the third functional layer 50 may be used to form a power trace, and at the same time, part of the third functional layer 50 may be patterned according to the source electrode 113 and the drain electrode 114 to form a metal block where the source electrode 113 and the drain electrode 114 are connected through a via hole, so that the depth of the via hole when the source electrode 113 or the drain electrode 114 is electrically connected with the light emitting element 210 when the array substrate 100 is used in a display panel can be reduced, and the connection reliability is ensured.
Since the planarization layer 60 of the array substrate 100 in the prior art is generally located between the second functional layer 20 and the third functional layer 50, and the inorganic film layer 40 is located on the side of the third functional layer 50 facing away from the second functional layer 20, since the planarization layer 60 is an organic film layer, the thickness of the planarization layer is thicker, and the thickness of the inorganic film layer 40 is thinner, the inorganic film layer 40 of the array substrate 100 in the prior art cannot completely cover the third functional layer 50, resulting in a problem of low reliability of the array substrate 100.
In the array substrate 100 according to the embodiment of the present application, the inorganic film layer 40 is disposed between the second functional layer 20 and the third functional layer 50 in an insulating manner, and the planarization layer 60 is disposed on a side of the third functional layer 50 facing away from the second functional layer 20. The original process route of the array substrate 100 is changed, and the planarization layer 60 with good fluidity and thicker film layer is arranged on one side of the third functional layer 50, which is away from the second functional layer 20, so that the coverage rate of the third functional layer 50 can be ensured, and the reliability of the array substrate 100 is improved.
It can be appreciated that, in the array substrate 100 provided in the embodiment of the present application, the third functional layer 50 may be disposed to facilitate formation of the power trace, and the like, and in some embodiments, the power trace may be disposed on the second functional layer, and the like, so long as the performance requirement of the array substrate 100 can be ensured.
As shown in fig. 9 to 11, another aspect of the embodiment of the present application further includes a display panel including the above-mentioned array substrate 100 and a light emitting layer 200, where the light emitting layer 200 is stacked on the array substrate 100, and the light emitting layer 200 includes a plurality of light emitting elements 210, and each light emitting element 210 is electrically connected to at least one transistor 110.
The display panel provided by the embodiment of the application comprises the array substrate 100 provided by each embodiment, so that the first electrode plate 121 and the second electrode plate 122 of the capacitor 120 are arranged in the same layer with the corresponding layer structure of the transistor 110, no additional new metal layer is needed for separately forming the electrode plate of the capacitor 120, and the whole manufacturing process of the array substrate 100 is simple and the cost is low. Moreover, the thickness of the insulating layer 30 in the area between the first electrode plate 121 and the second electrode plate 122 is smaller than the thickness of the insulating layer 30 in the area of the transistor 110, so that the distance between the first electrode plate 121 and the second electrode plate 122 is smaller, the capacitance between the first electrode plate 121 and the second electrode plate 122 is increased, meanwhile, the thickness of the insulating layer 30 in the area of the transistor 110 is larger, the process can be simplified, meanwhile, the mutual influence between different layer structures of the transistor 110 can be avoided, the performance of the transistor 110 is ensured, and the uniformity of the display panel in display is ensured.
In still another aspect, an embodiment of the present application further includes a display device, including the display panel provided in each embodiment, where display uniformity is good.
While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the respective embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions falling within the scope of the claims.
Claims (12)
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| CN110034132B (en) * | 2019-06-12 | 2019-10-29 | 成都京东方光电科技有限公司 | A kind of array substrate, display panel and display device |
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