CN115172359B - Semiconductor device and layout structure and manufacturing method thereof - Google Patents
Semiconductor device and layout structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN115172359B CN115172359B CN202210589151.XA CN202210589151A CN115172359B CN 115172359 B CN115172359 B CN 115172359B CN 202210589151 A CN202210589151 A CN 202210589151A CN 115172359 B CN115172359 B CN 115172359B
- Authority
- CN
- China
- Prior art keywords
- transistor
- gallium nitride
- gate
- layout structure
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 116
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 82
- 238000005070 sampling Methods 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 11
- 238000004804 winding Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000004021 metal welding Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- -1 fluoride ions Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
一种半导体装置及其版图结构、制作方法。所述版图结构包括：集成在氮化镓衬底上的第一晶体管、第二晶体管及第三晶体管，以及集成在所述氮化镓衬底内的启动电阻；所述第二晶体管与第一晶体管同时通断，并通过所述第一晶体管的源端输出采样信号；所述第三晶体管在上电期间通过启动电阻控制所述第三晶体管的通断；其中，所述启动电阻是在所述氮化镓衬底内的非有源区绕制而成的。采用上述方案，可以在氮化镓衬底上集成具有电流采样和启动功能的半导体装置，从而改善具有电流采样和启动功能的半导体装置的性能。
A semiconductor device and its layout structure and manufacturing method. The layout structure includes: a first transistor, a second transistor and a third transistor integrated on a gallium nitride substrate, and a startup resistor integrated in the gallium nitride substrate; the second transistor is turned on and off at the same time as the first transistor, and a sampling signal is output through the source end of the first transistor; the third transistor controls the on and off of the third transistor through the startup resistor during power-on; wherein the startup resistor is wound in a non-active area in the gallium nitride substrate. By adopting the above scheme, a semiconductor device with current sampling and startup functions can be integrated on a gallium nitride substrate, thereby improving the performance of the semiconductor device with current sampling and startup functions.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a layout structure thereof and a manufacturing method thereof.
Background
A semiconductor device having current sampling and starting functions generally includes a switching transistor, a sampling transistor, a starting transistor, and a starting resistor. The control circuit controls the voltage of the gate terminal of the switching transistor, so that the alternating voltage can be converted into direct voltage. The gate terminal power supply of the sampling transistor is controlled by the control circuit, so that the current of the sampling transistor can be sampled, and further, according to a current sampling result, the gate terminal voltage of the starting transistor is controlled by the starting resistor, and the functions of charging an external capacitor and the like can be realized.
Existing semiconductor devices with current sampling and starting functions are typically integrated on the same substrate. At this time, the starting resistor is wound on the voltage-resistant region of the transistor, and simultaneously plays a role in optimizing the surface electric field of the voltage-resistant region.
However, the semiconductor device with the current sampling and starting functions is difficult to integrate on the gallium nitride substrate due to the limitation of the starting resistor, and the performance of the semiconductor device cannot be improved by utilizing the characteristics of low characteristic on-resistance and high operating frequency of the gallium nitride.
Disclosure of Invention
The invention aims to integrate a semiconductor device with current sampling and starting functions on a gallium nitride substrate so as to improve the performance of the semiconductor device with current sampling and starting functions.
In order to solve the problems, the embodiment of the invention provides a layout structure of a semiconductor device, which comprises a first transistor, a second transistor and a third transistor integrated on a gallium nitride substrate, and a starting resistor integrated in the gallium nitride substrate;
The drain end of the first transistor, the drain end of the second transistor and the drain end of the third transistor are connected, and the gate end of the first transistor is connected with the gate end of the second transistor;
One end of the starting resistor is connected with the drain end of the third transistor, and the other end of the starting resistor is connected with the gate end of the third transistor;
the starting resistor is wound in an inactive area in the gallium nitride substrate.
The embodiment of the invention also provides a semiconductor device, which comprises a first transistor, a second transistor, a third transistor, a current sampling unit, a starting unit and a starting resistor, wherein the drain end of the first transistor, the drain end of the second transistor and the drain end of the third transistor are connected, and the gate end of the first transistor is connected with the gate end of the second transistor;
one end of the starting resistor is connected with the drain end of the third transistor, and the other end of the starting resistor is connected with the gate end of the third transistor;
the current sampling unit is connected with the first transistor and the second transistor, and is used for sampling the source end current of the second transistor and controlling the on-off of the first transistor according to the sampling result;
The starting unit is connected with the third transistor and used for forming a negative feedback loop with a starting resistor to control the on-off of the third transistor;
The semiconductor device comprises at least one of a first voltage clamping unit and a second voltage clamping unit, wherein one end of the first voltage clamping unit is connected with the drain end of the first transistor and the drain end of the second transistor, the other end of the first voltage clamping unit is connected with the gate end of the first transistor and the gate end of the second transistor and is used for clamping the gate end voltage of the first transistor and the gate end voltage of the second transistor, one end of the second voltage clamping unit is connected with the source end of the third transistor, and the other end of the second voltage clamping unit is connected with the gate end of the third transistor and is used for clamping the gate end voltage of the third transistor.
The embodiment of the invention also provides a manufacturing method of the layout structure, which is used for manufacturing the layout structure of the semiconductor device, and is characterized in that the manufacturing method of the first layout structure comprises the following steps:
Providing the gallium nitride substrate;
Forming the starting resistor in an inactive region in the gallium nitride substrate;
the first transistor, the second transistor, and the third transistor are formed on the gallium nitride substrate.
The embodiment of the invention also provides a chip, which comprises the layout structure of the semiconductor device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
By applying the scheme of the invention, the starting resistor is wound in the non-active area in the gallium nitride substrate, and the resistivity of the gallium nitride substrate is far higher than that of the metal layer on the surface of the gallium nitride substrate, so that the starting resistor with high resistance can be realized, and the semiconductor device with current sampling and starting functions can be integrated on the gallium nitride substrate.
Drawings
FIG. 1 is a partial circuit block diagram of a switching power supply chip;
FIG. 2 is a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first layout structure of a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first layout structure of another semiconductor device according to an embodiment of the present invention;
FIG. 5 is a schematic view of a first layout structure of yet another semiconductor device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a first layout structure of yet another semiconductor device according to an embodiment of the present invention;
FIG. 7 is a schematic view of a first layout structure of yet another semiconductor device according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a first layout structure of another semiconductor device according to an embodiment of the present invention;
FIG. 9 is an enlarged schematic view of a part of the structure of the W area in FIG. 3;
FIG. 10 is a schematic cross-sectional view taken along line BB' in FIG. 9;
fig. 11 is a schematic cross-sectional view taken along line AA' in fig. 3.
Detailed Description
Fig. 1 is a conventional semiconductor device with current sampling and starting functions.
Referring to fig. 1, a local circuit structure of a switching power supply chip includes a switching transistor M1, a sampling transistor M2, a start transistor M3, a start resistor R1, and a sampling resistor R2. Wherein SW is the high voltage terminal. GATE is the drive signal output. SOUCE is the source terminal of the first transistor M1. SENSE is the source of sampling transistor M2, connected to sampling resistor R2 and then to ground, and input to control circuit 103 as a sampling signal. The control circuit 103 includes a start-up circuit 101 and a pulse width modulation circuit 102.
In the power-on process, the voltage of the gate terminal of the starting transistor M3 is slowly increased, when the voltage difference between the voltage of the gate terminal and the voltage of the source terminal of the starting transistor M3 is larger than the threshold voltage of the starting transistor M3, the starting transistor M3 is conducted and charges the external capacitor through the starting circuit 101, meanwhile, a negative feedback loop is formed by devices in the starting circuit 101 and the starting resistor R1 to control the voltage of the gate terminal of the driving transistor M3, so that the charging current of the starting transistor M3 to the outside is stabilized, and the influence of the change of the voltage of the first-stage drain terminal due to the change of the voltage on the external capacitor is avoided. The pwm circuit 102 may receive the sampling signal and generate a corresponding driving signal based on the sampling signal to control the switching of the switching transistor M1 and the sampling transistor M2.
The conventional circuit structure shown in fig. 1 generally integrates a transistor and a start-up resistor on the same substrate and integrates a control circuit 103 on another layout when the layout is fabricated. The starting resistor is wound above the voltage-resistant area of the transistor, and meanwhile, the function of optimizing the surface electric field of the voltage-resistant area is achieved. .
Gallium nitride semiconductor devices, i.e., semiconductor devices implemented on gallium nitride substrates. Because the gallium nitride material has the characteristics of low characteristic on-resistance and high working frequency, the semiconductor device realized on the gallium nitride substrate can obviously improve the power conversion efficiency compared with a silicon-based semiconductor device.
However, when a layout is manufactured in a traditional way, because the existing gallium nitride technology lacks a substrate surface high-resistance material which is matched with the technology, high resistance is difficult to form above a substrate and a voltage-resistant area, and meanwhile, the traditional transistor layout structure cannot be matched with a gallium nitride substrate.
Therefore, how to provide a layout structure of a gallium nitride semiconductor device with current sampling and starting functions becomes a problem to be solved urgently.
In order to solve the problem, the invention provides a layout structure of a semiconductor device, in the layout structure, the starting resistor is wound in an inactive area in a gallium nitride substrate instead of being formed on the surface of the gallium nitride substrate, and the requirement of the starting resistor can be met because the resistivity of the gallium nitride substrate is far higher than that of a metal layer on the surface of the gallium nitride substrate, so that the semiconductor device with current sampling and starting functions is formed on the gallium nitride substrate.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. Referring to fig. 2, the apparatus may include a first transistor T1, a second transistor T2, a third transistor T3, a current sampling unit 21, a start-up unit 22, and a start-up resistor R1.
The drain terminal of the first transistor T1, the drain terminal of the second transistor T2 and the drain terminal of the third transistor T3 are connected, and the gate terminal of the first transistor T1 is connected with the gate terminal of the second transistor T2;
One end of the starting resistor R1 is connected with the drain end of the third transistor T3, and the other end of the starting resistor R1 is connected with the gate end of the third transistor T3;
The current sampling unit 21 is connected to the first transistor T1 and the second transistor T2, and is configured to sample a source current of the second transistor T2, and control on/off of the first transistor T1 according to a sampling result;
the starting unit 22 is connected to the third transistor T3, and is configured to form a negative feedback loop with the starting resistor R1 to control on/off of the third transistor T3.
The high voltage terminal SW is connected to drain terminals of the first transistor T1, the second transistor T2 and the third transistor T3. The source terminal of the first transistor T1 is grounded. The first transistor T1 and the second transistor T2 are turned on and off simultaneously.
The current sampling unit 21 includes a sampling resistor R2 and a sampling circuit 211. The source terminal of the second transistor T2 is grounded through the sampling resistor R2, and outputs a sampling signal to the sampling circuit 211. The semiconductor device may further include a driving unit 23. The driving unit 23 is connected to gate terminals of the first transistor T1 and the second transistor T2 to output corresponding driving signals according to the sampling result.
The third transistor T3 controls the on/off of the third transistor T3 through the start resistor R1 during power-up. Specifically, during the power-up process of the high voltage end SW, the gate voltage of the third transistor T3 is gradually increased, the third transistor T3 is turned on and then charges the control circuit through the start-up unit 22, and the start-up unit 22 forms a negative feedback loop through the start-up resistor R1 to control the gate voltage of the third transistor T3 so as to stabilize the charging current. After the start-up is completed, the start-up unit 22 will reduce the gate terminal voltage of the third transistor T3, thereby turning off the transistor and reducing the power consumption of the system.
In the semiconductor device, the gate terminals of the first transistor T1 and the second transistor T2 are connected, so that the first transistor T1 and the second transistor T2 can be turned on or off simultaneously, which is beneficial to improving the sampling precision. And the area of the circuit structure is small, which is beneficial to reducing the circuit cost and is widely applied to switching power supplies. In addition, since the semiconductor device has both the current sampling unit 21 and the starting unit 22, the current sampling and starting functions can be simultaneously realized.
In an embodiment of the present invention, the semiconductor device may further include at least one of a first voltage clamping unit 24 and a second voltage clamping unit 25. Wherein:
The first voltage clamping unit 24 has one end connected to the drain terminal of the first transistor T1 and the drain terminal of the second transistor T2, and the other end connected to the gate terminal of the first transistor T1 and the gate terminal of the second transistor T2, and is configured to clamp the gate terminal voltage of the first transistor T1 and the gate terminal voltage of the second transistor T2.
The second voltage clamping unit 25 has one end connected to the source terminal of the third transistor T3, and the other end connected to the gate terminal of the third transistor T3, and is configured to clamp the gate terminal voltage of the third transistor T3.
By providing the first voltage clamping unit 24 and the second voltage clamping unit 25, clamping can be performed after the gate voltages of the first transistor T1 to the third transistor T3 reach the driving voltage, thereby protecting the transistor gate from breakdown and improving the reliability of the semiconductor device.
The semiconductor device may be provided with only one voltage clamping unit 24, or only the second voltage clamping unit 25, or may be provided with both the first voltage clamping unit 24 and the second voltage clamping unit 25. It is understood that the reliability of the semiconductor device can be improved to some extent when only one voltage clamping unit is provided.
In a specific implementation, the transistor and the start-up resistor of the semiconductor device may be integrated on a transistor chip, and the control units of the semiconductor device may be integrated on a control chip. The transistor chip has a first layout structure, and the control signal has a second layout structure. Therefore, the layout structure of the semiconductor device provided by the embodiment of the invention comprises the first layout structure. In some embodiments, the layout structure of the semiconductor device may further include a second layout structure. The first layout structure is described in detail below:
in a specific implementation, the first layout structure comprises a first transistor, a second transistor and a third transistor which are integrated on the gallium nitride substrate, and a starting resistor integrated in the gallium nitride substrate. Wherein:
The drain end of the first transistor, the drain end of the second transistor and the drain end of the third transistor are connected, and the gate end of the first transistor is connected with the gate end of the second transistor;
One end of the starting resistor is connected with the drain end of the third transistor, and the other end of the starting resistor is connected with the gate end of the third transistor;
the starting resistor is wound in an inactive area in the gallium nitride substrate.
Because the resistivity of the gallium nitride substrate is far higher than that of the metal layer on the surface of the gallium nitride substrate, when the starting resistor is arranged in the gallium nitride substrate, the requirement of the starting resistor can be met, the starting resistor with high resistance is realized, and the semiconductor device with current sampling and starting functions is formed on the gallium nitride substrate.
In a specific implementation, the distribution of the first transistor, the second transistor, the third transistor and the start resistor on the first layout structure is not limited, as long as the three transistors maintain the above electrical connection relationship.
In an embodiment, referring to fig. 3, the first to third transistors may be sequentially arranged in the X direction. Note that in fig. 3, only the third transistor T3, and the source terminal 332 of the second transistor are identified. The second transistor shares the gate terminal and the drain terminal with the first transistor, so that the drain terminal of the second transistor is identical to the drain terminal of the second transistor except for the third transistor T3, and the gate terminal of the second transistor is identical to the gate terminal of the second transistor. Except for the source terminal of the third transistor T3 and the source terminal 332 of the second transistor, the remaining source terminals are all the source terminals of the first transistor.
As shown in fig. 3, the drain terminal of the first transistor, the drain terminal of the second transistor, and the drain terminal of the third transistor T3 are all connected to the drain terminal land 31. The gate terminal of the first transistor and the gate terminal 322 of the second transistor are both connected to the first gate terminal land 32 a. The gate terminal of the third transistor is connected to the second gate terminal land 32 b. The source of the first transistor is connected to the first source pad 33a, the source 332 of the second transistor is connected to the second source pad 33b, and the source of the third transistor T3 is connected to the third source pad 33 c. The periphery of the first layout structure is provided with a cut-off ring 34, which is used for grounding the corresponding port, preventing the accumulated charges from damaging the transistors in the cut-off ring 34 and protecting the transistors in the cut-off ring 34.
The drain terminal welding area, the gate terminal welding area and the source terminal welding area are called as metal welding areas of layout structures, namely pad, and are used for realizing external connection of corresponding ports. Specifically, the drain terminal bonding area 31 is used for implementing external connection of the source terminal of the transistor. The first gate terminal bonding area 32a and the second gate terminal bonding area 32b are used for realizing external connection of the gate terminal of the transistor. The first source terminal bonding pad 33a, the second source terminal bonding pad 33b, and the third source terminal bonding pad 33c are used to realize the external connection of the source terminal of the transistor.
In another embodiment of the present invention, referring to fig. 4, the second transistor, the first transistor and the third transistor T3 are sequentially arranged along the X direction. At this time, the second transistor and the third transistor T3 are distributed on the left and right sides of the first transistor, and accordingly, the first gate terminal pad 32a and the second source terminal pad 33b are changed accordingly. The connection relationship among the second transistor, the first transistor and the third transistor T3 is described above with reference to fig. 3, and will not be repeated here.
In still another embodiment of the present invention, referring to fig. 5, the second transistor and the third transistor T3 may be distributed along the Y direction, i.e., up and down. The connection relationship among the second transistor, the first transistor and the third transistor T3 is described above with reference to fig. 3, and will not be repeated here.
In an implementation, an active region of a transistor includes a drain terminal and a source terminal of the transistor. The active region of the transistor is located on the substrate. The regions between the transistors are inactive regions, the inactive regions between the transistors being located within the substrate.
The source terminals of the second transistor and the third transistor can be located at any position in the active region, and the positions of the corresponding source terminal welding regions also change correspondingly. For example, referring to fig. 3, the second source terminal pad 33b and the third source terminal pad 33c are located on the same side of the first source terminal pad 33 a. Referring to fig. 4, a second source terminal bonding pad 33b and a third source terminal bonding pad 33c are positioned at both sides of the first source terminal bonding pad 33 a.
In a specific implementation, the starting resistor is formed by winding an inactive region in the gallium nitride substrate, and specifically, the position of the inactive region in the gallium nitride substrate is not limited, so long as the starting resistor is formed by winding the inactive region in the gallium nitride substrate.
In an embodiment of the present invention, the inactive region in the gallium nitride substrate may include an inactive region near the transistor region in the gallium nitride substrate, that is, an inactive region in the gallium nitride substrate except for an inactive region under the metal bonding region in the region surrounded by the stop ring. The inactive region near the transistor region includes both inactive regions between transistors and inactive regions outside the transistor region and within the cut-off ring.
For example, referring to fig. 3 to 5, the start-up resistor 35 is entirely wound around the inactive region near the transistor region. One end of the start resistor 35 is connected to the drain terminal 313 of the third transistor, and the other end is connected to the gate terminal 323 of the third transistor.
In another embodiment of the present invention, the inactive region in the gallium nitride substrate may include an inactive region under a metal bonding region, where the metal bonding region may be at least one of a drain bonding region, a gate bonding region, and a source bonding region, which is not limited herein. Because the non-active area under the metal welding area in the substrate belongs to a part of the first layout structure and does not occupy extra area, when the starting resistor is wound on the non-active area under the metal welding area, the starting resistor can be formed without extra area, the area of the first layout structure is effectively reduced, and the cost is reduced.
Taking the distribution of transistors in fig. 4 as an example, referring to fig. 6, the start-up resistor 35 may be entirely wound around the inactive region below the first source terminal pad 33 a. At this time, the start resistor 35 may be connected to the drain terminal of the first transistor, and the other end thereof is connected to the third source terminal pad 33c, and thus to the source terminal of the third transistor.
In yet another embodiment of the present invention, the inactive region in the gallium nitride substrate may include both an inactive region near the transistor region and an inactive region below the metal bonding region. Because the part of the starting resistor is wound in the non-active area below the metal welding area, compared with the part of the starting resistor which is completely wound in the non-active area near the transistor area, the area of the first layout structure is reduced to a certain extent, and the cost is reduced.
Taking the distribution of the transistors in fig. 3 as an example, referring to fig. 7, the start resistor 35 may be partially wound under the drain terminal pad 31 in the inactive region, and partially wound under the first and second gate terminal pads 32a and 32b, the first and second source terminal pads 33a and 33b, and the third source terminal pad 33 c. The two parts are connected via an inactive region near the transistor area.
Taking the distribution of the transistors in fig. 4 as an example, referring to fig. 8, the on-resistance 35 may be formed by winding an inactive region near the transistor region and an inactive region below the metal bonding region.
In a specific implementation, since the metal layer is provided on the surface of the gallium nitride substrate, when the transistor active region is formed on the gallium nitride substrate, the semiconductor material forming the active region will form non-rectifying contact, i.e. ohmic contact, when contacting with the surface metal layer.
In an embodiment of the invention, the ohmic contact of the drain terminal of the third transistor is disconnected with the ohmic contact of the drain terminal of the first transistor to form an ohmic contact disconnection area, the drain terminal of the third transistor is connected with the drain terminal of the first transistor through surface metal, and the gate terminal of the first transistor is connected with the gate terminal of the second transistor through the ohmic contact disconnection area.
Taking the distribution of transistors in fig. 3 as an example, fig. 9 is a partial enlarged view of the W region in fig. 3. Referring to fig. 9, the ohmic contact 313a of the drain terminal of the third transistor is disconnected from the ohmic contact 311a of the drain terminal of the first transistor to form an ohmic contact disconnection region. The third transistor drain terminal 313 is connected to the first transistor drain terminal 311 through the surface metal layer s1, and the gate terminal 321 of the first transistor is connected to the gate terminal 322 of the second transistor through the ohmic contact disconnection region.
Since the gate terminal 321 of the first transistor is connected to the gate terminal 322 of the second transistor, the first transistor and the second transistor can be simultaneously turned on or off, and the sampling accuracy is improved.
Fig. 10 is a schematic cross-sectional view taken along line BB' in fig. 9. Referring to fig. 10, the gallium nitride substrate may include a second substrate layer 110, a second substrate layer 120, and a third substrate layer 130. Wherein the second substrate layer 120 is located above the second substrate layer 110, the third substrate layer 130 is located above the second substrate layer 120, and the third substrate layer 130 is provided with first to third transistors.
In a specific implementation, the material of the first substrate layer may be silicon, sapphire, silicon carbide, or gallium nitride (GaN). The material of the second substrate layer 120 may be gallium nitride, and the material of the third substrate layer 130 may be aluminum gallium nitride (AlGaN).
The second substrate layer 120 is a high-resistance layer of a gallium nitride substrate. The interface between the second substrate layer 120 and the third substrate layer 130 is called a two-dimensional electron gas layer, and the two-dimensional electron gas layer not only can conduct electricity, but also is close to the high-resistance layer of the gallium nitride substrate, so that the requirement of starting resistivity can be met. Therefore, the starting resistor is generally disposed at the interface between the second substrate layer 120 and the third substrate layer 130 (as shown in fig. 11), so as to meet the use requirement of the starting resistor. The starting resistor, also called a two-dimensional electron gas resistor, or an epitaxial resistor, can drive the gate end of the third transistor, and the resistivity basically meets the requirement.
The epitaxial resistor is used as the starting resistor, so that the epitaxial resistor can be realized without additional process flow, and the process is effectively simplified. Of course, in other embodiments, the starting resistor may be other resistor, which is not limited herein.
In implementations, referring to fig. 9 and 10, the inactive region 140 between transistors may serve as an isolation structure between transistors for preventing potential and current from interfering with each other, such that electrical isolation between transistors and the firing resistor is achieved. Non-active regions may be formed between the transistors by ion implantation into the gallium nitride substrate. The implanted ions are not limited as long as they can perform an isolating function, such as fluoride ions. The depth of the isolation structure may be set according to actual needs, for example, the depth of the isolation structure may be greater than the thickness of the third substrate layer, but less than the sum of the thicknesses of the second substrate layer and the third substrate layer.
In a specific implementation, the starting resistor may be spiral and distributed in the same plane, as shown in fig. 8. Of course, other shapes are possible and are not limited herein.
In a specific implementation, the resistivity of the starting resistor is related to the width of the windings and the composition of the metallic aluminum within the gallium nitride substrate. Wherein the composition of the metallic aluminum in the gallium nitride substrate, namely the composition of the metallic aluminum in the third substrate layer. At the same time, the substrate aluminum composition and winding width can be varied to meet different requirements for starting resistance and transistor characteristics. The winding width of the resistor can be proportional to the winding number of turns, taking the spiral distribution of the resistor as an example.
In an embodiment of the present invention, in a specific implementation, the size of the second transistor may be set smaller than the size of the first transistor, so that when the second transistor is sampled, a sampling current value is smaller, but a larger driving current can be output to the first transistor through the current sampling unit, and a system loss can be reduced by sampling a smaller current.
In a specific implementation, the third transistor may be sized smaller than the first transistor. The third transistor is used as a starting transistor, and the control chip is started only in a short time enough for the current capability, so that a large-size transistor is not needed.
In a specific implementation, at least one of the first transistor, the second transistor and the third transistor may be an enhancement type lateral high voltage transistor. Preferably, the first transistor, the second transistor and the third transistor are all enhancement type lateral high-voltage transistors. Because the enhanced lateral high-voltage transistor has the characteristic of positive-voltage driving of the grid electrode, the first transistor, the second transistor and the third transistor are arranged as the enhanced lateral high-voltage transistor, so that the first layout structure can be simplified, and an additional common-source common-grid (cascode) structure is not needed.
In an implementation, the current sampling unit and the starting unit may be integrated on a control chip, the chip having a second layout structure. In the second layout structure, the specific layout structures of the current sampling unit and the starting unit are not limited, and can be set by a person skilled in the art according to actual conditions.
In an embodiment of the present invention, the transistor chip may further include at least one of a first voltage clamping unit and a second voltage clamping unit.
One end of the first voltage clamping unit is connected with the drain end of the first transistor and the drain end of the second transistor, and the other end of the first voltage clamping unit is connected with the gate end of the first transistor and the gate end of the second transistor and is used for clamping the gate end voltage of the first transistor and the gate end voltage of the second transistor;
And one end of the second voltage clamping unit is connected with the source end of the third transistor, and the other end of the second voltage clamping unit is connected with the gate end of the third transistor and is used for clamping the gate end voltage of the third transistor.
In an implementation, the first voltage clamping unit and the second voltage clamping unit may both belong to a first layout structure, that is, are integrated on a gallium nitride substrate. The integrated circuit is integrated on a gallium nitride substrate, so that the complexity of a control circuit can be reduced, and the clamping effect is improved.
In other embodiments, the first voltage clamping unit and the second voltage clamping unit may also be located on the control chip, that is, integrated on the substrate corresponding to the control chip, which is not limited herein.
From the above, the layout structure in the embodiment of the invention has the functions of current sampling and starting and is easy to realize. The semiconductor device realized on the gallium nitride substrate can effectively improve the power conversion efficiency with respect to the silicon-based semiconductor device. And, when the starting resistor is partially or entirely disposed in the inactive region under the bonding region, the cost can be effectively reduced.
In order to enable those skilled in the art to better understand and implement the present invention, the following describes in detail the manufacturing method and chip corresponding to the layout.
The embodiment of the invention provides a manufacturing method of a layout structure, which can be used for manufacturing the layout structure of any semiconductor device. Specifically, the manufacturing method of the first layout structure comprises the following steps:
and step A1, providing the gallium nitride substrate.
In an implementation, referring to fig. 10, the gallium nitride substrate may include a first substrate layer 110, a second substrate layer 120, and a third substrate layer 130. The material of the first substrate layer 110 may be silicon, sapphire, silicon carbide, or gallium nitride (GaN). The material of the second substrate layer 120 may be gallium nitride, and the material of the third substrate layer 130 may be aluminum gallium nitride (AlGaN).
The interface between the second substrate layer 120 and the third substrate layer 130, which is called a two-dimensional electron gas layer, can not only conduct electricity, but also have higher resistivity, and can basically meet the requirement of starting resistivity.
In other embodiments, the gallium nitride substrate may have other structures as long as gallium nitride is included.
And step A2, forming the starting resistor in an inactive area in the gallium nitride substrate.
In implementations, the on-resistance may be formed at the same time that the inactive region is formed within the gallium nitride substrate. After forming the start-up resistor, the non-active region between the transistors is used as an isolation structure between the transistors. Under the isolation effect of the isolation structure, the resistor is started to wind to form a plurality of circles, and the isolation structure fills gaps between adjacent circles.
Taking the position of the starting resistor in fig. 3 as an example, a schematic cross-sectional view along the line AA' in fig. 3 is shown in fig. 11. Referring to fig. 11, the aa' line extends to the start resistor 35 through the first transistor drain terminal 311 and the first transistor gate terminal 321 in sequence. The start-up resistor 35 is fully wound around the inactive region near the transistor region. After the start resistor and the inactive region are formed simultaneously, the inactive region between the remaining transistors is used as the isolation structure 140 between the transistors, except for the inactive region occupied by the start resistor. The isolation structure 140 fills the gaps between adjacent turns of the firing resistor 35, as well as the gaps between the firing resistor 35 and the transistor.
And step A3, forming the first transistor, the second transistor and the third transistor on the gallium nitride substrate.
After forming an inactive region and a start-up resistor in a gallium nitride substrate, the first transistor, the second transistor, and the third transistor are formed on the gallium nitride substrate. For example, referring to fig. 11, a drain terminal 311, a gate terminal 321, and the like of the first transistor are formed on a gallium nitride substrate.
By adopting the scheme of the invention, the starting resistor is formed by winding the inactive area in the gallium nitride substrate, and the integration of the first layout structure on the gallium nitride substrate can be realized, so that the characteristics of gallium nitride can be utilized, the power conversion efficiency of the semiconductor device can be improved, and the performance of the semiconductor device can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210589151.XA CN115172359B (en) | 2022-05-27 | 2022-05-27 | Semiconductor device and layout structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210589151.XA CN115172359B (en) | 2022-05-27 | 2022-05-27 | Semiconductor device and layout structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115172359A CN115172359A (en) | 2022-10-11 |
| CN115172359B true CN115172359B (en) | 2024-12-27 |
Family
ID=83484239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210589151.XA Active CN115172359B (en) | 2022-05-27 | 2022-05-27 | Semiconductor device and layout structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115172359B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128896A (en) * | 2019-12-13 | 2020-05-08 | 深圳第三代半导体研究院 | A wireless voltage sensor and its preparation method |
| CN111463282A (en) * | 2020-03-30 | 2020-07-28 | 南京华瑞微集成电路有限公司 | Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5285103B2 (en) * | 2011-03-10 | 2013-09-11 | 株式会社東芝 | Nitride semiconductor device |
| CN103219898B (en) * | 2013-04-02 | 2016-06-01 | 苏州博创集成电路设计有限公司 | There is current sample and start the semiconductor device of structure |
| CN108667323B (en) * | 2018-06-25 | 2024-05-17 | 广州金升阳科技有限公司 | AC/DC input self-adaptive switch power supply circuit |
| US20200194610A1 (en) * | 2018-12-18 | 2020-06-18 | Bolb Inc. | Light-output-power self-awareness light-emitting device |
-
2022
- 2022-05-27 CN CN202210589151.XA patent/CN115172359B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111128896A (en) * | 2019-12-13 | 2020-05-08 | 深圳第三代半导体研究院 | A wireless voltage sensor and its preparation method |
| CN111463282A (en) * | 2020-03-30 | 2020-07-28 | 南京华瑞微集成电路有限公司 | Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115172359A (en) | 2022-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9887268B2 (en) | Capacitively-coupled field-plate structures for semiconductor devices | |
| US9214517B2 (en) | Semiconductor device using 2-dimensional electron gas and 2-dimensional hole gas and method of manufacturing the semiconductor device | |
| CN104319238B (en) | Form the method and its structure of high electron mobility semiconductor device | |
| CN110176488B (en) | LDMOS transistor with breakdown voltage clamp | |
| US11658181B2 (en) | HEMT power device operating in enhancement mode and manufacturing process thereof | |
| US20090072269A1 (en) | Gallium nitride diodes and integrated components | |
| US11121251B2 (en) | Laterally diffused metal oxide semiconductor device and method for manufacturing the same | |
| JP2018056506A (en) | Semiconductor device | |
| JP2007522677A (en) | Integrated Group III-Nitride Power Device | |
| WO2013027722A1 (en) | Semiconductor device | |
| US20050179089A1 (en) | Semiconductor device | |
| JP2004356622A (en) | Bonded electronic component and integrated power device including the electronic component | |
| US20130146888A1 (en) | Monolithic semiconductor device and method for manufacturing the same | |
| US11152468B2 (en) | Semiconductor device | |
| CN102931962B (en) | Form the method and its structure of semiconductor power switch device | |
| CN115172359B (en) | Semiconductor device and layout structure and manufacturing method thereof | |
| KR20200039235A (en) | Semiconductor device and method manufacturing the same | |
| US6798181B2 (en) | Voltage supply circuit for reducing power loss through a ground connection | |
| KR101137308B1 (en) | Power mos transistor and manufacturing method for reducing power consumption with surge protection means | |
| CN113421922B (en) | Three-dimensional IGBT with grid self-clamping function and manufacturing method thereof | |
| CN111969050B (en) | Semiconductor device and driving method thereof | |
| CN116615804A (en) | Semiconductor element and device | |
| US6583453B2 (en) | Semiconductor device having a voltage-regulator device | |
| US20240379842A1 (en) | Semiconductor device with schottky barrier interface and manufacturing method thereof | |
| US10847616B2 (en) | Semiconductor device, method of manufacturing semiconductor device, and semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |