CN115151972A - Memory and electronic equipment - Google Patents
Memory and electronic equipment Download PDFInfo
- Publication number
- CN115151972A CN115151972A CN202080096121.4A CN202080096121A CN115151972A CN 115151972 A CN115151972 A CN 115151972A CN 202080096121 A CN202080096121 A CN 202080096121A CN 115151972 A CN115151972 A CN 115151972A
- Authority
- CN
- China
- Prior art keywords
- memory
- chip
- differential amplifier
- word line
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
A memory and an electronic device, the memory including a first memory chip (1) and a logic chip (2) that are stacked and electrically connected, the first memory chip (1) including a first memory cell array. The memory cell array comprises a plurality of transistors (111), and a plurality of bit lines (113) and a plurality of word lines (112), the word lines (112) and the bit lines (113) are coupled with the transistors (111). The logic chip (2) comprises a differential amplifier (21), a word line driver and a reference voltage source (25), and the differential amplifier (21), the word line driver and the reference voltage source (25) are all electrically connected with the first memory cell array. Wherein the differential amplifier (21) comprises a first differential input (211), a second differential input (212) and an output (213). When the first differential input terminal 211 is electrically connected to a bit line 113 of the first memory cell array and the second differential input terminal 212 is electrically connected to a reference voltage source 25, a differential amplifier 21 performs differential processing on a reference voltage of the reference voltage source 25 and a signal of the bit line 113.
Description
The present application relates to the field of information technology, and in particular, to a memory and an electronic device.
In a conventional computing system, a Dynamic Random Access Memory (DRAM) is used as a memory for temporarily storing operation data of a Central Processing Unit (CPU) and data exchanged with an external memory such as a hard disk. Memory performance is often described in terms of sequential read and write "bandwidth" and read and write times per second (IOPS). The interface performance of the DRAM is gradually enhanced with the development of technology, but the performance of the memory array inside the memory is slowly developed. The bottleneck in the performance of current memories is the internal memory array, and one of the more important issues of memory arrays is the high Latency, latency (Latency), which is the shortest time interval between two consecutive activations.
The reason for the high latency of the existing memory is mainly that: on one hand, a memory chip includes a memory cell array and a logic circuit, and in order to increase the storage capacity of a memory, it is necessary to increase the area of the memory cell array in the memory chip and reduce the area of the logic circuit. Therefore, the size of the memory cell array design is larger, and can generally reach 512Row X1024 column, that is, 512 word lines and 1024 bit lines are included, that is, the word lines and the bit lines are both longer and more transistors are connected. Each time a word line activates multiple transistors, the long path for transferring data using the bit lines, and the large parasitic capacitance of the bit lines, result in high latency of the memory.
Disclosure of Invention
The application provides a memory and an electronic device, which are used for expanding the storage capacity of the memory, shortening the delay of the memory, simplifying the structure of the memory and reducing the cost.
In a first aspect, the present application provides a memory including a first memory chip and a logic chip that are stacked and electrically connected, wherein the first memory chip includes a plurality of first memory cell arrays. The memory cell array comprises a plurality of transistors, a plurality of bit lines and a plurality of word lines, and each transistor is connected with the bit line and the word line. Specifically, in a first memory cell array, a plurality of transistors are arranged in an array, and one of the transistors is connected between any one of the word lines and any one of the bit lines. The logic chip comprises a differential amplifier and an interface control circuit, wherein the differential amplifier and the interface control circuit are electrically connected with the first memory cell array. The differential amplifier comprises a first differential input end, a second differential input end and an output end, wherein the first differential input end and the second differential input end form a group of differential input ends, namely the differential amplifier carries out differential amplification on signals input from the first differential input end and signals input from the second differential input end. The interface control circuit further comprises a reference voltage source, wherein a first differential input end of the differential amplifier is electrically connected with the first memory cell array, specifically electrically connected with a bit line of the first memory cell array, and a second differential input end of the differential amplifier is electrically connected with the reference voltage source of the logic chip, so that the differential amplifier differentially amplifies the reference voltage of the reference voltage source and signals of the bit line.
In the technical scheme of the application, the differential amplifier is located in the logic chip, so that the area of the first storage chip is not occupied, and the capacity of the memory can be expanded. The first memory chip is stacked on the logic chip, so that the length of a connection line for connecting the first memory cell array to the differential amplifier can be shortened, thereby contributing to shortening the delay. The peripheral control circuit part is positioned on the logic chip, the storage part is positioned on the first storage chip, and the logic chip and the first storage chip can be respectively processed by adopting a more advanced technology so as to improve the transistor density and the speed of the memory. The scheme also utilizes a reference voltage source to input the reference voltage to the differential amplifier so as to simplify the structure of the memory, reduce the area occupied by a connecting wire between the differential amplifier and the first memory chip and reduce the cost.
In order to reduce the cost and the area of a logic chip, the memory in the application may further include a bit line multiplexer having a plurality of input ports and an output port, wherein one end of the input port of the bit line multiplexer is connected to the bit line of the first memory cell array, and one end of the output port is connected to the differential amplifier. The bit line multiplexer may be connected to a plurality of bit lines, and in practical applications, the bit line multiplexer selects one of the plurality of bit lines to output to the differential amplifier from the output port according to requirements. The scheme can reduce the number of the differential amplifiers in the memory, reduce the occupied area of the differential amplifiers and reduce the cost.
When the bit line multiplexer is specifically provided, the bit line multiplexer may be located in the first memory chip. Because the number of the connections between the multi-way gate and the bit lines of the first memory chip is large and the number of the connections between the multi-way gate and the differential amplifiers of the logic chip is small, the scheme can reduce the number of the connecting lines from the first memory chip to the logic chip so as to reduce the area occupied by the connecting lines, simplify the process and improve the reliability of the connection between the first memory chip and the logic chip.
In a further technical solution, the logic chip further includes a word line driver, and the word line driver is connected to a word line of the first memory chip. The word line driver is capable of providing a gate voltage to the transistors on the word line, controlling the turning on and off of the memory cells on the word line. In the scheme, the word line driver of the memory is positioned on the logic chip, the area of the first memory chip is not occupied, the number of the first memory cell arrays of the first memory chip is increased, and the memory capacity of the memory is expanded.
In order to reduce the cost and the area of a logic chip, the memory in the application can further comprise a word line multiplexer, wherein the word line multiplexer is provided with a plurality of output ports and an input port, one end of each output port of the word line multiplexer is connected with a word line of the first memory cell array, and the input end of each output port of the word line multiplexer is connected with a word line driver. The word line multiplexer may be connected to a plurality of word lines, and in practical applications, the word line multiplexer selects one of the plurality of word lines to connect to the word line driver according to requirements. The scheme can reduce the number of word line drivers in the memory, reduce the area occupied by the word line drivers and reduce the cost.
When the word line multiplexer is specifically provided, the word line multiplexer may be located in the first memory chip. Because the connection quantity of the multi-way gate and the word line positioned on the first storage chip is more and the connection quantity of the multi-way gate and the word line driver positioned on the logic chip is less, the scheme can reduce the quantity of connecting lines from the first storage chip to the logic chip so as to reduce the area occupied by the connecting lines, simplify the process and improve the reliability of the connection between the first storage chip and the logic chip.
In a specific aspect of the present application, the memory may further include a second memory chip stacked on the first memory chip, the second memory chip having a plurality of second memory cell arrays, the second memory cells also being electrically connected to the differential amplifier of the logic chip. The first memory chip and the second memory chip are both connected to the logic chip. In the embodiment of the application, the number of the memory chips included in the memory is not limited, and can be selected according to actual requirements.
The second memory chip also comprises a local differential amplifier, the bit lines of the second memory cell array are connected with the input ends of the local differential amplifier, and the output ends of the local differential amplifier are connected with the differential amplifier on the logic chip. In specific application, the signal may be first amplified by the local differential amplifier, and then amplified by the differential amplifier on the logic chip.
When the first memory chip and the logic chip are connected, a proper connection mode can be selected according to requirements, and particularly, the wiring layer of the first memory chip and the wiring layer of the logic chip can be connected through hybrid bonding connection. When the hybrid bonding connection process is adopted, the preparation of the first memory chip and the logic chip can be respectively completed in batches, and then the first memory chip is connected with the logic chip.
In a second aspect, the present disclosure further provides an electronic device, where the electronic device includes the memory according to any of the above-mentioned embodiments. The electronic equipment has the advantages of short storage data reading delay time, high storage capacity and low cost under the condition of a certain storage volume.
FIG. 1 is a schematic cross-sectional view of a memory according to an embodiment of the present application;
FIG. 2 is a diagram illustrating a layout of a memory according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of a first memory cell array according to an embodiment of the present application;
FIG. 4 is a schematic layout diagram of a memory according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a memory according to an embodiment of the present application;
fig. 6 is a schematic cross-sectional view of a memory according to an embodiment of the present application.
Description of reference numerals:
1-a first memory chip; 11-a first memory cell array;
111-transistor; 112-word lines;
113-a bit line; 12-a first semiconductor substrate;
13-a first wiring layer; 2-a logic chip;
21-a differential amplifier; 211-a first differential input;
212-a second differential input; 213-an output terminal;
22-interface control circuitry; 23-a second semiconductor substrate;
231-a through hole; 24-a second wiring layer;
25-a reference voltage source; 26-word line drivers;
3-an interconnect layer; a 4-bit line multiplexer;
5-word line multiplexer; 6-a second memory chip;
61-a second array of memory cells; 62-local area differential amplifier.
In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.
The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of this application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The memory provided in the embodiments of the present application may be applied to an electronic device, where the electronic device may be a computer system, such as a server, a desktop computer, and a notebook computer, and the memory in the embodiments of the present application may be specifically applied to a last cache of the computer system near a Central Processing Unit (CPU). In addition, the electronic equipment can also be mobile terminal products such as a mobile phone, and the type of the electronic equipment is not particularly limited in the application. The memory in the present application may specifically be a Dynamic Random Access Memory (DRAM). The memory can be particularly applied to data storage, and writing and reading of data can be carried out.
Fig. 1 is a schematic cross-sectional structure diagram of a memory in an embodiment of the present application, and fig. 2 is a schematic layout diagram of the memory in the embodiment of the present application, please refer to fig. 1 and fig. 2, the memory in the embodiment of the present application includes a first memory chip 1 and a logic chip 2, which are stacked and fixed, and the first memory chip 1 and the logic chip 2 are stacked and fixed and electrically connected. The first memory chip 1 includes a plurality of first memory cell arrays 11 (sub-arrays), and the logic chip 2 includes a plurality of differential amplifiers 21 and an interface control circuit 22. Fig. 3 is a schematic structural diagram of the first memory cell array 11 in the embodiment of the present application, and referring to fig. 3, the first memory cell array 11 may include a plurality of memory cells arranged in an array, where each memory cell includes a transistor 111 and a bit line 113 and a word line 112 connected to the transistor 111. The transistors 111 in each row are connected to the same word line 112, the transistors 111 in each column are connected to the same bit line 113, the extending direction of the word line 112 intersects with the extending direction of the bit line 113, and one transistor 111 is connected between any one word line 112 and any one bit line 113. The differential amplifier 21 of the logic chip 2 is electrically connected to the bit lines 113 of the first memory cell array 11, specifically, each differential amplifier 21 is connected to at least one bit line 113 of the first memory cell array 11, and each differential amplifier 21 is connected to one bit line 113 when operating, so as to amplify a signal corresponding to the connected bit line 113, thereby implementing data transmission. In the technical solution of the present application, the differential amplifier 21 is located in the logic chip 2, and the first memory chip 1 may have a larger area to arrange the first memory cell array 11, so as to expand the capacity of the memory. In addition, in the prior art, the differential amplifier 21 and the first memory array unit 11 are both located in the first memory chip 1, that is, the differential amplifier 21 and the first memory array unit 11 are both located in the plane of the first memory chip 1, and the connection line between the differential amplifier 21 and the bit line 113 needs to span a longer distance in the first logic chip 1. In the embodiment of the present application, the first memory chip 1 is stacked on the logic chip 2, so that the differential amplifier 21 is disposed opposite to the connected bit line 113, and the connection line when the first memory cell array 11 is connected to the differential amplifier 21 spans from the first memory chip 1 to the logic chip 2, so that the length of the connection line can be shortened, which is beneficial to shortening the delay. In this scheme, the differential amplifier 21 and the interface control circuit 22 are both located in the logic chip 2, and the memory portion is located in the first memory chip 1, so that the first memory chip 1 and the logic chip 2 may be prepared by different processes, and for the first memory chip 1, the first memory chip 1 mainly includes a memory structure, which may improve the transistor density of the memory. For the logic chip 2, the logic chip 1 only comprises a circuit structure, so that the processing by adopting a more advanced technology is facilitated, and the density and the operation rate of the circuit structure can be improved. The differential amplifier 21 comprises at least one set of differential inputs, each set of differential inputs comprises a first differential input 211 and a second differential input 212, and the differential amplifier 21 can perform a differential calculation on data input from the first differential input 211 and data input from the second differential input 212. In the technical solution of the present application, the interface control circuit 22 further includes a reference voltage source 25, the first differential input end 211 of the differential amplifier 21 is electrically connected to the first memory cell array 11, and specifically electrically connected to the bit line 113 of the first memory cell array 11, the second differential input end 212 is electrically connected to the reference voltage source 25, the reference voltage source 25 inputs a reference voltage to the differential amplifier 21, and the differential amplifier 21 performs a differential calculation by using the reference voltage and the bit line 113 voltage input from the first input end to obtain the memory cell data information.
In the prior art, the differential amplifiers 21 are located in the memory chip, and in a group of differential inputs of each differential amplifier 21, the first differential input 211 and the second differential input 212 are both connected to the bit line 113, so that there are more connection lines between the differential amplifier 21 and the memory cell array. In the embodiment of the present application, the first memory chip 1 and the logic chip 2 are stacked and electrically connected, and with the adoption of the technical scheme of the present application, only the first differential input terminal 211 of the differential amplifier 21 is electrically connected with the bit line 113 of the first memory chip 1, so that the connection line between the first memory chip 1 and the logic chip 2 for connecting the bit line 113 and the differential amplifier 21 is greatly reduced, and is almost reduced by half. The scheme can simplify the structure of the memory and reduce the occupied area of the connecting line between the differential amplifier 21 and the first memory chip 1. By sharing the resources of the reference voltage source 25, costs can also be reduced, and the calculation procedure simplified.
It should be noted that, in the embodiment of the present application, the first memory chip 1 is stacked on the logic chip 2, and only the position relationship between the first memory chip and the logic chip is described. Specifically, as shown in fig. 2, the first memory chip 1 and the logic chip 2 are not located on the same plane, and both the first memory chip 1 and the logic chip 2 can be regarded as a sheet structure, and two sheet structures are stacked. The first memory chip 1 and the logic chip 2 may be disposed in contact with each other, and other structures may be disposed between the first memory chip 1 and the logic chip 2.
In a specific embodiment, the differential amplifier 21 is a single-channel differential amplifier 21, and includes only one set of differential input terminals and output terminals 213, i.e. the input terminals include only the first differential input terminal 211 and the second differential input terminal 212. In the present embodiment, each set of differential amplifiers 21 includes a first differential input 211 and a second differential input 212 in the present embodiment. Each path of the differential amplifier 21 performs a differential operation on only the data obtained from the two corresponding differential input terminals of the path, and outputs the operation result from the output terminal 213 of the path of the differential amplifier 21.
The interface control circuit 22 may include a data bus, an address bus, a command enable, a command register, a data/address latch, a global differential amplifier, a refresh counter and refresh control logic, a data buffer, a power supply circuit, a reference power supply, and the like.
In implementing the embodiment of the present application, a specific manner of electrically stacking the first memory chip 1 and the logic chip 2 is not limited, and it can be considered that an interconnection layer 3 is provided between the first memory chip 1 and the logic chip 2, and the interconnection layer 3 is used to implement fixed connection and electrical connection between the first memory chip 1 and the logic chip 2. Referring to fig. 1, a first memory chip 1 includes a first semiconductor substrate 12, a plurality of first memory cell arrays 11 formed on the first semiconductor substrate 12, and a first wiring layer 13 connected to the first memory cell arrays 11; the logic chip 2 includes a second semiconductor substrate 23, a differential amplifier 21 and an interface control circuit 22 formed on the second semiconductor substrate 23, and a second wiring layer 24 connected to the differential amplifier 21 and the interface control circuit 22. In one connection mode of the first memory chip 1 and the logic chip 2: the first memory chip 1 and the logic chip 2 are connected face to face (face to face), and specifically, the first wiring layer 13 (top wiring layer of the first memory chip) of the first memory chip 1 and the second wiring layer 24 (top wiring layer of the logic chip) of the logic chip 2 may be connected by Hybrid bonding (Hybrid bonding), as shown in fig. 1. When the hybrid bonding connection process is adopted, the preparation of the first memory chip 1 and the logic chip 2 can be respectively completed in batches, and then the first memory chip 1 is connected with the logic chip 2. When the hybrid bonding connection is adopted, since the first chip top wiring layer 13 is located inside the memory opposite to the second chip top wiring layer 24, it is necessary to provide a through hole 231 in the first semiconductor substrate 12 or the second semiconductor substrate 23 in order to connect the memory to an external circuit.
In one embodiment of the present application, in order to reduce the memory latency, the first memory cell array 11 may include a number of bit lines 113 smaller than 1024 and a number of word lines 112 smaller than 512, i.e., the memory may be fine-grained. Specifically, in one embodiment, the number of bit lines 113 of the first memory cell array 11 may be 8 to 512; in another embodiment, the number of word lines 112 of the first memory cell array 11 is 8 to 256; in one embodiment, the number of the bit lines 113 of the first memory cell array 11 may be 8 to 256, and the number of the word lines 112 may be 8 to 512. The smaller the number of word lines 112 and bit lines 113 in the first memory cell array 11, the higher the degree of fine-grained memory, and the shorter the delay of the memory. In the prior art, in order to reduce memory latency, the memory cell arrays of the memory are made finer in size, so that the number of the memory cell arrays in each memory chip is increased, and the number of the differential amplifiers 21 connected to the bit lines 113 is also increased, which results in that the differential amplifiers 21 occupy more area of the memory chip. The area occupied by the memory cell array in the memory chip with the same area is reduced, the memory capacity is reduced, and the average cost per byte of memory is increased. By adopting the technical scheme of the present application, the differential amplifier 21 is disposed on the logic chip 2, and the first memory chip 1 may have a larger area for disposing the first memory cell array 11, which may increase the storage capacity of the memory.
Fig. 4 is a schematic diagram of another layout of a memory in the embodiment of the present application. As shown in fig. 4, in order to reduce the cost, in the embodiment of the present application, the memory further includes a bit line multiplexer 4, where one end of the bit line multiplexer 4 has a plurality of input ports, and the other end of the bit line multiplexer 4 has an output port, and the output port may be connected to any one of the plurality of input ports. Each input port of the bit line multiplexer 4 may be connected to a bit line 113 of the first memory cell array 11, but in practical applications, only some input ports of the plurality of input ports of the bit line multiplexer 4 may be connected to the bit line 113, and the application is not limited thereto; the output port of the bit line multiplexer 4 is connected to the differential amplifier 21, and the bit line multiplexer 4 can select one bit line 113 connected to the input port to communicate with the output port. In the application, a plurality of bit lines 113 may be connected to one differential amplifier 21, and one bit line 113 of the plurality of bit lines 113 connected to the bit line multiplexer 4 may be connected to the differential amplifier 21 by the bit line multiplexer 4. In the prior art, each bit line 113 is typically connected to a differential amplifier 21. When the number of bit lines 113 of each first memory cell array 11 of the memory is reduced, that is, after the first memory cell array 11 is made fine-grained, the number of the first memory cell arrays 11 is increased, the total number of bit lines 113 of the first memory chip 1 is also increased, the number of differential amplifiers 21 to be connected is also increased, the occupied area is increased, and the cost of the first memory chip 1 is also increased. In this scheme, the number of differential amplifiers 21 used can be reduced, the area of the logic chip 2 occupied by the differential amplifiers 21 can be reduced, and the cost can be reduced.
As shown in fig. 4, when the bit line multiplexer 4 is specifically disposed, the bit line multiplexer 4 may be disposed on the first memory chip 1, so as to reduce the number of connection lines between the first memory chip 1 and the logic chip 2, thereby simplifying the process. In addition, the number of the connecting lines between the first memory chip 1 and the logic chip 2 is small, so that the reliability of the connection between the first memory chip 1 and the logic chip 2 is high, and the damage is not easy to occur. Specifically, if the bit line multiplexer 4 is located on the logic chip 2, the number of the bit lines 113 of the first memory chip 1 needs to be connected from the first memory chip 1 to the input ports of the bit line multiplexer 4 located on the logic chip 2. And the bit line multiplexer 4 is located in the first memory chip 1, the bit line 113 is directly connected with the bit line multiplexer 4 in the first memory chip 1, the output port of the bit line multiplexer 4 is connected with the logic chip 2, and a plurality of input ports of the bit line multiplexer 4 correspond to one output port, so that the number of the output ports is far smaller than that of the input ports, and the number of connecting lines between the first memory chip 1 and the logic chip 2 is small.
With continued reference to fig. 4, in addition to any of the above embodiments, the logic chip 2 further includes a word line driver 26, and the word line driver 26 is connected to the word line 112 of the first memory chip 1. The word line driver 26 is electrically connected to the word lines 112 of the first memory cell array 11 to turn on and off the memory cells on the word lines 112. In this scheme, the word line driver 26 of the memory is located in the logic chip 2, and therefore, the area of the first memory chip 1 is not occupied, which is beneficial to increasing the number of the first memory cell arrays 11 of the first memory chip 1 and increasing the storage capacity of the memory.
With continued reference to fig. 4, the memory further includes a word line multiplexer 5, wherein one end of the word line multiplexer 5 has a plurality of output ports, and the other end thereof has an input port, and the input port can be connected to any one of the plurality of output ports. Each output port of the word line multiplexer 5 may be connected to a word line 112 of the first memory cell array 11, and certainly in practical applications, only some output ports of the multiple output ports of the word line multiplexer 5 may be connected to the word line 112, which is not limited in the present application; the input port of the word line multiplexer 5 is connected to the word line driver 26, and the word line multiplexer 5 can select one of the word lines 112 connected to the output port to communicate with the input port. In the application, a plurality of word lines 112 may be connected to one word line driver 26 in common, and one word line 112 of the plurality of word lines 112 connected to the word line multiplexer 5 may be connected to the word line driver 26 by the word line multiplexer 5. Typically, one word line driver 26 is connected to each word line 112 as is known in the art. When the number of word lines 112 of each first memory cell array 11 of the memory is decreased, that is, after the first memory cell array 11 is made fine-grained, the number of the first memory cell arrays 11 is increased, the total number of word lines 112 of the first memory chip 1 is also increased, the number of word line drivers 26 to be connected is also increased, the area occupied by the word line drivers 26 is increased, and the cost of the first memory chip 1 is also increased. In this scheme, the number of word line drivers 26 used can be reduced, the area of the logic chip 2 occupied by the word line drivers 26 can be reduced, and the cost can be reduced.
Specifically, when the word line multiplexer 5 is provided, the word line multiplexer 5 may be provided on the first memory chip 1, so as to reduce the number of connection lines between the first memory chip 1 and the logic chip 2, thereby simplifying the process. In addition, the number of the connecting lines between the first memory chip 1 and the logic chip 2 is small, so that the reliability of the connection between the first memory chip 1 and the logic chip 2 is high, and the damage is not easy to occur. Specifically, if the word line multiplexer 5 is located on the logic chip 2, the word lines 112 of the first memory chip 1 need to be connected from the first memory chip to the output ports of the word line multiplexer 5 located on the logic chip 2, and the number of the word line multiplexers is large. And the word line multiplexer 5 is located in the first memory chip 1, the word line 112 is directly connected with the word line multiplexer 5 in the first memory chip 1, the input port of the word line multiplexer 5 is connected with the logic chip 2, and a plurality of output ports of the word line multiplexer 5 correspond to one input port, so that the number of the input ports is smaller than that of the output ports, and the number of connecting lines between the first memory chip 1 and the logic chip 2 is smaller.
Fig. 5 is a schematic cross-sectional view of another memory in an embodiment of the present application, please refer to fig. 5, in another embodiment of the present application, the memory further includes a second memory chip 6, the second memory chip 6 is stacked on the first memory chip 1, and the second memory chip 6 and the first memory chip 1 share a logic chip 2. In a specific embodiment, the second memory chip 6 includes a plurality of second memory cell arrays 61, and the second memory cell arrays 61 are electrically connected to the differential amplifier 21. The second memory chip 6 may have the structural features of the first memory chip 1, the connection relationship between the second memory chip 6 and the logic chip 2, or the connection relationship between the first memory chip 1 and the logic chip 2.
In a specific embodiment, the memory may include one second memory chip 6, and may also include two or more second memory chips 6, which is not limited in this application.
Fig. 6 is a schematic cross-sectional view of another memory in the embodiment of the present application, and as shown in fig. 6, in an embodiment, the second memory chip 6 further includes a local differential amplifier 62, a bit line of the second memory cell array 61 is connected to an input terminal of the local differential amplifier 62, and an output terminal of the local differential amplifier 62 is connected to the differential amplifier 21 on the logic chip 2. In a specific application, the signal may be first amplified by the local differential amplifier 62, and then amplified by the differential amplifier 21 of the logic chip 2.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
- A memory, comprising:a first memory chip including a first memory cell array including a plurality of transistors, and word lines and bit lines coupled with the plurality of transistors;a logic chip stacked and electrically connected with the first memory chip, including a differential amplifier and a reference voltage source;the differential amplifier is provided with a first differential input end and a second differential input end, the first input end is electrically connected with the first memory cell array, the second input end is electrically connected with the reference voltage source, and the first differential input end and the second differential input end are a pair of differential input ends.
- The memory according to claim 1, further comprising a bit line multiplexer having one end connected to the plurality of bit lines of the first memory cell array and the other end connected to the differential amplifier.
- The memory of claim 2, wherein the bit line multiplexer is located on the first memory chip.
- The memory of any one of claims 1 to 3, wherein the logic chip further comprises a word line driver connected to a word line of the first memory chip.
- The memory of claim 4, further comprising a word line multiplexer having one end connected to a plurality of the word lines and another end connected to the word line driver.
- The memory of claim 5, wherein the word line multiplexer is located on the first memory chip.
- The memory according to any one of claims 1 to 6, further comprising a second memory chip stacked on the first memory chip, the second memory chip including a plurality of second memory cell arrays, the second memory cell arrays being electrically connected to the differential amplifier.
- The memory of claim 7, wherein the second memory chip further comprises a local differential amplifier, the second array of memory cells being electrically connected to the local differential amplifier, the local differential amplifier being electrically connected to a differential amplifier on the logic chip.
- The memory according to any one of claims 1 to 8, wherein the first memory chip is hybrid bonded to the logic chip.
- An electronic device, characterized in that it comprises a memory according to any one of claims 1 to 9.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/077293 WO2021168839A1 (en) | 2020-02-28 | 2020-02-28 | Memory and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115151972A true CN115151972A (en) | 2022-10-04 |
Family
ID=77490617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080096121.4A Pending CN115151972A (en) | 2020-02-28 | 2020-02-28 | Memory and electronic equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115151972A (en) |
| WO (1) | WO2021168839A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116367540B (en) * | 2023-05-10 | 2023-10-24 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2354618B (en) * | 1999-09-24 | 2001-11-14 | Pixelfusion Ltd | Memory devices |
| JP4662740B2 (en) * | 2004-06-28 | 2011-03-30 | 日本電気株式会社 | Stacked semiconductor memory device |
| CN100541664C (en) * | 2007-01-25 | 2009-09-16 | 林殷茵 | A kind of resistance random access memory and methods of storage operating thereof |
| CN101236780B (en) * | 2008-02-26 | 2012-07-04 | 中国科学院上海微系统与信息技术研究所 | Circuit design standard and implementation method for 3-D solid structure phase change memory chip |
| TW201207852A (en) * | 2010-04-05 | 2012-02-16 | Mosaid Technologies Inc | Semiconductor memory device having a three-dimensional structure |
| CN106910746B (en) * | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacturing method, packaging method |
| US10957382B2 (en) * | 2018-08-09 | 2021-03-23 | Micron Technology, Inc. | Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections |
-
2020
- 2020-02-28 CN CN202080096121.4A patent/CN115151972A/en active Pending
- 2020-02-28 WO PCT/CN2020/077293 patent/WO2021168839A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021168839A1 (en) | 2021-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11114139B2 (en) | Stacked memory device, a system including the same and an associated method | |
| US10727200B2 (en) | Memory device including bump arrays spaced apart from each other and electronic device including the same | |
| WO2021196853A1 (en) | Memory block and memory | |
| CN105431939A (en) | stack memory | |
| US7006402B2 (en) | Multi-port memory device | |
| US12132018B2 (en) | Transmission circuit, interface circuit, and memory | |
| KR100582821B1 (en) | Multi-port memory device | |
| US12189996B2 (en) | Multiple register clock driver loaded memory subsystem | |
| CN115151972A (en) | Memory and electronic equipment | |
| CN112242156A (en) | Packaged integrated circuit memory devices and methods of operating the same | |
| US11842792B2 (en) | Interface circuit, data transmission circuit, and memory | |
| CN212392002U (en) | Interface circuit, data transmission circuit and memory | |
| CN212392001U (en) | Transmission circuit, interface circuit and memory | |
| US20210103533A1 (en) | Memory system and memory chip | |
| US8547766B2 (en) | Area-efficient data line layouts to suppress the degradation of electrical characteristics | |
| CN114121083B (en) | Interface circuit, data transmission circuit and memory | |
| JP2007095266A (en) | Semiconductor memory device | |
| US20250062283A1 (en) | Semiconductor package | |
| US11881256B2 (en) | Semiconductor memory device and method of controlling load of global input-output lines of the same | |
| WO2024148728A1 (en) | Memory circuit and memory thereof | |
| CN113467711B (en) | Memory device for artificial intelligence operation | |
| TWI825919B (en) | Memory | |
| CN118540933A (en) | Semiconductor device and memory system | |
| CN116417452A (en) | Integrated circuit structure, memory and integrated circuit layout | |
| CN119673234A (en) | Memory device and method of operating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |