CN115149931A - Complementary Fully Differential Dynamic Comparator for Common-Mode Voltage Mismatch - Google Patents

Abstract

The invention relates to a complementary fully differential dynamic comparator for resisting common mode voltage mismatch, comprising an NMOS input part, a PMOS input part, a latch circuit and a reset MOS switch. The NMOS input part adopts a plurality of NMOSs connected to form a differential Input circuit; PMOS input part uses a number of PMOS connected to form a differential input circuit; latch circuit uses a number of NMOS and PMOS to form a positive feedback circuit, the substrate of NMOS is connected to ground VSS, and the substrate of PMOS is connected to power supply VDD. Therefore, under the mismatch of 100mV, the offset voltage is close to 0mV, which is much smaller than the traditional 200mV and has better stability. The design pressure of the upper system is relieved, and the area and power consumption of the upper system are reduced. There is no need to take a two-input dynamic comparator, reducing the difficulty of implementation. A complementary structure can be provided, and the PMOS and NMOS are simultaneously introduced into the comparator as input transistors, thereby realizing the function of being insensitive to common mode mismatch.

Description

Complementary Fully Differential Dynamic Comparator for Common Mode Voltage Mismatch

technical field

The invention relates to a circuit structure of a dynamic comparator, in particular to a complementary fully differential dynamic comparator for resisting common mode voltage mismatch.

Background technique

As far as the prior art is concerned, the fully differential dynamic comparator is an important branch of the dynamic comparator. Its main function is to compare two sets of differential signals and output digital logic results. In the past two decades, various dynamic comparators have been proposed for different needs. These fully differential dynamic comparators are used as an integral part in integrated circuits such as analog-to-digital converters, SRAM memory chips, etc.

The most primitive current-sensing type dynamic comparator, which is generally considered to be the dynamic comparator today, dates back to 1995. Its main function is to compare two voltage signals and output a digital logic result of 0 or 1. (DOI: 10.1109/4.364429).

Later, the prior art document (DOI: 10.1109/JSSC.2003.819166) disclosed that comparing two voltage signals is extended to comparing two sets of differential signals, that is, a four-input dynamic comparator, or a fully differential dynamic comparator. Based on this, a large number of fully differential dynamic comparators have emerged, each of which has its own characteristics, solving specific problems in the comparator or optimizing the performance of the entire comparator. Some are to reduce the supply voltage, some are to improve the comparison accuracy, some are to reduce the kickback noise, and some are to increase the signal input range.

However, a limitation of these fully differential dynamic comparators is that the two sets of signals that need to be compared must have exactly equal common-mode voltages. If there is a deviation, commonly referred to as a common-mode mismatch, the accuracy of the comparator will sharply decrease. Deterioration, commonly known as comparison point shift. Moreover, the prior art does not provide a solution.

In view of the above-mentioned defects, the designer actively researches and innovates, in order to create a complementary fully differential dynamic comparator for resisting common mode voltage mismatch, making it more valuable in industry.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the purpose of the present invention is to provide a complementary fully differential dynamic comparator for resisting common mode voltage mismatch.

The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of the present invention includes: an NMOS input part, a PMOS input part, a latch circuit, and a reset MOS switch, and the NMOS input part is connected by a plurality of NMOS A differential input circuit is formed; the PMOS input part uses a plurality of PMOSs to connect to form a differential input circuit; the latch circuit uses a number of NMOS and PMOS to form a positive feedback circuit, the substrate of the NMOS is connected to the ground VSS, and the PMOS is connected to the ground VSS. The substrates are all connected to the power supply VDD.

Further, in the above-mentioned complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, the NMOS constituting the NMOS input part includes NMOS MN1, NMOS MN2, NMOS MN3, NMOS MN4, NMOS MN5, and the set The gate terminal of the NMOS MN1 is connected to the input signal V _IP , the gate terminal of the NMOS MN2 is connected to the input signal V _RN , the gate terminal of the NMOS MN3 is connected to the input signal V _RP , and the gate terminal of the NMOS MN4 is connected to the input signal V _IN , it is assumed that the source terminals of the NMOS MN1, NMOS MN2, NMOS MN3, and NMOS MN4 are connected to each other and the drain terminal of the NMOS MN5 is provided with a connection point B, and the point P1 is assumed to be the point where the drain terminals of the NMOS MN1 and NMOS MN2 are connected. The point N1 is where the drain terminals of NMOS MN3 and NMOS MN4 are connected, the NMOS MN5 is a pseudo current source driven by a clock latch, the clock latch is connected to the gate terminal of NMOS MN5, and the source terminal of NMOS MN5 is connected to ground VSS.

Further, in the above-mentioned complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, the PMOS constituting the PMOS input portion includes PMOS MP1, PMOS MP2, PMOS MP3, PMOS MP4, PMOS MP5, and PMOSMP8 , PMOS M9, the gate terminal of the PMOS MP1 is set to be connected to the input signal V _IN , the gate terminal of the PMOS MP2 is set to be connected to the input signal V _RP , the gate terminal of the PMOS MP3 is set to be connected to the input signal V _RN , the gate terminal of the PMOS MP4 is set to be connected Connect the input signal V _IP , the source ends of the PMOS MP1, PMOS MP2, PMOS MP3, and PMOS MP4 are connected to each other, and the drain end of the PMOS MP5 is provided with a connection point T, and the place where the drain ends of the PMOS MP1 and PMOS MP2 are connected is Point N2, set point P2 where the drain terminals of the PMOS MP3 and PMOS MP4 are connected, the PMOS MP5 is driven by the inverted signal of the clock latch, the source terminal of the PMOS MP5 is connected to the power supply VDD, and the PMOS MP8 The source terminal is connected to the power supply VDD, the gate terminal is connected to the point N2, the drain terminal is connected to the output _vON , the source terminal of the PMOSMP9 is connected to the power supply VDD, the gate terminal is connected to the point P2, and the drain terminal is connected to the output _vOP .

Further, in the above-mentioned complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, when the PMOS MP8 is in the reset state, the gate terminal voltage is grounded VSS, in the conducting state, and v _ON is reset. Set at the power supply VDD; when the PMOS MP8 is in the working state, the gate terminal voltage of the PMOS MP8 gradually rises from the ground VSS to the power supply VDD to release the forcing effect on the output point _vON .

Further, in the above-mentioned complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, when the PMOS MP9 is in the reset state, the gate terminal voltage is grounded VSS, and is in a conducting state, and v _OP is Reset at the power supply VDD; when the PMOS MP9 is in the working state, the gate terminal voltage of the PMOS MP9 gradually rises from the ground VSS to the power supply VDD to release the forcing effect on the output point _vOP .

Still further, in the above-mentioned complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, the NMOS and PMOS constituting the latch circuit include NMOS MN6, NMOS MN7, PMOS MP6, and PMOS MP7, wherein NMOSMN6 , NMOS MN7 constitutes a positive feedback circuit, PMOS MP6, PMOS MP7 constitute a positive feedback circuit, the source end of the NMOS MN6 is connected to the point P1, the gate end is connected to the output v _OP , the source end of the NMOS MN7 is connected to Point N1, its gate terminal is connected to the output _vON , the source terminal of the PMOS MP6 is connected to the power supply VDD, the drain terminal is connected to _vON , the gate terminal is connected to _vOP , the source terminal of the PMOS MP7 is connected to the power supply VDD, and the drain terminal is connected to the power supply VDD. The terminal is connected to _vOP , and the gate terminal is connected to _vON .

By means of the above scheme, the present invention has at least the following advantages:

1. Under the mismatch of 100mV, the offset voltage is close to 0mV, which is much smaller than the traditional 200mV and has better stability.

2. The design pressure of the upper system is relieved, and the area and power consumption of the upper system are reduced.

3. There is no need to take a two-input dynamic comparator, which reduces the difficulty of implementation.

4. A complementary structure can be provided, and PMOS and NMOS are introduced into the comparator as input transistors at the same time, thereby realizing the function of being insensitive to common mode mismatch.

The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, and implement it according to the content of the description, the preferred embodiments of the present invention are described in detail below with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a complementary fully differential dynamic comparator for resisting common-mode voltage mismatch.

FIG. 2 is a simplified schematic diagram of the implementation of FIG. 1 .

Figure 3 is a schematic diagram of the voltage waveform when there is no common-mode voltage mismatch.

Figure 4 is a schematic diagram of the voltage waveform when the 100mV common mode voltage is mismatched.

FIG. 5 is a schematic structural diagram of a 19-bit pipeline analog-to-digital converter.

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. The following examples are intended to illustrate the present invention, but not to limit the scope of the present invention.

Complementary fully differential dynamic comparators for resisting common-mode voltage mismatch as shown in Figures 1 to 2 are different in that they include an NMOS input part, a PMOS input part, a latch circuit, and a reset MOS switch. . Specifically, the NMOS input part uses several NMOSs connected to form a differential input circuit. The PMOS input part uses several PMOSs to connect to form a differential input circuit. Therefore, as the complement of the NMOS input part, the two differential inputs form a complementary structure to meet the requirement of effective anti-common-mode mismatch. At the same time, the latch circuit adopts a number of NMOS and PMOS to form a positive feedback circuit. In addition, the substrates of the NMOSs are all connected to the ground VSS, and the substrates of the PMOSs are all connected to the power supply VDD. During implementation, under the combined action of the clock latch and its inversion signal, P1, N1, v _OP and v _ON are reset to the power supply VDD, and the point P2 and the point N2 are reset to the ground VSS.

Referring to a preferred embodiment of the present invention, the NMOS constituting the NMOS input part includes NMOS MN1, NMOS MN2, NMOS MN3, NMOS MN4, and NMOS MN5. During implementation, it is assumed that the gate terminal of NMOS MN1 is connected to the input signal V _IP , the gate terminal of NMOS MN2 is connected to the input signal V _RN , the gate terminal of NMOS MN3 is connected to the input signal V _RP , and the gate terminal of NMOS MN4 is connected to the input signal V _IN , and at the same time, It can be set that the source terminals of NMOS MN1, NMOS MN2, NMOS MN3 and NMOS MN4 are connected with the drain terminal of NMOS MN5 and a connection point B is provided. In addition, the point P1 may be set where the drain terminals of NMOS MN1 and NMOS MN2 are connected, and the point N1 may be set where the drain terminals of NMOS MN3 and NMOS MN4 are connected. During implementation, the NMOS MN5 is a pseudo current source driven by a clock latch, the clock latch is connected to the gate terminal of the NMOS MN5, and the source terminal of the NMOS MN5 is connected to the ground VSS.

Further, the PMOS constituting the PMOS input portion includes PMOS MP1, PMOS MP2, PMOS MP3, PMOS MP4, PMOS MP5, PMOS MP8, and PMOS M9. Specifically, the gate terminal of PMOS MP1 is connected to the input signal V _IN , the gate terminal of PMOS MP2 is connected to the input signal V _RP , the gate terminal of PMOS MP3 is connected to the input signal V _RN , and the gate terminal of the PMOS MP4 is connected to the input signal V _IP . Meanwhile, the source terminals of PMOS MP1, PMOS MP2, PMOS MP3, and PMOS MP4 are connected to each other, and a connection point T is provided with the drain terminal of PMOS MP5. In addition, the point N2 is set where the drain terminals of PMOS MP1 and PMOS MP2 are connected, and the point P2 is set where the drain terminals of PMOS MP3 and PMOS MP4 are connected. During implementation, the PMOS MP5 is driven by the inverted signal of the clock latch. The inverted signal is opposite in phase to the source clock signal, and can be generated by the original clock signal passing through an inverter under the same process conditions. Also, the source terminal of the PMOS MP5 is connected to the power supply VDD. The source terminal of the PMOS MP8 is connected to the power supply VDD, the gate terminal is connected to the point N2, and the drain terminal is connected to the output _vON . The source terminal of the PMOS MP9 is connected to the power supply VDD, the gate terminal is connected to the point P2, and the drain terminal is connected to the output v _OP .

During the actual implementation, when the PMOS MP8 is in a reset state, the gate terminal voltage is grounded VSS, in a conducting state, and v _ON is reset to the power supply VDD. When the PMOS MP8 is in the working state, the gate terminal voltage of the PMOS MP8 gradually rises from the ground VSS to the power supply VDD to release the forcing effect on the output point _vON . When the PMOS MP9 is in a reset state, the gate terminal voltage is grounded VSS, and is in a conducting state, and v _OP is reset to the power supply VDD. When the PMOS MP9 is in the working state, the gate terminal voltage of the PMOS MP9 gradually rises from the ground VSS to the power supply VDD to release the forcing effect on the output point _vOP .

Looking further, the NMOS and PMOS constituting the latch circuit of the present invention include NMOS MN6, NMOS MN7, PMOS MP6, and PMOS MP7, wherein NMOS MN6 and NMOS MN7 constitute a positive feedback circuit, and PMOS MP6 and PMOS MP7 constitute a positive feedback circuit. Specifically, the source terminal of the NMOS MN6 is connected to the point P1, and the gate terminal of the NMOS MN6 is connected to the output v _OP . In this way, in the reset state, the drain terminal of the power supply VDD is forcibly connected to the output v _ON through the MOS transistor connected to it. During normal operation, the source voltage is discharged from VDD through the NMOS input circuit until VSS. At the same time, the source terminal of the NMOS MN7 is connected to the point N1, and its gate terminal is connected to the output _vON . In this way, in the reset state, the MOS transistor connected to it is forced to the power supply VDD, and the drain terminal is connected to the output v _OP . During normal operation, the source voltage is discharged from VDD through the NMOS input circuit until VSS. In addition, the source terminal of the PMOS MP6 is connected to the power supply VDD, the drain terminal is connected to _vON , and the gate terminal is connected to _vOP . The source terminal of the PMOS MP7 is connected to the power supply VDD, the drain terminal is connected to _vOP , and the gate terminal is connected to _vON . In this way, a positive feedback circuit can be formed with PMOS MP6 to speed up the circuit speed.

Moreover, in FIG. 1 , several transistors for resetting are also provided, including NMOS transistors and PMOS transistors. Specifically, it includes NMOSMR1 and NMOSMR2 composed of NMOS transistors. The gate terminal is connected to the inverted signal of the clock signal latch, and the source terminal is connected to the ground line VSS. The drain terminal of NMOSMR1 is connected to the N2 node for resetting N2 to VSS in the reset state. The drain terminal of NMOSMR2 is connected to the P2 node for resetting P2 to VSS in the reset state.

At the same time, it also includes PMOSMR3 and PMOSMR4 composed of PMOS transistors. The gate terminal is connected to the clock signal latch, and the source terminal is connected to the power supply VDD. The drain terminal of PMOSMR3 is connected to the P1 node for resetting P1 to VDD in the reset state. The drain terminal of PMOSMR4 is connected to the N1 node for resetting N1 to VDD in the reset state.

Furthermore, as shown in FIG. 2 , the present invention can also provide a simplified implementation manner without NMOS MN2, NMOS MN4, PMOS MP2, and PMOS MP4. Doing so can save the entire circuit area, increase the operating speed, and reduce power consumption. However, the kickback noise is slightly worse than the original circuit.

The working principle of the present invention is as follows:

On the two inverters connected back to back in the present invention, the two inverters are PMOS MN6+PMOS MP6 and NMOS MN7+NMOS MP7 back-to-back connection relationship so that they form a positive feedback for amplifying the magnitude relationship of the input signal , get the logical output result.

作为它的反相信号，为高电平。此时，非标注的MOS管导通 P1，N1，v_OP和v_ON被重置到VDD。P2和N2被重置到VSS。B点为输入信号中最小的一个再减一个阈值电压大小，T点为输入信号中最大一个再加一个阈值电压大小。NMOS MN5和PMOS MP5在重置时处于断开状态。之后，时钟信号latch上升沿到来时，所有非标注的MOS管断开，释放各个节点。由此，NMOSMN5和PMOS MP5导通，整个比较器开始工作。The non-labeled MOS transistors in Figures 1 and 2 are used to reset the output signal. When the latch clock signal is low,

As its inverse signal, it is high level. At this time, the non-labeled MOS transistors are turned on P1, N1, v _OP and v _ON are reset to VDD. P2 and N2 are reset to VSS. Point B is the smallest one of the input signals minus a threshold voltage, and point T is the largest one of the input signals plus a threshold voltage. NMOS MN5 and PMOS MP5 are disconnected at reset. After that, when the rising edge of the clock signal latch arrives, all non-labeled MOS transistors are disconnected, releasing each node. As a result, NMOSMN5 and PMOS MP5 are turned on, and the entire comparator starts to work.

During implementation, the latch signal transitions from VSS to VDD at 0.1ns. The voltage of the two points P1 and N1 was originally reset to VDD by the non-labeled MOS transistor, and now it starts to discharge to VSS. Similarly, P2 and N2 were originally reset to VSS by non-marked MOS transistors, and now they start to charge VDD. Note that the voltage at point B and point T is indeterminate in the reset state, but depends on the specific input voltage. Let V _I be a set of differential voltages V _IP - V _IN =0.5V+10mV. _VR is another set of differential voltages V _IP - V _IN = 0.5V. The example in the figure VI is _10mV greater than VR _. So _vOP finally outputs VDD, and _vON finally outputs VSS. This result is called a logical "1". If V _I is smaller than VR, then _vOP finally outputs VSS, and _{vON finally} outputs VDD. This result is called a logical "0". The time from the rising edge of the clock to when one of NMOS MN6 and NMOS MN7 is turned on first can be represented by N-Phase1. N-Phase2 means that one of NMOS MN6 and NMOS MN7 is first turned on until |v _OP -v _ON | reaches VDD/2. P-Phase indicates the time from the rising edge of the clock to when one of PMOS MP8 and PMOS MP9 is turned off first.

Can be added to introduce 100mV common mode voltage mismatch. At this time, _VICM =0.8V, _VRCM =0.9V, and _VI is still _10mV larger than VR. It can be seen that _vOP tends to the wrong VSS, while _vON tends to the wrong VDD during the 0.3 to 0.5 ns time period. In a traditional fully differential comparator, at this time, _vOP and _vON will continue to change in the wrong direction, resulting in a wrong comparison result. Relying on the circuit structure of the present invention, after 0.5ns, v _OP and v _ON self-correct the wrong direction, and finally obtain the correct logic "1".

It should be noted that there are differences in this time under different processes and VDD voltages. The time of 0.1 ns and the following 0.3 ns and 0.5 ns listed in the present invention is obtained when the feature size is 180 nm and VDD is 1.8 V. For some advanced processes, such as 14nm and 22nm, these times will be reduced to the ps level.

Combining with the actual implementation, as shown in Figure 3, it is an example of the voltage waveform when there is no common mode voltage mismatch. The adopted process feature size is 180nm, and the power supply voltage VDD is 1.8V. For other processes and supply voltages, the waveforms are similar and the operating time to complete a comparison will vary. In Figure 3, latch represents the clock signal. When the rising edge of latch comes, the whole comparator starts to work. Among them, nodes P1 and N1 correspond to P1 and N1 in the circuit diagram. They start to discharge from the reset state VDD until VSS, which can be divided into two stages. Specifically, the first stage of the process corresponds to the N-Phase1 described in the figure, and this stage of the process indicates that P1 and N1 drop from the VDD voltage to the VDD-V _TH voltage. During this process, both MN6 and MN7 are off. The N-Phase2 process refers to the process that P1 and N1 are turned on due to the source voltage drop to VDD-V _TH , until the output |v _OP -v _ON | reaches 0.5VDD. When the output |v _OP -v _ON | reaches 0.5VDD, it means that the comparator has output the logic result that can be distinguished by the latter stage.

Meanwhile, nodes P2 and N2 correspond to P2 and N2 in the circuit diagram. They charge from the reset state VSS until they reach VDD-V _TH and turn off, releasing control of the output points v _OP and v _ON . Corresponds to the P-Phase process in the waveform diagram. The voltage waveforms of the two output nodes of _vOP and _vON in the corresponding circuit diagram of vop and von in the figure. They are initially reset at VDD. When the whole circuit enters the N-Phase2 process, the discharge starts and the voltage drops. At the same time, the positive feedback structure formed by MN6-7 and MP6-7 begins to separate the two output voltages and amplify the difference between them. In the example waveform V _I is V _IP - V _IN , _{VR is V RP -} V _RN , and V _I is 10mV greater than VR _. Therefore, the output result _vOP is VDD, and _vON is VSS, that is, the logical result of logic '1' is obtained.

As shown in Figure 4, it provides an example of the voltage waveform situation with a 100mV common-mode voltage mismatch. The process feature size is 180nm, and the power supply voltage VDD is 1.8V. For other processes and supply voltages, the waveforms are similar and the operating time to complete a comparison will vary. The latch in Figure 4 represents the clock signal. When the rising edge of latch comes, the whole comparator starts to work.

Specifically, the nodes P1 and N1 therein correspond to P1 and N1 in the circuit diagram. They start to discharge from the reset state VDD until VSS. Due to the existence of 100mV common-mode mismatch, although the difference between _VI and VR is still only _10mV , the voltage waveforms of P1 and N1 are not like Figure 3. There is no common-mode voltage mismatch. As in the case of matching, the voltage waveforms of P1 and N1 do not fit well. Among them, nodes P2 and N2 correspond to P2 and N2 in the circuit diagram. They charge from the reset state VSS until they reach VDD-V _TH and turn off, releasing control of the output points v _OP and v _ON . Then continue to charge to VDD. Due to the existence of 100mV common-mode mismatch, although the difference between V _I and _VR is still only 10mV, the voltage waveforms of P2 and N2 are not the same as those in the above figure without common-mode voltage mismatch. The voltage waveforms of P2 and N2 Not a good fit.

At the same time, the voltage waveforms of the two output nodes of _vOP and _vON in the corresponding circuit diagram of vop and von in the figure. They are initially reset at VDD. When the rising edge of the clock signal latch comes and MN6 and MN7 are turned on, v _OP and v _ON begin to discharge. But due to a 100mV mismatch in the common mode voltage (V _ICM is 100mV less than _VRCM in the example), during the 0.3ns to 0.5ns period, MN1-5 dominate, pulling vop to the wrong VSS and von to the wrong VDD. For traditional fully differential dynamic comparators, a false logic '0' will eventually be output. Because the present invention adds complementary PMOS MP1, PMOS MP2, PMOS MP3, PMOS MP4, and PMOS MP5. After 0.5ns, PMOS MP1, PMOS MP2, PMOS MP3, PMOS MP4, PMOS MP5 will dominate, pulling vop and von that are tending towards the wrong result back into the correct direction, still getting a logical '1' result.

As shown in FIG. 5 , during the actual implementation, the complementary fully differential dynamic comparator constructed by the present invention can be formed into a 19-bit pipeline analog-to-digital converter to realize effective function expansion.

The whole system quantizes the analog signals V _IP -V _IN in the figure into a 19-bit digital code output. There are a total of six stages of the pipeline, and each stage uses 16 comparators according to the present invention. The entire pipelined analog-to-digital converter is controlled by a periodic clock and operates as follows:

In the first clock cycle, the input signals V _IP - V _IN are input from the far left to the first stage "3.5-bit multiplying digital-to-analog converter" and 16 comparators provided by the present invention. The V _RP and V _RN input terminals of the first-stage 16 comparators provided by the present invention will be connected to different reference voltages:

V _RP - V _RN = -15/16V (1st comparator),

V _RP - V _RN = -13/16V, 2nd comparator),

V _RP - V _RN = -11/16V (3rd comparator),

V _RP - V _RN = -9/16V,...

V _RP -V _RN = -7/16V,

V _RP -V _RN = -5/16V,

V _RP -V _RN = -3/16V,

V _RP -V _RN = -1/16V,

V _RP - V _RN = 1/16V,

V _RP - V _RN = 3/16V,

V _RP - V _RN = 5/16V,

V _RP - V _RN = 7/16V,

V _RP - V _RN = 9/16V,

V _RP - V _RN = 11/16V,

V _RP - V _RN = 13/16V,

V _RP - V _RN = 15/16V (16th comparator).

It is used to quantize the input signal V _IP -V _IN in the range of -1V to +1V. For example, if one of the 16 comparators is connected to V _RP -V _RN = 1/16V, then if the input signal is greater than 1/16V, the comparator will output logic '1'; if it is less than 1/16V, the comparator will output logic '0'. Assuming that the input signal for this clock cycle is 2/16V, then the 16 logical results generated by the 16 comparisons will be 1111-1111-1000-000, with 9 logical '1' and 7 logical '0', indicating that the signal is Quantization is in the 9th interval of the first level.

Since there are only 16 comparators, the first stage can only quantize 4 bits. In order to achieve a quantization accuracy of 19 bits, the coarse quantization result needs to be input into the first-stage "3.5-bit multiplying digital-to-analog converter" above. The residual voltage (in this embodiment, the input signal is 2/16V minus the comparison voltage of the ninth quantization interval 1/16V) is amplified, and then taken to the subsequent stage for further quantization. At the same time, the result (9 in this embodiment) is recorded in the "digital alignment correction" module at the bottom, and the quantization result with 19-bit precision is output uniformly after all the quantization of the subsequent stage is completed.

In the second clock cycle, the 16 comparators corresponding to the second stage will receive the residual voltage generated by the first stage "3.5-bit multiplying digital-to-analog converter" (in this embodiment, the input signal is 2/16V minus the 9th The comparison voltage of each quantization interval is 1/16V) the amplified voltage. Like the 16 comparators in the first stage, V _RP and V _RN will also be connected to different reference voltages to further quantify the amplified residual voltage given by the first stage to obtain 16 logical results. On the one hand, the 16 logic results are given to the upper second stage "3.5-bit multiplying digital-to-analog converter" to generate the input signal required for the third stage quantization, and on the other hand, the results are also stored in the lower part like the first stage""Digital Alignment Correction" module, after waiting for all the quantization of the subsequent stage, the quantization result of 19-bit precision will be output uniformly.

The third clock cycle and so on, until the sixth clock cycle. Since stage 6 already satisfies 19-bit quantization accuracy, the "3.5-bit multiplying digital-to-analog converter" block is no longer required to continue generating headroom voltages for the next stage of quantization. After the 16 comparators of the sixth stage complete the comparison and obtain the quantization result, the "digital alignment correction" module that stores the quantization result of each stage of each clock cycle will integrate the quantization information of each stage to obtain the final 19-bit quantized digital result.

As far as the comparator is concerned, the comparison accuracy of each stage of the comparator directly determines the correctness of the final output 19-bit quantized digital result. And the mismatch of the common mode voltage, that is, the common mode of the residual voltage output by each stage "3.5-bit multiplying digital-to-analog converter" to the next stage and the reference voltage connected to each comparator V _RP and V _RN The mismatch between the common modes will degrade the comparison accuracy of the comparator. This will seriously affect the final 19-bit output result and overall system performance. The usual solution to this problem is to spend a lot of area and power on the "3.5-bit multiplying digital-to-analog converter" and the driver circuit that generates V _RP and V _RN to try to make the two common-mode voltages as consistent as possible , to improve the accuracy of the comparator. The present invention solves this problem starting from the comparator itself. Therefore, the entire upper system will not have to spend extra cost to stabilize the common mode voltage.

As can be seen from the above-mentioned textual description and in conjunction with the accompanying drawings, after adopting the present invention, it has the following advantages:

1. Under the mismatch of 100mV, the offset voltage is close to 0mV, which is much smaller than the traditional 200mV and has better stability.

2. The design pressure of the upper system is relieved, and the area and power consumption of the upper system are reduced.

3. There is no need to take a two-input dynamic comparator, which reduces the difficulty of implementation.

4. A complementary structure can be provided, and PMOS and NMOS are introduced into the comparator as input transistors at the same time, thereby realizing the function of being insensitive to common mode mismatch.

In addition, the indicated orientation or positional relationship described in the present invention is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or structure must have A specific orientation, or operation with a specific orientation configuration, should not be construed as a limitation of the present invention.

The terms "primary" and "secondary" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "primary", "secondary" may expressly or implicitly include one or more of that feature. In the description of the present invention, "several" means two or more, unless otherwise expressly and specifically defined.

Likewise, the terms "first" and "second" are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, terms such as "connection" and "arrangement" should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integration; it may be a mechanical The connection can also be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be an internal connection between two components or an interaction relationship between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations. And it can be directly on another component or indirectly on that other component. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top" , "bottom", "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the indicated device. Or the components must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. It should be pointed out that for those skilled in the art, some improvements can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims (6)

1. A complementary fully differential dynamic comparator for resisting common-mode voltage mismatch, characterized by: the device comprises an NMOS input part, a PMOS input part, a latch circuit and a reset MOS switch, wherein the NMOS input part adopts a plurality of NMOSs to be connected to form a differential input circuit; the PMOS input part adopts a plurality of PMOS to be connected to form a differential input circuit; the latch circuit adopts a positive feedback circuit formed by a plurality of NMOS and PMOS, wherein the substrates of the NMOS are connected with a ground VSS, and the substrates of the PMOS are connected with a power supply VDD.

2. The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of claim 1, wherein: the NMOS of the NMOS input part comprises an NMOS MN1, an NMOS MN2, an NMOS MN3, an NMOS MN4 and an NMOS MN5, and the grid end of the NMOS MN1 is connected with an input signal V _IP The grid end of the NMOS MN2 is connected with an input signal V _RN The grid end of the NMOS MN3 is connected with an input signal V _RP The grid end of the NMOS MN4 is connected with an input signal V _IN The source ends of the NMOS MN1, the NMOS MN2, the NMOS MN3 and the NMOS MN4 are connected, a connection point B is arranged between the source ends of the NMOS MN1 and the NMOS MN2 and the drain end of the NMOS MN5, the connection point P1 is arranged at the drain end of the NMOS MN1 and the drain end of the NMOS MN2, the connection point N1 is arranged at the drain end of the NMOS MN3 and the drain end of the NMOS MN4, the NMOS MN5 is a pseudo current source driven by a clock latch, the clock latch is connected with the gate end of the NMOS MN5, and the source end of the NMOS MN5 is connected with a grounded VSS.

3. The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of claim 1, wherein: the PMOS comprises PMOS MP1, PMOS MP2, PMOS MP3, PMOS MP4, PMOS MP5, PMOS MP8 and PMOS M9, and the gate terminal of the PMOS MP1 is connected with an input signal V _IN The gate terminal of the PMOS MP2 is connected with an input signal V _RP The gate terminal of the PMOS MP3 is connected with an input signal V _RN The gate terminal of the PMOS MP4 is connected with an input signal V _IP The source ends of the PMOS MP1, the PMOS MP2, the PMOS MP3 and the PMOS MP4 are connected and a connection point T is arranged with the drain end of the PMOS MP5, the connection point of the drain ends of the PMOS MP1 and the PMOS MP2 is a point N2, the connection point of the drain ends of the PMOS MP3 and the PMOS MP4 is a point P2, the PMOS MP5 is driven by the inverse signal of the clock latch, and the clock latch is used for driving the PMOS MP5The source end of the PMOS MP5 is connected with a power supply VDD, the source end of the PMOS MP8 is connected with the power supply VDD, the grid end is connected with a point N2, and the drain end is connected with an output v _ON The source end of the PMOS MP9 is connected with a power supply VDD, the grid end is connected with a point P2, and the drain end is connected with an output v _OP Are connected.

4. The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of claim 3, wherein: when the PMOS MP8 is in a reset state, the voltage of the grid end is grounded VSS and is in a conducting state, v _ON Reset at power supply VDD; when the PMOS MP8 is in a working state, the voltage of the grid end of the PMOS MP8 is gradually increased from the grounded VSS to the power supply VDD to release the voltage to an output point v _ON The forcing action of (2).

5. The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of claim 3, wherein: when the PMOS MP9 is in a reset state, the grid end voltage is grounded VSS and is in a conducting state v _OP Reset at power supply VDD; when the PMOS MP9 is in a working state, the voltage of the grid end of the PMOS MP9 is gradually increased from the grounded VSS to the power supply VDD to release the voltage to an output point v _OP The forcing action of (2).

6. The complementary fully differential dynamic comparator for resisting common-mode voltage mismatch of claim 1, wherein: the NMOS and the PMOS which form the latch circuit comprise NMOS MN6, NMOS MN7, PMOS MP6 and PMOS MP7, wherein the NMOS MN6 and the NMOS MN7 form a positive feedback circuit, the PMOS MP6 and the PMOS MP7 form a positive feedback circuit, the connection position of the source end of the NMOS MN6 is a point P1, the grid end of the point P1 is connected with the output v _OP The source end of the NMOS MN7 is connected with a point N1, and the grid end of the NMOS MN is connected with the output v _ON The source end of the PMOS MP6 is connected with a power supply VDD, and the drain end is connected with v _ON Connected to gate terminal v _OP The source end of the PMOS MP7 is connected with a power supply VDD, and the drain end is connected with v _OP Connected with gate terminal v _ON Are connected.

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