CN115148241A - Sense amplifier and semiconductor memory - Google Patents

Abstract

The utility model provides a sense amplifier and semiconductor memory, including the control module, it is equipped with input and first output, be used for acquireing the temperature data of memory cell, carry out delay processing to the first control signal that its input received according to the temperature data of memory cell and generate the second control signal, adjust the time of amplifying the module switch-on first power end, adjust the charge sharing time of bit line or complementary bit line and memory cell, the amplifying module, its first control end is connected with the first output of control module, it is used for communicateing first power end under the control of sensing amplification stage second control signal, enlarge the voltage difference between bit line and complementary bit line under the drive of first power end. By the arrangement, the charge sharing voltage on the bit line and the complementary bit line is ensured to be the maximum value at the end time of the charge sharing phase, and the voltages on the bit line and the complementary bit line are accurately amplified in the sensing amplification phase.

Description

Sense Amplifiers and Semiconductor Memory

technical field

The present disclosure relates to, but is not limited to, sense amplifiers and semiconductor memories.

Background technique

With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly.

A sense amplifier (Sense Amplifier: SA for short) is an important part of a semiconductor memory, and its main function is to sense and amplify a small signal on a bit line, and then perform a read or write operation. The small signal on the bit line is generated by the charge sharing between the memory cell and the bit line or the complementary bit line. The magnitude of the small signal on the bit line is related to the accuracy of the sense amplifier's sense amplification.

SUMMARY OF THE INVENTION

The present disclosure provides a sense amplifier, including:

A control module, which is provided with an input terminal and a first output terminal, is used to obtain the temperature data of the storage unit, performs delay processing on the first control signal received by the input terminal according to the temperature data of the storage unit to generate a second control signal, and adjusts the The time when the amplifying module is connected to the first power supply terminal adjusts the charge sharing time between the bit line or the complementary bit line and the storage unit;

The amplifying module, the first control terminal of which is connected to the first output terminal of the control module, which is used to connect the first power terminal under the control of the second control signal in the sensing amplification stage, and amplify the bit line driven by the first power terminal and the voltage difference between the complementary bit line.

In some embodiments, the control module is further provided with a second output terminal, which is further configured to perform a non-operation on the second control signal to generate a third control signal;

The amplifying module is further provided with a second control terminal; the second control terminal is connected to the second output terminal of the control module, and is used for connecting the second power terminal under the control of the third control signal;

Wherein, the voltage of the first power supply terminal is greater than the voltage of the second power supply terminal.

In some embodiments, the control module includes:

a control unit, which is provided with an output terminal for generating a delay adjustment signal according to the temperature data of the storage unit;

The adjustment unit is provided with an input end, an output end and a control end, the control end is connected to the output end of the control unit, the input end receives the first control signal, and performs delay processing on the first control signal according to the delay adjustment signal, and outputs the first control signal. Two control signals.

In some embodiments, the control module further includes:

The input end of the first inverter is connected with the output end of the adjusting unit, and is used for performing a negation operation on the second control signal and outputting the third control signal.

In some embodiments, the control unit includes three output terminals, the delay adjustment signal includes three gating signals, and the adjustment unit includes:

a first adjustment sub-unit, the output end of which is connected to the first input end of the selection unit, and is used for delaying the first control signal and outputting the fourth control signal;

The second adjustment sub-unit, the output end of which is connected to the second input end of the selection unit, is used for delaying the first control signal and outputting the fifth control signal;

The third adjustment sub-unit, the output end of which is connected to the third input end of the selection unit, is used for delaying the first control signal and outputting the sixth control signal; wherein, the delay amount of the fourth control signal, the delay of the fifth control signal The delay amount and the delay amount of the sixth control signal are different;

The selection unit is also provided with an output end and three control ends, each control end is connected with the corresponding output end of the control unit, and receives the corresponding gating signal; One of the control signal, the fifth control signal and the sixth control signal is selected for output; the output signal of the selection unit is used to control the first control terminal of the amplifying module.

In some embodiments, the adjustment unit further includes:

The input end of the second inverter is connected to the output end of the selection unit, and is used for outputting after negating the output signal of the selection unit; the output signal of the second inverter is used to control the first control end of the amplifying module.

In some embodiments, the control unit is used to:

When the temperature data is within the first temperature range, the outputted first strobe signal is a valid value, and the outputted second strobe signal and the third strobe signal are invalid values; the control selection unit selects the fourth control signal to output;

When the temperature data is within the second temperature range, the outputted second strobe signal is a valid value, and the outputted first strobe signal and the third strobe signal are invalid values; the control selection unit selects the fifth control signal to output;

When the temperature data is within the third temperature range, the outputted third strobe signal is a valid value, and the outputted first strobe signal and the second strobe signal are invalid values; the control selection unit selects the sixth control signal to output;

Wherein, the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the delay amount of the fourth control signal is less than or equal to The delay amount of the fifth control signal is smaller than the delay amount of the sixth control signal.

In some embodiments, the first regulating subunit includes:

a first pulse generator, the input terminal of which receives the first control signal, and is used for generating the first pulse signal according to the first control signal;

a first delay circuit, the input terminal of which receives the first control signal, performs delay processing on the first control signal and outputs the first delay signal;

a second pulse generator, the input terminal of which is connected to the output terminal of the first delay circuit, and is used for generating a second pulse signal according to the first delay signal;

a first latch, the first input terminal of which is connected to the first pulse generator, and the second input terminal of which is connected to the second pulse generator, and is used for generating a fourth control signal according to the first pulse signal and the second pulse signal .

In some embodiments, the second regulatory subunit includes:

a third pulse generator, the input terminal of which receives the first control signal, and is used for generating a third pulse signal according to the first control signal;

a second delay circuit, the input terminal of which receives the first control signal, and outputs a second delay signal after delaying the first control signal, and the delay amount of the second delay circuit is greater than the delay amount of the first delay circuit;

a fourth pulse generator, the input terminal of which is connected to the output terminal of the second delay circuit, and used for generating a fourth pulse signal according to the second delay signal;

The second latch, whose first input terminal is connected to the third pulse generator, and whose second input terminal is connected to the fourth pulse generator, is used for generating the fifth control signal according to the third pulse signal and the fourth pulse signal .

In some embodiments, the third regulatory subunit includes:

a fifth pulse generator, the input terminal of which receives the first control signal, and is used for generating the fifth pulse signal according to the first control signal;

a third delay circuit, the input terminal of which receives the first control signal, and outputs a third delay signal after delaying the first control signal, and the delay amount of the third delay circuit is greater than the delay amount of the second delay circuit;

a sixth pulse generator, the input terminal of which is connected to the output terminal of the third delay circuit, for generating the sixth pulse signal according to the third delay signal;

The third latch, the first input terminal of which is connected to the fifth pulse generator, and the second input terminal of which is connected to the sixth pulse generator, which is used for generating the sixth control signal according to the fifth pulse signal and the sixth pulse signal .

In some embodiments, the structures of the first pulse generator, the second pulse generator, the third pulse generator, the fourth pulse generator, the fifth pulse generator, and the sixth pulse generator are the same.

In some embodiments, the first pulse generator includes:

Odd number of third inverters, the output end of the third inverter of the upper stage is connected with the input end of the third inverter of the next stage; the input end of the third inverter of the first stage receives the first control signal, the output end of the third inverter of the last stage is connected with the second input end of the first NAND gate;

The first NAND gate receives the first control signal at its first input and outputs the first pulse signal at its output.

In some embodiments, the first latch, the second latch and the third latch have the same structure, and the first latch includes:

The second NAND gate; its first input terminal is used as the first input terminal of the first latch, its second input terminal is connected to the output terminal of the third NAND gate, and its output terminal is connected to the first input terminal of the third NAND gate. an input connection;

The third NAND gate; the second input terminal is used as the second input terminal of the first latch, and its output terminal is used as the output terminal of the first latch.

In some embodiments, the first delay circuit includes:

a first buffer, the input terminal of which receives the first control signal;

The input end of the second buffer is connected to the output end of the first buffer, and the output end of the second buffer outputs the first delay signal.

In some embodiments, the second delay circuit includes:

a third buffer, the input terminal of which receives the first control signal;

a fourth buffer, the input terminal of which is connected to the output terminal of the third buffer;

a fifth buffer, the input terminal of which is connected to the output terminal of the fourth buffer;

The input end of the sixth buffer is connected to the output end of the fifth buffer, and the output end of the sixth buffer is the second delayed signal.

In some embodiments, the third delay circuit includes:

a seventh buffer, the input terminal of which receives the first control signal;

an eighth buffer, the input end of which is connected to the output end of the seventh buffer;

a ninth buffer, the input end of which is connected to the output end of the eighth buffer;

a tenth buffer, the input terminal of which is connected to the output terminal of the ninth buffer;

The eleventh buffer, the input terminal of which is connected to the output terminal of the tenth buffer;

The input end of the twelfth buffer is connected to the output end of the eleventh buffer, and the output end of the twelfth buffer outputs the third delay signal.

In some embodiments, the control unit includes:

a temperature sensor, which is used to detect temperature data of the storage unit, and generate temperature encoded data according to the temperature data;

The temperature decoder, whose input end is connected with the output end of the temperature sensor, is used for generating a delay adjustment signal according to the temperature encoded data.

In some embodiments, the amplification module includes:

The third P-type transistor, the source of which is connected to the first power supply terminal, and the gate of which is used as the first control terminal of the amplifying module;

a first P-type transistor, the source of which is connected to the drain of the third P-type transistor, and the gate of which is connected to the drain of the second P-type transistor;

a second P-type transistor, the source of which is connected to the source of the first P-type transistor, and the gate of which is connected to the drain of the first P-type transistor;

a first N-type transistor, whose drain is connected to the drain of the first P-type transistor, whose gate is connected to the second N-type transistor, whose gate is connected to a complementary bit line, and whose source is indirectly coupled to the second power supply terminal;

The second N-type transistor has its drain connected to the drain of the second P-type transistor, its gate connected to the first N-type transistor, its gate connected to the bit line, and its source connected to the source of the first N-type transistor.

In some embodiments, the amplification module includes:

The source of the third N-type transistor is connected to the second power supply terminal, the gate is used as the second control terminal of the amplifying module, and the drain is connected to the source of the first N-type transistor.

Another embodiment of the present disclosure provides a semiconductor memory including the sense amplifier involved in the above embodiments.

The sense amplifier and semiconductor memory provided by the present disclosure include a control module and an amplifying module. The control module performs delay processing on the first control signal according to the temperature data of the storage unit, so as to adjust the level change time of the first control signal, so as to realize the change of the first control signal according to the temperature data of the storage unit. The temperature data adjusts the end time of the charge sharing phase, compensates for the change of the voltage driving capability of the memory cell due to the change of temperature data, and ensures that the charge sharing voltage formed on the bit line and the complementary bit line at the end of the charge sharing phase is The maximum value is achieved to accurately amplify the voltage on the bit line and the complementary bit line in the sense amplification stage.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure.

1 is a schematic diagram of the circuit structure of a sense amplifier;

2A is a schematic diagram of a working principle of a sense amplifier in a charge sharing stage;

2B is a schematic diagram of another working principle of a sense amplifier in a charge sharing stage;

FIG. 2C is a schematic diagram of another working principle of a sense amplifier in a charge sharing stage;

FIG. 3 is a schematic diagram of a circuit structure of a sense amplifier provided by an embodiment of the present application;

4 is a schematic diagram of a circuit structure of a control module provided by an embodiment of the present application;

5A is a schematic diagram of a circuit structure of a first regulating circuit provided by an embodiment of the present application;

FIG. 5B is a schematic diagram of a working principle of a first regulating circuit provided by an embodiment of the present application;

5C is a schematic diagram of another working principle of the first regulating circuit provided by an embodiment of the present application;

6A is a schematic diagram of a circuit structure of a second regulating circuit provided by an embodiment of the present application;

FIG. 6B is a schematic diagram of the working principle of the second regulating circuit provided by an embodiment of the present application;

7A is a schematic diagram of a circuit structure of a third regulating circuit provided by an embodiment of the present application;

FIG. 7B is a schematic diagram of the working principle of a third regulating circuit provided by an embodiment of the present application;

8A is a schematic diagram of a working principle of a sense amplifier provided by an embodiment of the present application;

FIG. 8B is a schematic diagram of another working principle of the sense amplifier provided by an embodiment of the present application;

FIG. 8C is a schematic diagram of yet another working principle of the sense amplifier provided by an embodiment of the present application.

Reference number:

200, amplification module; 300, storage unit; 100, control module; 120, control unit; 110, adjustment unit; 111, first adjustment subunit; 112, second adjustment subunit; 113, third adjustment subunit; 121 , temperature sensor; 122, temperature decoder; 130, first inverter; 140, second inverter;

310, the first pulse generator; 330, the second pulse generator; 320, the first delay circuit; 340, the first latch; 311, the first NAND gate; 312, the third inverter; 331, the first Four NAND gates; 332, the fourth inverter; 341, the second NAND gate; 342, the third NAND gate; 321, the first buffer; 322, the second buffer;

410, the third pulse generator; 420, the second delay circuit; 430, the fourth pulse generator; 440, the second latch; 411, the fifth NAND gate; 412, the fifth inverter; 431, the first Six NAND gate; 432, sixth inverter; 441, seventh NAND gate; 442, eighth NAND gate; 421, third buffer; 422, fourth buffer; 423, fifth buffer; 424. sixth buffer;

510, the fifth pulse generator; 520, the third delay circuit; 530, the sixth pulse generator; 540, the third latch; 511, the ninth NAND gate; 512, the seventh inverter; 531, the first Ten NAND gate; 532, eighth inverter; 541, eleventh NAND gate; 542, twelfth NAND gate; 521, seventh buffer; 522, eighth buffer; 523, ninth buffer 524, the tenth buffer; 525, the eleventh buffer; 526, the twelfth buffer.

The above-mentioned drawings have shown clear embodiments of the present disclosure, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by referring to specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as recited in the appended claims.

As shown in FIG. 1, a sense amplifier includes an amplification module 200, and the amplification module 200 includes a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a first N-type transistor N1, a second N-type transistor N1, and a second N-type transistor P2. type transistor N2 and a third N-type transistor N3.

After the source of the first P-type transistor P1 is connected to the source of the second P-type transistor P2, it is connected to the drain of the third P-type transistor P3, and the source of the third P-type transistor P3 is connected to the first power supply terminal. After the source of the first N-type transistor N1 is connected to the source of the second N-type transistor N2, it is connected to the drain of the third N-type transistor N3, and the source of the third N-type transistor N3 is connected to the second power supply terminal.

The drain of the first N-type transistor N1 is connected to the drain of the first P-type transistor P1 and then connected to the bit line BL. The drain of the second N-type transistor N2 is connected to the drain of the second P-type transistor P2 and then connected to the complementary bit line BLB. The gate of the first N-type transistor N1 is connected to the drain of the second N-type transistor N2, the gate of the second N-type transistor N2 is connected to the drain of the first N-type transistor N1, and the gate of the second P-type transistor P2 is connected to The drain of the first P-type transistor P1 and the gate of the first P-type transistor P1 are connected to the drain of the second P-type transistor P2.

The storage unit 300 includes a control transistor SN and a storage capacitor Cs. The gate of the control transistor SN is connected to the word line WL, the first end of the control transistor SN is connected to the bit line BL, and the second end of the control transistor SN is connected to the first end of the storage capacitor Cs. , the second terminal of the storage capacitor Cs is connected to the ground terminal.

Below in conjunction with Fig. 2A, the working sequence of the sense amplifier when the storage data of the storage unit 300 is "1":

In the charge sharing phase T1, the gate of the third P-type transistor P3 receives the first power enable signal SAP to be high, and the gate of the third N-type transistor N3 receives the second power enable signal SAN to be low. Both the third N-type transistor N3 and the third P-type transistor P3 are turned off, and the amplifying module 200 is disconnected from the first power supply terminal and the second power supply terminal. The word line signal on the word line WL is at a high level, the control transistor SN in the storage unit 300 is turned on, the storage capacitor Cs in the storage unit 300 shares the charge with the bit line BL, and the voltage of the bit line BL increases.

In the sense amplification stage T2, the gate of the third P-type transistor P3 receives the first power enable signal SAP to be low, and the gate of the third N-type transistor N3 receives the second power enable signal SAN to be high. , the amplifying module 200 is connected to both the first power supply terminal and the second power supply terminal, the amplifying module 200 further drives the voltage on the bit line BL and the complementary bit line BLB, and forms a larger voltage on the bit line BL and the complementary bit line BLB Difference.

In the charge sharing stage T1, the word line signal on the word line WL is at a high level, the control transistor SN is turned on, and the storage capacitor Cs of the storage unit 300 and the parasitic capacitor C _{BL of the bit line BL} perform charge sharing. A charge sharing voltage VCS is formed on the bit line BL and the complementary bit line BLB, and the charge sharing voltage VCS is relatively weak. In the sensing amplifying stage T2, the amplifying module 200 connects the first power supply terminal and the second power supply terminal, and the amplifying module 200 performs sensing and amplifying to amplify the weak charge sharing voltage VCS into a full-scale data voltage difference. That is, let the voltage of the bit line BL be the voltage of the first power supply terminal, the voltage of the complementary bit line BLB to be the voltage of the second power supply terminal, or the voltage of the complementary bit line BLB to be the voltage of the first power supply terminal, and the voltage of the bit line BL is The voltage of the second power supply terminal.

In the sensing amplification stage T2, a certain sensing voltage is required for the sensing amplification operation. The sensing margin is defined as the difference between the charge sharing voltage VCS and the sensing voltage. The magnitude of the charge sharing voltage VCS is related to the charge sharing stage T1. related.

If the time of the charge sharing stage T1 is too short, the charge sharing between the memory cell 300 and the bit line BL or the complementary bit line BLB has not ended, the charge sharing voltage VCS does not reach the maximum value of the charge sharing, and the charge sharing voltage VCS is relatively small, which will cause If the sensing margin is small, the sensing margin will be lost. Furthermore, if the charge sharing voltage VCS is too small, so that the sensing margin is smaller than zero, the sensing result will fail. If the time of the charge sharing stage T1 is too long, the leakage path on the bit line BL or the complementary bit line BLB will cause greater charge loss, the charge sharing voltage VCS will become smaller, and the sensing margin will also be relatively small or even less than zero. Happening.

At the beginning of the design of the sense amplifier, a reasonable time of the charge sharing stage T1 is set, so that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value when the charge sharing stage ends. However, the voltage driving capability of the memory cell 300 may vary with temperature data. As shown in FIG. 2B , when the temperature data is low, the voltage driving capability of the memory cell 300 becomes stronger, the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB reaches the maximum value in advance, and the charge passes through the leakage path of the bit line BL. At the end of the charge sharing stage T1, the charge sharing voltage VCS is still relatively small, which will make the sensing margin relatively small or even less than zero, resulting in erroneous reading of data, for example: the voltage of the bit line BL in the charge sharing stage T1 is greater than the complementary bit The voltage of the line BLB goes through the sensing amplifying stage T2, so that the voltage of the bit line BL is lower than the voltage of the complementary bit line BLB, and the data "1" in the memory cell is read as the data "0". As shown in FIG. 2C , when the temperature data is high, the voltage driving capability of the memory cell 300 becomes weak. At the end of the charge sharing stage T1, the bit line BL or the complementary bit line BLB does not complete the charge sharing with the storage capacitor Cs, and the bit line The charge sharing voltage VCS on BL and the complementary bit line BLB is still relatively small, which makes the sensing margin relatively small or even smaller than zero.

In order to solve the above problems, the present disclosure provides a sense amplifier and a semiconductor memory, including a control module 100 and an amplification module 200 . The control module 100 performs delay processing on the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the amplification module 200 The time when the first power supply terminal is turned on can adjust the time for the charge sharing between the bit line BL or the complementary bit line BLB and the storage unit 300 to ensure the charge sharing on the bit line BL and the complementary bit line BLB at the end of the charge sharing stage T1 The voltage VCS is at the maximum value, so as to accurately amplify the voltage difference between the bit line BL and the complementary bit line BLB in the sense amplification stage T2.

As shown in FIG. 3 , an embodiment of the present disclosure provides a sense amplifier, including a control module 100 and an amplification module 200 . The control module 100 is provided with an input end and a first output end, and the amplification module 200 is provided with a first control end. The first output terminal of the control module 100 is connected to the first control terminal of the amplification module 200 .

The input terminal of the control module 100 receives the first control signal EN1. The control module 100 acquires the temperature data of the storage unit 300, and performs delay processing on the first control signal EN1 according to the temperature data of the storage unit 300 to generate the second control signal EN2. The amplifying module 200 is connected to the first power terminal under the control of the second control signal EN2 in the sense amplifying stage T2, and is driven by the first power terminal to amplify the voltage difference between the bit line BL and the complementary bit line BLB.

The charge sharing stage T1 and the sensing amplification stage T2 are two adjacent stages, and the ending time of the charge sharing stage T1 is the starting time of the sensing amplification stage T2. The second control signal EN2 controls the amplifying module 200 to turn on the first power supply terminal, so that the sense amplifier enters the sensing amplifying stage T2, then the level change time of the second control signal EN2 determines the starting time of the sensing amplifying stage T2, and also determines the starting time of the sensing amplifying stage T2. The end time of the charge sharing phase T1.

When the second control signal EN2 is valid at the rising edge, the time of the level change of the second control signal EN2 is the time of the rising edge, and when the second control signal EN2 is valid at the falling edge, the time of the level change of the second control signal EN2 is falling edge time.

When the temperature data of the storage unit 300 is relatively high, the delay amount of the delay processing for the first control signal EN1 is relatively large, that is, the level change time of the second control signal EN2 is relatively late, and the sense amplifier is in the charge sharing stage T1 time It is relatively long to compensate for the fact that the voltage driving capability of the memory cell 300 is weakened due to the increase of temperature data.

When the temperature data of the storage unit 300 is relatively low, the delay amount of the delay processing for the first control signal EN1 is relatively small. That is, the level change time of the second control signal EN2 is earlier, and the time of the sense amplifier in the charge sharing stage T1 is shorter to compensate for the fact that the voltage driving capability of the memory cell 300 becomes stronger due to the decrease of temperature data.

In the above technical solution, the control module 100 performs delay processing on the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the level change time of the first control signal EN1, so as to adjust the charge sharing according to the temperature data of the storage unit 300 At the end time of the stage T1, the voltage driving capability of the memory cell 300 changes due to the change of the temperature data is compensated. It is ensured that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value at the end of the charge sharing stage T1, so as to accurately amplify the voltage on the bit line BL and the complementary bit line BLB in the sensing amplification stage T2.

In some embodiments, as shown in FIG. 3 , the control module 100 is further provided with a second output terminal, the amplifying module 200 is further provided with a second control terminal, the second output terminal of the control module 100 and the second control terminal of the amplifying module 200 end connection. The control module 100 performs a non-operation on the second control signal EN2 to output a third control signal EN3, and the amplifying module 200 is connected to the second power terminal under the control of the third control signal EN3 in the sensing amplifying stage T2.

In the above technical solution, the control module 100 performs delay processing on the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the level change time of the first control signal EN1 and adjust the time when the amplifying module 200 is connected to the first power terminal . The third control signal EN3 is obtained by negating the second control signal EN2, so that the time when the amplifying module 200 is connected to the second power terminal is adapted to the time when the amplifying module 200 is connected to the first power terminal. After the amplifying module 200 turns on the first power supply terminal and the second power supply terminal, it amplifies the voltage on the bit line BL and the complementary bit line BLB, so as to adjust the start time of the sensing amplification stage T2 according to the temperature data of the storage unit 300 . , and at the same time adjust the end time of the charge sharing phase T1 according to the temperature data of the storage unit 300 .

In some embodiments, the voltage VH of the first power terminal is greater than the voltage VL of the second power terminal, and the second power terminal is usually a ground terminal.

In some embodiments, as shown in FIG. 4 , the control module 100 includes a control unit 120 , a regulation unit 110 and a first inverter 130 . The control module 100 is provided with an output end, the adjustment unit 110 is provided with an input end, an output end and a control end, and the first inverter 130 is provided with an input end and an output end.

The output end of the control unit 120 is connected to the control end of the adjustment unit 110 , and the output end of the adjustment unit 110 is connected to the input end of the first inverter 130 . The control unit 120 generates a delay adjustment signal according to the temperature data of the storage unit 300, the input terminal of the adjustment unit 110 receives the first control signal EN1, the control terminal of the adjustment unit 110 receives the delay adjustment signal, and the adjustment unit 110 controls the first control signal according to the delay adjustment signal. The signal EN1 is delayed to output the second control signal EN2, and the first inverter 130 performs the negation of the second control signal EN2 to output the third control signal EN3.

In some embodiments, as shown in FIG. 4 , the control unit 120 includes a temperature sensor 121 and a temperature decoder 122 , the temperature sensor 121 is provided with an output terminal, and the temperature decoder 122 is provided with an input terminal and an output terminal. The output terminal of the temperature sensor 121 is connected to the input terminal of the temperature decoder 122 . The temperature sensor 121 detects the temperature data of the storage unit 300, and performs encoding processing on the temperature data to generate temperature encoded data. The input end of the temperature decoder 122 is connected to the output end of the temperature sensor 121. The temperature decoder 122 decodes the temperature encoded data, and compares the decoding result with each temperature range to determine the corresponding temperature data. information, and generate a delay adjustment signal according to the gear information corresponding to the temperature data.

In some embodiments, as shown in FIG. 4 , the control unit 120 includes three output terminals, the delay adjustment signal includes three gating signals, and the adjustment unit 110 includes a first adjustment subunit 111 , a second adjustment subunit 112 , a Three adjustment subunits 113 and selection unit 114 . The selection unit 114 is provided with three input terminals, which are marked as a first input terminal, a second input terminal and a third input terminal in sequence.

The first adjustment subunit 111 is provided with an input end and an output end, the output end of the first adjustment subunit 111 is connected to the first input end of the selection unit 114, and the input end of the first adjustment subunit 111 receives the first control signal EN1, and delaying the first control signal EN1 to output a fourth control signal EN4.

The second adjustment subunit 112 is provided with an input end and an output end, the output end of the second adjustment subunit 112 is connected to the second input end of the selection unit 114, and the input end of the second adjustment subunit 112 receives the first control signal EN1, The first control signal EN1 is delayed and the fifth control signal EN5 is output.

The third adjustment subunit 113 is provided with an input end and an output end, the output end of the third adjustment subunit 113 is connected to the third input end of the selection unit 114, and the input end of the third adjustment subunit 113 receives the first control signal EN1, and delaying the first control signal EN1 to output a sixth control signal EN6.

The delay amount of the fourth control signal EN4, the delay amount of the fifth control signal EN5, and the delay amount of the sixth control signal EN6 are all different, that is, the level change time of the fourth control signal EN4, the fifth control signal EN5 The level change time of , and the level change time of the sixth control signal EN6 are different.

Wherein, when the fourth control signal EN4, the fifth control signal EN5 and the sixth control signal EN6 are all rising edge signals, the level change time is the rising edge time. When the fourth control signal EN4, the fifth control signal EN5, and the sixth control signal EN6 are all falling edge signals, the level change time is the falling edge time.

The selection unit 114 is also provided with three control terminals, each control terminal is connected with the corresponding output terminal of the control unit 120, each control terminal of the selection unit 114 receives the corresponding gating signal, and the selection unit 114 controls the three gating signals. Next, one output is selected from the fourth control signal EN4 , the fifth control signal EN5 and the sixth control signal EN6 , wherein the output terminal of the selection unit 114 outputs a signal to control the first control terminal of the amplifying module 200 .

In the above technical solution, the adjustment unit 110 includes three adjustment subunits, a selection unit 114 and a second inverter 140, and the output signals of the three adjustment subunits have different delays relative to the first control signal EN1, that is, three The timing of the level change of the output signal of the adjustment subunit is different, and the selection unit 114 selects one output from the output signals of the three adjustment subunits according to the three gating signals. Whether the three gating signals are valid is determined according to the temperature data of the storage unit 300 , so as to adjust the level change time of the first control signal EN1 according to the temperature data of the storage unit 300 , and use the output signal of the selection unit 114 to control the first control terminal of the amplifying module 200 to adjust the charge according to the temperature data of the storage unit 300 End time of sharing phase T1.

In some embodiments, there are three temperature gear ranges, labeled as a first temperature range, a second temperature range, and a third temperature range. The upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range. For example, the first temperature range is T≤20°C, the second temperature range is 20°C<T≤60°C, and the third temperature range is T>60°C.

In some embodiments, the three gating signals output by the control unit 120 are marked as a first gating signal, a second gating signal and a third gating signal. The first gate signal is used to control the selection unit 114 to select the fourth control signal EN4 to output. The second gate signal is used to control the selection unit 114 to select the fifth control signal EN5 to output. The third gate signal is used to control the selection unit 114 to select the sixth control signal EN6 to output.

In some embodiments, the delay amount of the fourth control signal EN4 is smaller than the delay amount of the fifth control signal EN5, and the delay amount of the fifth control signal EN5 is smaller than the delay amount of the sixth control signal EN6, that is, the voltage of the fourth control signal EN4 The level change time is earlier than the level change time of the fifth control signal EN5, and the level change time of the fifth control signal EN5 is earlier than the level change time of the sixth control signal EN6.

In some embodiments, when the temperature data is within the first temperature range, the first gating signal output by the control unit 120 is a valid value, and the second gating signal and the third gating signal output by the control unit 120 are invalid values , the selection unit 114 selects the fourth control signal EN4 to output under the control of the three strobe signals.

When the temperature data is within the second temperature range, the second gate signal output by the control unit 120 is a valid value, and the first gate signal and the third gate signal output by the control unit 120 are invalid values. The selection unit 114 selects the fifth control signal EN5 to output under the control of the signal number.

When the temperature data is within the third temperature range, the third strobe signal output by the control unit 120 is a valid value, and the first strobe signal and the second strobe signal output by the control unit 120 are invalid values. Under the control of the signal number, the selection unit 114 selects the sixth control signal EN6 to output.

In the above technical solution, that is, when the temperature of the storage unit 300 is higher, the selection unit 114 selects the control signal output with a larger delay, that is, the control signal output with a later level change time, so that the time of the charge sharing stage T1 is Longer, there is sufficient charge sharing time between the memory cell 300 and the bit line BL, so that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is maximized at the end of the charge sharing phase T1.

In some embodiments, as shown in FIG. 5A , the first adjustment subunit 111 includes a first pulse generator 310 , a first delay circuit 320 , a second pulse generator 330 and a first latch 340 .

Both the first pulse generator 310 and the second pulse generator 330 are provided with input terminals and output terminals. The first delay circuit 320 is provided with an input terminal and an output terminal. The first latch 340 is provided with a first input terminal, a second input terminal and an output terminal.

The output terminal of the first pulse generator 310 is connected to the first input terminal In1 of the first latch 340 , the input terminal of the second pulse generator 330 is connected to the output terminal of the first delay circuit 320 , and the output terminal of the second pulse generator 330 is connected. The output terminal is connected to the second input terminal In2 of the first latch 340 .

The input terminal of the first pulse generator 310 receives the first control signal EN1, and the first pulse generator 310 generates the first pulse signal PL1 according to the first control signal EN1. The input terminal of the first delay circuit 320 also receives the first control signal EN1, and the first delay circuit 320 delays the first control signal EN1 to output a first delay signal. The second pulse generator 330 generates the second pulse signal PL2 according to the first delay signal. The first input terminal In1 of the first latch 340 receives the first pulse signal PL1, the second input terminal In2 of the first latch 340 receives the second pulse signal PL2, and the first latch 340 receives the first pulse signal PL1 according to the first pulse signal PL1. and the second pulse signal PL2 to generate a fourth control signal EN4, which is output via the output terminal Out1.

In some embodiments, the first pulse generator 310 includes a first NAND gate 311 and an odd number of third inverters 312 . An odd number of third inverters 312 are connected in cascade, that is, the input terminal of the third inverter 312 of the first stage receives the first control signal EN1, and the input terminal of the third inverter 312 of the second stage is connected to the first control signal EN1. The output of the third inverter 312 of the stage. By analogy, the input terminal of the third inverter 312 of the last stage is connected to the output terminal of the third inverter 312 of the penultimate stage.

As shown in FIG. 5B , the first control signal EN1 is a rising edge signal, and after the first control signal EN1 undergoes an odd number of NOT operations, the output signal of the third inverter 312 of the last stage is a falling edge signal, and the first control signal The rising edge time t1 of EN1 is earlier than the falling edge time t3 of the output signal of the third inverter 312 of the last stage.

The first input end R1 of the first NAND gate 311 receives the first control signal EN1, the output end of the third inverter 312 of the last stage is connected to the second input end R2 of the first NAND gate 311, the first AND After the NOT gate 311 performs NAND operation on the first control signal EN1 and the output signal of the third inverter 312 of the last stage, it outputs the first pulse signal PL1 through its output terminal, and the pulse width of the first pulse signal PL1 is smaller than that of the first pulse signal PL1. A pulse width of the control signal EN1.

In some embodiments, as shown in FIG. 5A , the first delay circuit 320 includes a first buffer 321 and a second buffer 322 . The input terminal of the second buffer 322 is connected to the output terminal of the first buffer 321 . The input end of the first buffer 321 receives the first control signal EN1, and the output end of the second buffer 322 outputs the first delay signal. When the first control signal EN1 is a rising edge signal, after two signal delays, the rising edge time t2 of the first delay signal is later than the rising edge time t1 of the first control signal EN1.

In some embodiments, the first pulse generator 310 and the second pulse generator 330 have the same structure. Continuing to refer to FIG. 5A , the second pulse generator 330 includes a fourth NAND gate 331 and an odd number of fourth inverters 332 . The first input terminal R3 of the fourth NAND gate 331 receives the first delayed signal, and the fourth inverter 332 of the first stage receives the first delayed signal, which is input to the first delay signal of the fourth NAND gate 331 after an odd number of NOT operations. With two input terminals R4, the fourth NAND gate 331 outputs a second pulse signal PL2 through the output terminal after performing NAND operation on the first delayed signal and the first delayed signal after an odd number of NOT operations.

As shown in FIG. 5B , both the first control signal EN1 and the first delay signal are rising edge signals, and the rising edge time t1 of the first control signal EN1 is earlier than the rising edge time t2 of the first delay signal, then the first pulse signal The pulse start time t1 of PL1 is earlier than the pulse start time t2 of the second pulse signal PL2, and the time difference Δτ1 between the pulse start time of the second pulse signal PL2 and the pulse start time of the first pulse signal PL1 is equal to The time difference Δτ1 between the rising edge timing of the first delay signal and the rising edge timing of the first control signal EN1 is Δτ1. The first pulse signal PL1 and the second pulse signal PL2 have the same pulse level and the same pulse width.

In some embodiments, with continued reference to FIG. 5A , the first latch 340 includes a second NAND gate 341 and a third NAND gate 342 . The first input terminal of the second NAND gate 341 serves as the first input terminal In1 of the first latch 340 , the second input terminal of the second NAND gate 341 is connected to the output terminal of the third NAND gate 342 , the second The output terminal of the NAND gate 341 is connected to the first input terminal of the third NAND gate 342, and the second input terminal of the third NAND gate 342 is used as the second input terminal In2 of the first latch 340. The output terminal of the gate 341 serves as the output terminal Out1 of the first latch 340 .

As shown in FIG. 5C , the first control signal EN1 is a rising edge signal, and when both the first pulse signal PL1 and the second pulse signal PL2 are low-level pulses, the first input terminal In1 of the first latch 340 first receives the signal. After the low-level pulse, the second input terminal In2 of the first latch 340 receives the low-level pulse. The output end of the first latch 340 outputs a low level at the pulse start time t1 of the first pulse signal PL1 and keeps the low level. The output end of the first latch 340 outputs a high level at the pulse start time t2 of the second pulse signal PL2 and keeps the high level. That is, the fourth control signal EN4 output from the output terminal Out1 of the first latch 340 is still a rising edge signal. The rising edge time of the fourth control signal EN4 is determined by the pulse start time t2 of the second pulse signal PL2.

In some embodiments, as shown in FIG. 6A , the second adjustment subunit 112 includes a third pulse generator 410 , a second delay circuit 420 , a fourth pulse generator 430 and a second latch 440 .

Both the third pulse generator 410 and the fourth pulse generator 430 are provided with an input terminal and an output terminal, the second delay circuit 420 is provided with an input terminal and an output terminal, and the second latch 440 is provided with a first input terminal In3, a first input terminal and an output terminal. Two input terminals In4 and output terminals Out2.

The output terminal of the second delay circuit 420 is connected to the input terminal of the fourth pulse generator 430 , the output terminal of the third pulse generator 410 is connected to the first input terminal In3 of the second latch 440 , and the output terminal of the fourth pulse generator 430 The terminal is connected to the second input terminal In4 of the second latch 440 .

The input terminal of the third pulse generator 410 receives the first control signal EN1, and the third pulse generator 410 generates the third pulse signal PL3 according to the first control signal EN1. The input end of the second delay circuit 420 receives the first control signal EN1, and the second delay circuit 420 delays the first control signal EN1 to output a second delay signal. The input terminal of the fourth pulse generator 430 receives the second delay signal, and the fourth pulse generator 43 generates the fourth pulse signal PL4 according to the second delay signal. The first input terminal In3 of the second latch 440 receives the third pulse signal PL3, the second input terminal In4 of the second latch 440 receives the fourth pulse signal PL4, and the second latch 440 receives the third pulse signal PL3 according to the and the fourth pulse signal PL4 to generate the fifth control signal EN5, and output the fifth control signal EN5 via the output terminal Out2.

Wherein, the delay amount of the second delay circuit 420 is greater than the delay amount of the first delay circuit 320 . That is, the level change time of the second delay signal output by the second delay circuit 420 is later than the level change time of the first delay signal output by the first delay circuit 320 . When both the first delay signal and the second delay signal are rising edge signals, the time of the level change is the rising edge time. When both the first delay signal and the second delay signal are falling edge signals, the level change time is the falling edge time.

In some embodiments, as shown in FIG. 6A , the second delay circuit 420 includes a third buffer 421 , a fourth buffer 422 , a fifth buffer 423 and a sixth buffer 424 . The input terminal of the third buffer 421 receives the first control signal EN1 , the output terminal of the third buffer 421 is connected to the input terminal of the fourth buffer 422 , and the output terminal of the fourth buffer 422 is connected to the input terminal of the fifth buffer 423 , the output terminal of the fifth buffer 423 is connected to the input terminal of the sixth buffer 424 , and the first control signal EN1 outputs a second delayed signal after four delay processing. Compared with the first delay signal obtained after two delays, the level change time of the second delay signal obtained after four delays is later than the level change time of the first delay signal.

The structure of the third pulse generator 410 is the same as that of the first pulse generator 310 . The third pulse generator 410 includes a fifth NAND gate 411 and an odd number of cascaded fifth inverters 412. The connection relationship between the fifth NAND gate 411 and the odd number of cascaded fifth inverters 412 is the same as that of the first pulse. The generator 310 is similar and will not be repeated here. The structure of the fourth pulse generator 430 is the same as that of the first pulse generator 310 . The fourth pulse generator 430 includes a sixth NAND gate 431 and an odd number of cascaded sixth inverters 432, and the connection relationship between the sixth NAND gate 431 and the odd number of cascaded sixth inverters 432 is the same as that of the first pulse. The generator 310 is similar and will not be repeated here. The principle of generating the third pulse signal PL3 by the third pulse generator 410 and the principle of generating the fourth pulse signal PL4 by the fourth pulse generator 430 are the same as the principle of generating the first pulse signal PL1 by the first pulse generator 310 .

As shown in FIG. 6B , the third pulse signal PL3 and the fourth pulse signal PL4 have the same pulse level and the same pulse width. The pulse start time t6 of the fourth pulse signal PL4 is later than the pulse start time t5 of the third pulse signal PL3, and the pulse start time t6 of the fourth pulse signal PL4 and the pulse start time t5 of the third pulse signal PL3 are between. The time difference is the same as the time difference between the level change moment of the second delay signal and the level change moment of the first control signal EN1.

As shown in FIG. 6A , the structure of the second latch 440 is the same as that of the first latch 340 . The second latch 440 includes a seventh NAND gate 441 and an eighth NAND gate 442. The connection relationship between the seventh NAND gate 441 and the eighth NAND gate 442 is similar to that in the first latch 340, and is not shown here. Repeat. The principle of generating the fifth control signal EN5 by the second latch 440 is the same as the principle of generating the fourth control signal EN4 by the first latch 340 .

As shown in FIG. 6B , the output terminal Out2 of the second latch 440 outputs a low level at the pulse start time t5 of the third pulse signal PL3 and keeps the low level. The output terminal Out2 of the second latch 440 outputs a high level at the pulse start time t6 of the fourth pulse signal PL4 and keeps the high level. That is, the fifth control signal EN5 output by the second latch 440 is a rising edge signal. The rising edge time of the fifth control signal EN5 is determined by the pulse start time t6 of the fourth pulse signal PL4.

Since the time difference between the level change instant of the second delay signal and the level change instant of the first control signal EN1 is greater than the time difference between the level change instant of the first delay signal and the level change instant of the first control signal EN1, The time difference between the pulse start time t6 of the fourth pulse signal PL4 and the pulse start time t5 of the third pulse signal PL3 is greater than the pulse start time t2 of the second pulse signal PL2 and the pulse start time of the first pulse signal PL1 The time difference between the time points t1 means that the rising edge time t6 of the fifth control signal EN5 is later than the rising edge time t1 of the fourth control signal EN4.

In some embodiments, as shown in FIG. 7A , the third adjustment subunit 113 includes a fifth pulse generator 510 , a third delay circuit 520 , a sixth pulse generator 530 and a third latch 540 .

The fifth pulse generator 510 and the sixth pulse generator 530 are provided with an input terminal and an output terminal, the third delay circuit 520 is provided with an input terminal and an output terminal, and the third latch 540 is provided with a first input terminal In5, Two input terminals In6 and output terminals Out3.

The output terminal of the third delay circuit 520 is connected to the input terminal of the sixth pulse generator 530 , the output terminal of the fifth pulse generator 510 is connected to the first input terminal In5 of the third latch 540 , and the output terminal of the sixth pulse generator 530 The terminal is connected to the second input terminal In6 of the third latch 540 .

The input terminal of the fifth pulse generator 510 receives the first control signal EN1, and the fifth pulse generator 510 generates the fifth pulse signal PL5 according to the first control signal EN1. The input terminal of the third delay circuit 520 receives the first control signal EN1, and the third delay circuit 520 delays the first control signal EN1 to output a third delay signal. The input terminal of the sixth pulse generator 530 receives the third delay signal, and the sixth pulse generator 530 generates the sixth pulse signal PL6 according to the third delay signal. The first input terminal In5 of the third latch 540 receives the fifth pulse signal PL5, the second input terminal In6 of the third latch 540 receives the sixth pulse signal PL6, and the third latch 540 receives the fifth pulse signal PL5 according to the and the sixth pulse signal PL6 to generate a sixth control signal EN6, which is output via the output terminal Out3.

The delay amount of the third delay circuit 520 is greater than the delay amount of the second delay circuit 420 . That is, the level change time of the third delay signal output by the third delay circuit 520 is later than the level change time of the second delay signal output by the second delay circuit 420 . When both the second delay signal and the third delay signal are rising edge signals, the time of the level change is the rising edge time. When both the second delay signal and the third delay signal are falling edge signals, the time of the level change is the falling edge time.

In some embodiments, as shown in FIG. 7A , the third delay circuit 520 includes a seventh buffer 521 , an eighth buffer 522 , a ninth buffer 523 , a tenth buffer 524 , an eleventh buffer 525 and a third buffer Twelve buffers 526. The input terminal of the seventh buffer 521 receives the first control signal EN1, the input terminal of the eighth buffer 522 is connected to the output terminal of the seventh buffer 521, and the input terminal of the ninth buffer 523 is connected to the output terminal of the eighth buffer 522. The input terminal of the tenth buffer 524 is connected to the output terminal of the ninth buffer 523 , the input terminal of the eleventh buffer 525 is connected to the output terminal of the tenth buffer 524 , and the input terminal of the twelfth buffer 526 The terminal is connected to the output terminal of the eleventh buffer 525, and the output terminal of the twelfth buffer 526 outputs the third delay signal. After the first control signal EN1 is delayed for six times, the third delayed signal at the output terminal is output. By delaying six times, the level changing time of the third delayed signal is made later than the level changing time of the second delayed signal.

As shown in FIG. 7A , the structure of the fifth pulse generator 510 is the same as that of the first pulse generator 310 . The fifth pulse generator 510 includes a ninth NAND gate 511 and an odd number of cascaded seventh inverters 512. The connection relationship between the ninth NAND gate 511 and the odd number of cascaded seventh inverters 512 is the same as that of the first pulse. The generator 310 is similar and will not be repeated here. The structure of the sixth pulse generator 530 is the same as that of the first pulse generator 310 . The sixth pulse generator 530 includes a tenth NAND gate 531 and an odd number of cascaded eighth inverters 532. The tenth NAND gate 531 and the odd number of cascaded eighth inverters 532 are connected in the same relationship as the first pulse. The generator 310 is similar and will not be repeated here. The principle of generating the fifth pulse signal PL5 by the fifth pulse generator 510 and the principle of generating the sixth pulse signal PL6 by the sixth pulse generator 530 are the same as the principle of generating the first pulse signal PL1 by the first pulse generator 310, and are no longer used. Repeat.

As shown in FIG. 7B , the fifth pulse signal PL5 and the sixth pulse signal PL6 have the same pulse level and the same pulse width. The pulse start time t8 of the sixth pulse signal PL6 is later than the pulse start time t7 of the fifth pulse signal PL5, and the pulse start time t8 of the sixth pulse signal PL6 and the pulse start time t7 of the fifth pulse signal PL5 are between. The time difference is the same as the time difference between the level change instant of the third delay signal and the level change instant of the first control signal EN1.

As shown in FIG. 7A , the structure of the third latch 540 is the same as that of the first latch 340. The third latch 540 includes an eleventh NAND gate 541 and a twelfth NAND gate 542. The tenth The connection relationship between the first NAND gate 541 and the twelfth NAND gate 542 is similar to that in the first latch 340, and will not be repeated here. The principle of generating the sixth control signal EN6 by the third latch 540 is the same as the principle of generating the fourth control signal EN4 by the first latch 340 .

As shown in FIG. 7B , the output terminal Out3 of the third latch 540 outputs a low level at the pulse start time t7 of the fifth pulse signal PL5 and keeps the low level. The output terminal of the third latch 540 outputs a high level at the pulse start time t8 of the sixth pulse signal PL6 and keeps the high level. That is, the sixth control signal EN6 output by the third latch 540 is a rising edge signal. The rising edge time of the sixth control signal EN6 is determined by the pulse start time t8 of the sixth pulse signal PL6.

Since the time difference between the level change instant of the third delay signal and the level change instant of the first control signal EN1 is greater than the time difference between the level change instant of the second delay signal and the level change instant of the first control signal EN1, The time difference between the pulse start time t8 of the sixth pulse signal PL6 and the pulse start time t7 of the fifth pulse signal PL5 is greater than the pulse start time t6 of the fourth pulse signal PL4 and the pulse start time of the third pulse signal PL3 The time difference between the time points t5 means that the rising edge time t8 of the sixth control signal EN6 is later than the rising edge time t6 of the fifth control signal EN5.

In some embodiments, as shown in FIG. 4 , the control unit 120 further includes a second inverter 140 , the input terminal of the second inverter 140 is connected to the output terminal of the selection unit 114 , and the second inverter 140 is used for A negation operation is performed on the output signal of the selection unit 114 , and the output signal of the second inverter 140 is used to control the first control terminal of the amplifying module 200 . When the control unit 120 outputs a rising edge signal, the second inverter 140 outputs a falling edge signal, the first inverter 130 outputs a rising edge signal, and the falling edge signal output by the second inverter 140 controls the amplifying module 200 to sense the In the sense amplification stage T2, the first power terminal is turned on, and the rising edge signal output by the first inverter 130 controls the amplifying module 200 to turn on the second power terminal in the sense amplification stage T2.

In some embodiments, as shown in FIG. 3 , the amplifying module 200 includes a first P-type transistor P1 , a second P-type transistor P2 , a third P-type transistor P3 , a first N-type transistor N1 , and a second N-type transistor N2 and a third N-type transistor N3. The connection relationship of the transistors in the amplifying module 200 has been described in FIG. 1 and will not be repeated.

The gate of the third P-type transistor P3 serves as the first control terminal of the amplifying module 200 , and the gate of the third N-type transistor N3 serves as the second control terminal of the amplifying module 200 .

In some embodiments, the second control signal EN2 is valid for a falling edge signal, and the third control signal EN3 is valid for a rising edge signal.

In some embodiments, the first control signal EN1 is a rising edge signal, the gate of the third P-type transistor P3 is connected to the second inverter 140 , and the second control signal EN2 receiving the output of the second inverter 140 is a falling edge signal The gate of the third N-type transistor N3 is connected to the first inverter 130 , and the third control signal EN3 output by the first inverter 130 is received as a rising edge signal.

8A, 8B and 8C, with the storage unit 300 storing data as "1" and writing data as "0", the working sequence when writing data to the storage unit 300 is described below:

In the charge sharing stage T1, the word line signal on the word line WL is high, the control transistor SN in the storage unit 300 is turned on, the storage capacitor Cs in the storage unit 300 shares the charge with the bit line BL, and the voltage of the bit line BL increases.

As shown in FIG. 8A , when the temperature data of the storage unit 300 is relatively low and is in the first temperature range, the selection unit 114 selects the fourth control signal EN4 output by the first adjustment sub-unit 111 to output, compared with the fifth control signal EN5 and the sixth control signal EN6, the rising edge time of the fourth control signal EN4 is earlier, the second control signal EN2 is at a high level for a short time, the third control signal EN3 is at a low level for a short time, and the third N The time when the P-type transistor N3 and the third P-type transistor P3 are in the off state is relatively short, and the time when the amplifying module 200 is disconnected from the first power supply terminal and the second power supply terminal is relatively short, then the storage capacitor Cs in the storage unit 300 is connected to the bit line BL. The shared charge time is shorter. Since the memory cell 300 has a strong voltage driving capability when the temperature is low, it is ensured that the third N-type transistor N3 and the third P-type transistor P3 are turned on when the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value. The sensing amplification stage T2 is entered in time.

As shown in FIG. 8B , when the temperature data of the storage unit 300 rises and is located in the second temperature range, the selection unit 114 selects the fifth control signal EN5 output by the second adjustment sub-unit 112 to output, compared with the fourth control signal EN4, The rising edge time of the fifth control signal EN5 is later, the time when the second control signal EN2 is at a high level is prolonged, the time when the third control signal EN3 is at a low level is prolonged, the third N-type transistor N3 and the third P-type transistor The time when P3 is in the off state is prolonged, the time when the amplifying module 200 is disconnected from the first power supply terminal and the second power supply terminal is prolonged, and the storage capacitor Cs in the storage unit 300 shares the charge with the bit line BL for a prolonged time. Since the voltage driving capability of the memory cell 300 becomes weak after the temperature rises, by prolonging the charge sharing time, it is ensured that the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value at the end of the charge sharing period T1.

As shown in FIG. 8C , when the temperature data of the storage unit 300 continues to rise and is located in the third temperature range, the selection unit 114 selects the sixth control signal EN6 output by the third adjustment sub-unit 113 to output, compared with the fifth control signal EN5 , the rising edge time of the sixth control signal EN6 is later, the time when the second control signal EN2 is at a high level is further extended, the time when the third control signal EN3 is at a low level is further extended, the third N-type transistor N3 and the third The time when the P-type transistor P3 is in the off state is further extended, the time when the amplifying module 200 is disconnected from the first power supply terminal and the second power supply terminal is further extended, and the storage capacitor Cs in the storage unit 300 shares the charge with the bit line BL time is further extended. Since the voltage driving capability of the memory cell 300 becomes weaker after the temperature rises, by further prolonging the charge sharing time, it is ensured that the charge sharing voltage on the bit line BL and the complementary bit line BLB reaches the maximum value at the end of the charge sharing period T1.

In the sensing amplification stage T2, the gate of the third P-type transistor P3 receives the second control signal EN2 and changes to a low level, and the gate of the third N-type transistor N3 receives the third control signal EN3 and changes to a high level, and the amplification The module 200 is connected to both the first power supply terminal and the second power supply terminal, and the amplifying module 200 further drives the voltage on the bit line BL and the complementary bit line BLB to form a larger voltage difference between the bit line BL and the complementary bit line BLB.

In the above technical solution, the control unit 120 performs delay processing on the first control signal EN1 according to the temperature data of the storage unit 300 to adjust the falling edge timing of the second control signal EN2, so as to realize the adjustment of the charge sharing stage according to the temperature data of the storage unit 300 At the end of T1, the voltage driving capability of the memory cell 300 is changed due to the increase of the temperature data, so as to ensure that the charge sharing voltage VCS on the bit line BL and the complementary bit line BLB is the maximum value at the end of the charge sharing phase T1, Accurately amplify the voltages on the bit line BL and the complementary bit line BLB in the sense amplification stage T2.

An embodiment of the present disclosure provides a semiconductor memory including the sense amplifier involved in the above embodiments.

Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common general knowledge or techniques in the technical field not disclosed by this disclosure . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (20)

1. A sense amplifier, comprising:

the control module is provided with an input end and a first output end and is used for acquiring temperature data of the storage unit, delaying the first control signal received by the input end of the control module according to the temperature data of the storage unit to generate a second control signal, adjusting the time of the amplification module for connecting the first power supply end, and adjusting the charge sharing time of the bit line or the complementary bit line and the storage unit;

and the first control terminal of the amplifying module is connected with the first output terminal of the control module, and the amplifying module is used for connecting the first power supply terminal under the control of the second control signal in a sensing amplifying stage, and amplifying the voltage difference between the bit line and the complementary bit line under the drive of the first power supply terminal.

2. The sense amplifier of claim 1,

the control module is also provided with a second output end and is also used for carrying out non-operation on the second control signal to generate a third control signal;

the amplifying module is also provided with a second control end; a second control end of the first control module is connected with a second output end of the control module and is used for being communicated with a second power supply end under the control of the third control signal;

wherein the voltage of the first power supply terminal is greater than the voltage of the second power supply terminal.

3. The sense amplifier according to claim 1 or 2, wherein the control module comprises:

the control unit is provided with an output end and is used for generating a delay adjusting signal according to the temperature data of the storage unit;

and the adjusting unit is provided with an input end, an output end and a control end, the control end of the adjusting unit is connected with the output end of the control unit, the input end of the adjusting unit receives the first control signal, carries out delay processing on the first control signal according to the delay adjusting signal and outputs the second control signal.

4. The sense amplifier of claim 3, wherein the control module further comprises;

and the input end of the first inverter is connected with the output end of the adjusting unit and is used for carrying out non-operation on the second control signal and outputting a third control signal.

5. The sense amplifier of claim 3, wherein the control unit includes three outputs, the delay adjustment signal includes three strobe signals, and the adjustment unit includes:

the output end of the first adjusting subunit is connected with the first input end of the selection unit, and the first adjusting subunit is used for delaying the first control signal and outputting a fourth control signal;

the output end of the second adjusting subunit is connected with the second input end of the selecting unit and is used for performing delay processing on the first control signal and outputting a fifth control signal;

the output end of the third adjusting subunit is connected with the third input end of the selection unit, and the third adjusting subunit is used for performing delay processing on the first control signal and outputting a sixth control signal; wherein the delay amount of the fourth control signal, the delay amount of the fifth control signal and the delay amount of the sixth control signal are all different;

the selection unit is also provided with an output end and three control ends, and each control end is connected with the corresponding output end of the control unit and receives the corresponding gating signal; for selecting one output from among the fourth control signal, the fifth control signal, and the sixth control signal under control of the three strobe signals; the output signal of the selection unit is used for controlling the first control end of the amplification module.

6. The sense amplifier of claim 5, wherein the adjustment unit further comprises:

the input end of the second phase inverter is connected with the output end of the selection unit and used for outputting the output signal of the selection unit after carrying out non-operation on the output signal; the output signal of the second inverter is used for controlling the first control end of the amplifying module.

7. The sense amplifier of claim 5, wherein the control unit is configured to:

when the temperature data is in a first temperature range, the output first gating signal is an effective value, and the output second gating signal and the output third gating signal are invalid values; controlling the selection unit to select the fourth control signal to be output;

when the temperature data is in a second temperature range, the output second gating signal is an effective value, and the output first gating signal and the output third gating signal are invalid values; controlling the selection unit to select the fifth control signal to be output;

when the temperature data is in a third temperature range, the output third gating signal is an effective value, and the output first gating signal and the output second gating signal are invalid values; controlling the selection unit to select the sixth control signal to be output;

wherein the upper limit value of the first temperature range is less than or equal to the lower limit value of the second temperature range, and the upper limit value of the second temperature range is less than or equal to the lower limit value of the third temperature range; the delay amount of the fourth control signal is smaller than the delay amount of the fifth control signal, and the delay amount of the fifth control signal is smaller than the delay amount of the sixth control signal.

8. The sense amplifier of claim 5, wherein the first regulation subunit comprises:

a first pulse generator, the input end of which receives the first control signal, for generating a first pulse signal according to the first control signal;

a first delay circuit, an input end of which receives the first control signal, and outputs a first delay signal after performing delay processing on the first control signal;

the input end of the second pulse generator is connected with the output end of the first delay circuit and used for generating a second pulse signal according to the first delay signal;

a first latch, a first input of which is connected to the first pulse generator, a second input of which is connected to the second pulse generator, for generating the fourth control signal in accordance with the first pulse signal and the second pulse signal.

9. The sense amplifier of claim 5, wherein the second regulation subunit comprises:

a third pulse generator, the input end of which receives the first control signal, for generating a third pulse signal according to the first control signal;

the input end of the second delay circuit receives the first control signal, and outputs a second delay signal after the first control signal is subjected to delay processing, and the delay amount of the second delay circuit is greater than that of the first delay circuit;

a fourth pulse generator, an input end of which is connected with the output end of the second delay circuit, for generating a fourth pulse signal according to the second delay signal;

a second latch, a first input of which is connected to the third pulse generator and a second input of which is connected to the fourth pulse generator, for generating the fifth control signal according to the third pulse signal and the fourth pulse signal.

10. The sense amplifier of claim 5, wherein the third regulation subunit comprises:

a fifth pulse generator, an input end of which receives the first control signal, for generating a fifth pulse signal according to the first control signal;

a third delay circuit, an input end of which receives the first control signal and outputs a third delay signal after delaying the first control signal, and a delay amount of the third delay circuit is greater than that of the second delay circuit;

a sixth pulse generator, an input end of which is connected to the output end of the third delay circuit, for generating a sixth pulse signal according to the third delay signal;

a third latch, a first input of which is connected to the fifth pulse generator, a second input of which is connected to the sixth pulse generator, for generating the sixth control signal according to the fifth pulse signal and the sixth pulse signal.

11. The sense amplifier of claim 8 wherein the first, second, third, fourth, fifth and sixth pulse generators are identical in structure.

12. The sense amplifier of claim 11, wherein the first pulse generator comprises:

the output end of the third inverter of the previous stage is connected with the input end of the third inverter of the next stage; the input end of the third inverter of the first stage receives the first control signal, and the output end of the third inverter of the last stage is connected with the second input end of the first NAND gate;

the first nand gate has a first input end receiving the first control signal and an output end outputting the first pulse signal.

13. The sense amplifier of claim 8, wherein the first, second, and third latches are identical in structure, the first latch comprising:

a second NAND gate; the first input end of the first latch is used as the first input end of the first latch, the second input end of the first latch is connected with the output end of the third NAND gate, and the output end of the first latch is connected with the first input end of the third NAND gate;

the third NAND gate; the second input terminal is used as the second input terminal of the first latch, and the output terminal is used as the output terminal of the first latch.

14. The sense amplifier of claim 8, wherein the first delay circuit comprises:

a first buffer, an input terminal of which receives the first control signal;

and the input end of the second buffer is connected with the output end of the first buffer, and the output end of the second buffer outputs the first delay signal.

15. The sense amplifier of claim 9, wherein the second delay circuit comprises:

a third buffer, an input end of which receives the first control signal;

the input end of the fourth buffer is connected with the output end of the third buffer;

a fifth buffer, an input end of which is connected with an output end of the fourth buffer;

and the input end of the sixth buffer is connected with the output end of the fifth buffer, and the output end of the sixth buffer outputs the second delay signal.

16. The sense amplifier of claim 10, wherein the third delay circuit comprises:

a seventh buffer, an input of which receives the first control signal;

an eighth buffer, an input end of which is connected with an output end of the seventh buffer;

a ninth buffer, an input end of which is connected with an output end of the eighth buffer;

a tenth buffer, an input end of which is connected with an output end of the ninth buffer;

an eleventh buffer, an input end of which is connected with an output end of the tenth buffer;

and an input end of the twelfth buffer is connected with an output end of the eleventh buffer, and an output end of the twelfth buffer outputs the third delay signal.

17. The sense amplifier of claim 3, wherein the control unit comprises:

the temperature sensor is used for detecting the temperature data of the storage unit and generating temperature coding data according to the temperature data;

and the input end of the temperature decoder is connected with the output end of the temperature sensor, and the temperature decoder is used for generating the delay adjusting signal according to the temperature encoding data.

18. The sense amplifier of claim 1, wherein the amplification module comprises:

a third P-type transistor, a source of which is connected to the first power terminal, and a gate of which is used as a first control terminal of the amplifying module;

the source electrode of the first P-type transistor is connected with the drain electrode of the third P-type transistor, and the grid electrode of the first P-type transistor is connected with the drain electrode of the second P-type transistor;

the source electrode of the second P-type transistor is connected with the source electrode of the first P-type transistor, and the grid electrode of the second P-type transistor is connected with the drain electrode of the first P-type transistor;

a first N-type transistor having a drain connected to the drain of the first P-type transistor, a gate connected to the second N-type transistor, a gate connected to the complementary bit line, and a source indirectly coupled to a second power supply terminal;

and the drain electrode of the second N-type transistor is connected with the drain electrode of the second P-type transistor, the grid electrode of the second N-type transistor is connected with the first N-type transistor, the grid electrode of the second N-type transistor is connected with a bit line, and the source electrode of the second N-type transistor is connected with the source electrode of the first N-type transistor.

19. The sense amplifier of claim 18, wherein the amplifying module comprises:

and the source electrode of the third N-type transistor is connected with the second power supply end, the grid electrode of the third N-type transistor is used as the second control end of the amplification module, and the drain electrode of the third N-type transistor is connected with the source electrode of the first N-type transistor.

20. A semiconductor memory characterized by comprising the sense amplifier according to any one of claims 1 to 19.

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