CN115134541A - High dynamic CMOS image sensor with high and low gains and logarithmic response, time sequence control method and reading mode - Google Patents

Abstract

A high dynamic CMOS image sensor with high and low gain and logarithmic response, a time sequence control method and a reading mode belong to the field of semiconductor photoelectric direction image sensors. The invention utilizes the principle that charge compensation elements respectively work in a cut-off region and a subthreshold region under different light intensities: the charge compensation element is positioned in a cut-off region under weak light and strong light, and no conducting current exists, so that the pixel structure has the same technical function as a high-dynamic pixel with a high-low gain structure, and has strong detection capability under the weak light; under super-strong light or long integration time, the charge compensation element works in a sub-threshold region, and the charge compensation of the over-flash light is realized by utilizing the characteristic that the current and the voltage of the transistor in the sub-threshold region are in logarithmic relation, so that the image can be formed under super-high light intensity. The invention can obtain a plurality of images with the same integral time under one exposure, and the plurality of images can be synthesized into an image with an ultrahigh dynamic range corresponding to weak light, strong light and ultrahigh light.

Description

A high dynamic CMOS image sensor with both high and low gain and logarithmic response and timing control method and reading method

technical field

The invention belongs to the field of semiconductor photoelectric directional image sensors, in particular to a high dynamic CMOS image sensor with both high and low gain and logarithmic response, as well as a timing control method and a reading method corresponding thereto.

Background technique

The dynamic range is an important indicator for evaluating CMOS image sensors, which indicates the range of the maximum light intensity signal and the minimum light intensity signal that the CMOS image sensor can detect simultaneously in the same frame of image. The larger the dynamic range, the grayscale details of the obtained image. The higher the level. With the continuous development of integrated circuit technology, CMOS image sensors have been widely used in the field of image sensing. The dynamic range of ordinary CMOS image sensors can only reach 60-70dB. However, in the fields of automotive imaging, security monitoring, military, and automated optical detection, the range of ambient light can reach more than 100dB, and ordinary CMOS image sensors can no longer meet the actual scene. Imaging requirements.

The widely used high dynamic CMOS image sensor adopts the pixel structure with high and low gain, as shown in Figure 1. The pixel structure is composed of a clamp photodiode 1, a charge transfer control transistor 2, a reset transistor 3, a high dynamic range transistor 4, a source follower 5, and a row select transistor 6. 2-6 are standard NMOS transistors. The working sequence is shown in Figure 2. First, the reset operation is performed, and transistors 2, 3, and 4 are all turned on once; then the pixel enters the integration stage, and the FD point is reset again before the integration ends, and the low gain reset value RST_L is read respectively. and the high gain reset value RST_H; next, the integration ends, the charge transfer control transistor 2 is turned on, and the photogenerated charge generated by the clamp photodiode 1 is transferred to the FD point to obtain the high gain signal voltage SIG_H; then the charge transfer control transistor 2 and The high dynamic range transistor 4 is turned on again at the same time, and the low gain signal value SIG_L is read at this time. During the conduction period of the high dynamic range transistor 4, the FD point is connected to the FDL point, which is equivalent to increasing the capacitance of the FD point, which can accommodate more photo-generated charges from the clamping photodiode 1, thereby improving the dynamic range of the pixel. The method of obtaining high and low gains through two charge transfers can expand the dynamic range of the pixel by 20 to 30 dB, so that the total dynamic range is close to or reaches 90 dB.

High dynamic pixels with high and low gain structure, although the dynamic range is improved by two charge transfer, but due to the limitation of pixel area and filling ratio, the well capacity of the clamped photodiode is limited, when the light intensity is too strong, or when the integration time is long , the clamped photodiode reaches full well during the integration time and will not be able to hold more charges, thus limiting the dynamic range of the image sensor.

In addition, there are also ways to extend the dynamic range, such as multi-level lateral overflow gates, dual photodiodes, and diode-connected logarithmic modes. The above methods require special processes to manufacture large capacitors, complex circuit structures, and large pixel areas, and are not suitable for large Disadvantages of area array image sensor, large dark current under low light, and poor signal-to-noise ratio.

SUMMARY OF THE INVENTION

The invention relates to a high dynamic CMOS image sensor with high and low gain and logarithmic response at the same time, and a timing control method and reading method corresponding to it. The purpose of the present invention is to perform an additional ion implantation on the reset transistor and the high dynamic range transistor on the basis of the traditional high and low gain based high dynamic pixel structure to adjust the threshold voltage of the two NMOS transistors to be lower than the normal value. Together they constitute the charge compensation element proposed by the present invention. The charge compensation element works in the sub-threshold region under super strong illumination or super long integration time, and can inject charges into the FD point to compensate for the photo-generated charge overflowing from the clamp photodiode to the FD point to avoid the clamp photodiode reaching full capacity. signal saturation caused by the trap, thus achieving extended dynamic range. The invention utilizes the principle that the charge compensation element works in the cut-off region and the sub-threshold region respectively under different light intensities: under a certain integration time (such as 10ms), under weak light (0.0001lux to 0.1lux) and strong light (0.1lux) ～10lux), the charge compensation element is in the cut-off region, and there is no on-current. At this time, the pixel structure of the present invention has the same function as the high-dynamic pixel technology with high and low gain structure, so it has strong detection ability under weak light; Under strong light (over 10 lux), the charge compensation element works in the sub-threshold region, and the photo-generated charge can be compensated by using the characteristic that the transistor current and voltage in the sub-threshold region have a logarithmic relationship, so imaging can be performed under ultra-high light intensity. The present invention can obtain multiple images with the same integration time under one exposure, corresponding to weak light, strong light and super strong light, and the multiple images can be synthesized into an image with ultra-high dynamic range. The invention also utilizes the principle that the charge compensation elements work in the cut-off region and the sub-threshold region respectively under different integration times: when the pixel structure is under a certain light intensity (such as 10 lux), when the integration time is very short (such as 100 μs), the charge compensation The element is in the cut-off region and has no on-current. At this time, the pixel structure of the present invention has the same function as the aforementioned technology, so it still has a strong imaging ability when the integration time is short under a certain light intensity; when the integration time is very long (such as 10ms), the clamping photodiode reaches full well, the charge compensation element works in the sub-threshold region, and the compensation of the photo-generated charge is realized by using the characteristic that the current and voltage of the transistor in the sub-threshold region are logarithmic. At this time, the output signal is proportional to the logarithm of the light intensity and has nothing to do with the integration time.

Technical scheme of the present invention:

A high dynamic CMOS image sensor with both high and low gain and logarithmic response, the structure is shown in Figure 3. The pixel structure includes a clamped photodiode 1 , a charge transfer control transistor 2 , a novel reset transistor 7 , a novel high dynamic range transistor 8 , a source follower 5 and a row select transistor 6 . The new reset transistor 7 and the new high dynamic range transistor 8 together constitute the charge compensation element 9 of the present invention.

The clamping photodiode 1 is used as a photodetecting element, which can convert the received optical signal into an electrical signal and accumulate photo-generated charges. The P terminal of the clamping photodiode 1 is connected to GND, and the N terminal is connected to the source of the charge transfer control transistor 2 . The charge transfer control transistor 2 is used to transfer the photogenerated charge accumulated in the clamp photodiode 1 to the FD point. The control signal TX of the gate of the charge transfer control transistor 2 comes from the row control module in the image sensor system, and the drain is connected to FD point. The charge compensation element 9 includes a new type of reset transistor 7 and a new type of high dynamic range transistor 8, wherein the drain of the new type of reset transistor 7 is connected to the Vpix potential, and the source is connected to the drain of the new type of high dynamic range transistor 8. The source is connected to the FD point. The gate control signals RST and HDR of the charge compensation element 9 composed of the new reset transistor 7 and the new high dynamic range transistor 8 come from the row control module. Operating in the subthreshold region for long integration times increases the dynamic range of the image sensor. The source follower 5 and the row selection transistor 6 are used to output the pixel signal to the subsequent readout circuit. The gate of the source follower 5 is connected to the FD point, the drain is connected to VDD, and the source is connected to the drain of the row selection transistor 6. extremely connected. The control signal SEL of the gate terminal of the row selection transistor 6 comes from the row control module, and the source is connected to the column bus for outputting the signal value of the pixel to the subsequent readout circuit of the image sensor system.

The charge transfer control transistor 2 , the source follower 5 and the row selection transistor 6 are all manufactured by standard NMOS transistor technology.

The new reset transistor 7 and the new high dynamic range transistor 8 are based on an additional ion implantation based on the standard process to adjust the threshold voltage of the transistor, so that the threshold voltage is lower than the normal value, so the two together constitute The described charge compensation element 9 is obtained. The device works in the sub-threshold region under super strong light or when integrating for a long time. It can inject the photo-generated charge from the charge compensation clamp photodiode 1 overflowing to the FD point to the FD point, so as to avoid the signal caused by the clamp photodiode reaching the full well. saturation. Using the characteristic that the transistor current and voltage in the sub-threshold region have a logarithmic relationship, the logarithmic response is obtained based on the linear response of weak light and strong light, which greatly expands the dynamic range of the image sensor.

A timing control method and reading method of a high dynamic CMOS image sensor with both high and low gain and logarithmic response are shown in Figure 4, and the specific steps are as follows:

Step 1, reset operation.

First, the pixel enters the reset state, the charge transfer control transistor 2 and the charge compensation element 9 are turned on at the same time, the charge in the clamping photodiode 1 is emptied, and the FD point voltage is reset to Vpix.

Step 2, integral operation.

After the reset operation, the gate control signal voltages of the charge transfer control transistor 2 and the charge compensation element 9 drop to VTXL and VRL respectively, the pixel enters the integration stage, and the clamp photodiode 1 begins to accumulate photo-generated charges.

1) When the exposure time is not long enough under weak light or strong light, the photo-generated charge generated in the clamp photodiode 1 is less than or equal to the full well capacity of the clamp photodiode 1, and the photo-generated charge is all accumulated in the clamp photodiode 1. The excess photogenerated charges flow to the FD point through the charge transfer control transistor 2, so the voltage at the FD point will not change during the integration time. The gate-source voltage V _GS of the charge compensation element 9 is much smaller than the threshold voltage, so the charge compensation element 9 works in the cut-off region, and no current flows to the FD point.

2) With the increase of the light intensity or the extension of the integration time, the photo-generated charges accumulated in the clamp photodiode 1 during the integration process will exceed its full well capacity, and the excess photo-generated charges will flow to the FD point through the charge transfer control transistor 2. , which constitutes the overflow current I _OV , which is equal to the photo-generated current I _ph generated by the clamp photodiode 1,

I _OV =I _ph =ηRP _in

Among them, η, R, and P _in are the quantum efficiency, responsivity and incident light power of the clamped photodiode 1, respectively; the current causes the voltage at the FD point to drop, and the voltage change value ΔV _FD is proportional to the integration time t,

ΔV _FD =ηRP _in ·t

Since the light intensity is not large enough at this time, the photogenerated charge flowing to the FD point is limited within a certain integration time, and the voltage at the FD point will not drop a lot. At this time, it is reflected that the voltage change at the FD point is proportional to the light intensity. The voltage value of the FD is read out through the source follower 5, the row selection transistor 6 and the subsequent circuits as the linear signal value LOG_S1 in logarithmic mode.

3) When the light intensity is too strong or the integration time is long, the photo-generated charge accumulated in the clamp photodiode 1 far exceeds its full well capacity, and the excess photo-generated charge will flow to the FD point through the charge transfer control transistor 2. And accumulated at the FD point, a continuous photo-generated overflow current I _OV is generated, which causes the voltage at the FD point to continuously drop, so that the V _GS of the charge compensation element 9 continues to increase. Since the internal transistor of the charge compensation element 9 has undergone an additional ion implantation on the basis of the standard process, its threshold voltage is lower than the normal value, and the _VGS value is close to the threshold voltage at this time, so that the charge compensation element 9 enters from the cut-off region to the Sub-threshold operating region, resulting in a current flowing from Vpix to the FD point. This current can cancel the overflow current I _OV flowing from the clamp photodiode 1 to the FD point, so it is called the charge compensation current I _C . If the light intensity is strong enough or the integration time is long enough, the photo-generated overflow current I _OV and the charge compensation current _IC reach a balance state, then the voltage at the FD point will no longer change with the integration time. At this time, the charge compensation element 9 works in the sub-threshold region, and the charge compensation current I _C is as follows:

where _IS is a constant having a current dimension, V _RST is the gate voltage of the charge compensation element 9, V _FD is the voltage at point FD, V _TH is the threshold voltage of the charge compensation element 9, m is the subthreshold slope factor, V _T is the thermal voltage.

After balancing, the charge compensation current is equal to the photogenerated overflow current,

I _OV = I _C = ηRP _in

_{The VFD} expression can be obtained:

According to the above formula, the change of the voltage value at the FD point at this time is proportional to the logarithm of the incident light intensity. This voltage can be read out by the source follower 5, the row select transistor 6 and subsequent circuits as the signal value LOG_S2 in logarithmic mode.

Before the integration ends, perform a reset operation on the FD point again, the new reset transistor 7 and the new high dynamic range transistor 8 inside the charge compensation element 9 are turned on respectively, and the gate control signal HDR of the new high dynamic range transistor 8 is high level. When VHDRH, the FD point voltage is used as the low gain reset value RST_L, which can be read out through the source follower 5, row select transistor 6 and subsequent circuits; then the HDR signal voltage drops to VRL, and the FD point voltage is used as the high gain reset value RST_H , can be read out through source follower 5, row select transistor 6 and subsequent circuits. At this point, the integration phase of the pixel circuit ends.

Step 3, the first charge transfer process.

First, the charge transfer control transistor 2 is turned on, and under the action of the potential difference, the photogenerated charges accumulated in the clamp photodiode 1 are transferred to the FD point through the charge transfer control transistor 2. At this time, the high-gain signal value SIG_H of the FD point is read, and the voltage can be read out through the source follower 5, the row selection transistor 6 and subsequent circuits.

Step 4, the second charge transfer process.

After the first charge transfer, the new high dynamic range transistor 8 is turned on, and the FD and FDL points are short-circuited. During this period, the charge transfer control transistor 2 is turned on again, and the remaining photo-generated charges in the clamp photodiode 1 continue to be transferred through the charge transfer control transistor 2. to FD and FDL points. The read voltage value of the FD point is the signal value SIG_L with a low gain, and the voltage can be read out through the source follower 5 , the row select transistor 6 and subsequent circuits.

For the high dynamic CMOS image sensor with both high and low gain and logarithmic response according to the present invention, the relationship between the input light intensity of the pixel and the output signal is shown in FIG. 5 . Under a certain integration time, according to the intensity of incident light, high dynamic pixels can be divided into four working states: state 1 (HG) and state 2 (LG) are linear regions, the difference between them is that state 1 corresponds to the highest input light intensity At this time, since the new high dynamic range transistor 8 of the pixel is turned off, the capacitance value of the FD point is small, and the CVG (charge-voltage conversion gain) of the pixel is large, so that a very high signal-to-noise ratio can be obtained in low light. State 2 corresponds to strong light, when the new high dynamic range transistor 8 is turned on, the CVG of the pixel is smaller, and the full well capacity is increased. State 3 is the transition between state 2 and state 4, and the output signal is still proportional to the light intensity at this time. Under super strong light, the pixel works in state 4, and the charge compensation element 9 works in the sub-threshold region. The current flowing from the clamping photodiode to the FD and the compensation current formed by the charge compensation element 9 reach a balance, so that the output signal and the input light intensity match. is proportional to the number, thereby expanding the dynamic range. Under a certain integration time (such as 10ms), the corresponding light intensity range of state 1 is in the order of 0.0001 lux to 0.1 lux, the light intensity range of state 2 is in the order of 0.1 lux to 10 lux, and the light intensity range of state 3 is still Maintaining the order of 10 lux, the light intensity of state 4 ranges from the order of 10 lux to the order of 10,000 lux or more. It can be seen that, by using the charge compensation element 9 and the control timing and signal reading method of the present invention, 4 pictures with the same exposure time can be outputted under one frame of imaging, respectively for weak light, strong light and super strong light. . Compared with the traditional method of using high and low gain to improve the dynamic range, the present invention adds states 3 and 4 in addition to states 1 and 2 corresponding to weak light and strong light. 1 order of magnitude, and state 4 corresponds to super-intensive light. At this time, since the charge compensation element 9 of the present invention works at a sub-threshold value, the pixel output signal is proportional to the logarithm of the light intensity, which greatly improves the dynamic range of the image sensor. , which can increase the dynamic range by at least 60dB on the basis of the traditional use of high and low gain to improve the dynamic range.

Beneficial effects of the present invention:

(1) Compared with the traditional high-low gain based high-dynamic image sensor pixel structure, the high-dynamic CMOS image sensor with high and low gain and logarithmic response described in the present invention does not change the pixel circuit structure, and increases through the charge compensation element. An additional ion implantation reduces the threshold voltage of the reset transistor and the high dynamic range transistor that constitute the charge compensation element, so that the charge compensation element operates in the sub-threshold region when the light intensity is too strong or the integration time is too long. At this time, the compensation current generated by the charge compensation element has an exponential relationship with the gate-source voltage, which will compensate the photo-generated overflow current flowing to the FD point through the charge transfer control transistor. With the increase of the light intensity or the increase of the integration time, the two currents will reach a balance. At this time, the voltage at the FD point will no longer change with the integration time, and its voltage value is proportional to the logarithm of the incident light intensity, thus greatly expanding the the dynamic range of the image sensor.

(2) Compared with the way of improving the dynamic range of the existing image sensor, the pixel structure of the high dynamic CMOS image sensor with both high and low gain and logarithmic response described in the present invention has a simple circuit structure. The compensation element works in the sub-threshold region under super-intensive light or long-time exposure, and realizes the logarithmic response of the input light intensity and the output signal. Multiple images in logarithmic mode, high gain, low gain, etc. can be simultaneously acquired for objects with different light intensities under one frame. These images have the same exposure time, realizing the technology based on dual photodiodes combined with different integration times. LED flickering effect that cannot be detected by the high dynamic image sensor.

(3) Compared with the traditional image sensor pixel structure that realizes high dynamic range, the high dynamic CMOS image sensor pixel structure with both high and low gain and logarithmic response according to the present invention has a linear response in weak light and strong light , the signal-to-noise ratio is the same as that of the traditional 4T pixel structure based on the clamp photodiode, and it has super weak light detection ability; at the same time, it has a logarithmic response under super strong light, and the output signal does not saturate with the increase of light intensity, which can change the dynamic The range is extended by 3 to 4 orders of magnitude.

(4) Compared with the traditional image sensor pixel structure that realizes high dynamic range, the high dynamic CMOS image sensor pixel structure with both high and low gain and logarithmic response according to the present invention can be divided into 4 tasks according to the incident light intensity interval The states are linear high gain, linear low gain, log linear and log response, respectively corresponding to weak light, strong light, transition between strong light and super strong light, and super strong light. After signal amplification and analog-to-digital conversion by subsequent readout circuits, the digital output signals of the four states contain sufficient information. The output results of these four states are fused to obtain a high dynamic range image that retains all the details of the image from low light to super bright light.

Description of drawings

Fig. 1 is the circuit structure of high and low gain high dynamic pixel;

Figure 2 is the working timing of high and low gain and high dynamic pixels;

Fig. 3 is a high dynamic pixel circuit structure with both high and low gain and logarithmic response;

Figure 4 is a high dynamic pixel working sequence and reading method with high and low gain and logarithmic response at the same time;

Fig. 5 is a high dynamic pixel input light intensity and output signal relationship curve with both high and low gain and logarithmic response;

Fig. 6 is working sequence and reading mode of embodiment 1;

Fig. 7 is working sequence and reading mode of embodiment 2;

8 is a high dynamic pixel circuit structure having both a single-gain linear response and a logarithmic response in Embodiment 3;

Fig. 9 is working sequence and reading mode of embodiment 3;

In the figure: 1 clamp photodiode, 2 charge transfer control transistors, 3 reset transistors, 4 high dynamic range transistors, 5 source followers, 6 row select transistors, 7 new reset transistors, 8 new high dynamic range transistors, 9 charge Compensation element.

Detailed ways

Example 1

The pixel circuit structure of the high-dynamic CMOS image sensor with both high and low gain and logarithmic response described in Embodiment 1 is shown in FIG. 3 . The pixel structure consists of a clamp photodiode 1, a charge transfer control transistor 2, a new reset transistor 7, a new high dynamic range transistor 8, a source follower 5, and a row select transistor 6. The charge transfer control transistor 2 in the pixel, the source The follower 5 and the row selection transistor 6 are all manufactured by standard NMOS transistor process. The new reset transistor 7 and the new high dynamic range transistor 8 together constitute the charge compensation element 9 of the present invention, which is an additional process based on the standard process. The ion implantation is used to adjust the threshold voltage of the transistor so that its threshold voltage is -0.3V. The charge compensation element 9 works in the sub-threshold region under super strong light or when integrating for a long time, and injects charge into the FD point to compensate for the photo-generated charge overflowing from the clamp photodiode 1 well to the FD point, so as to avoid reaching the FD point due to the clamp photodiode. Signal saturation due to full well. Among them, the clamping photodiode 1 is used as a photodetection element, which can convert the received optical signal into an electrical signal. The P terminal is connected to 0V, and the N terminal is connected to the source of the charge transfer control transistor 2 . The control signal TX of the gate of the charge transfer control transistor 2 comes from the row control module in the image sensor system, and the drain is connected to the FD point. The charge compensation element 9 includes a new reset transistor 7 and a new high dynamic range transistor 8. The drain of the new reset transistor 7 is connected to the Vpix potential of 3.3V, the gate control signal RST comes from the row control module, and the source is connected to the new high dynamic range. The drain of the transistor 8, the gate control signal HDR of the new high dynamic range transistor 8 comes from the row control module, and the source is connected to the FD point. The gate of the source follower 5 is connected to the FD point, the drain is connected to 3.3V, and the source is connected to the drain of the row selection transistor 6 . The control signal SEL of the gate terminal of the row selection transistor 6 comes from the row control module, and the source is connected to the column bus for outputting the signal value of the pixel to the subsequent readout circuit of the image sensor system.

The specific timing control method and reading method of the high dynamic CMOS image sensor with high and low gain and logarithmic response according to the present invention are shown in FIG. 4 , and the specific steps are as follows:

Step 1, reset operation.

First, the pixel enters the reset state, the charge transfer control transistor 2 and the charge compensation element 9 are turned on at the same time, the charge in the clamping photodiode 1 is emptied, and the voltage at the FD point is reset to 3.3V.

Step 2, integral operation.

After the reset operation, the gate control signal voltages of the charge transfer control transistor 2 and the charge compensation element 9 both drop to 0V, the pixel enters the integration stage, and the clamp photodiode 1 begins to accumulate photo-generated charges.

1) When the exposure time is not long enough under weak light or strong light, the photo-generated charge generated in the clamp photodiode 1 is less than or equal to the full well capacity of the clamp photodiode 1, and all the photo-generated charges are accumulated in the clamp photodiode 1, which will not The excess photogenerated charges flow to the FD point through the charge transfer control transistor 2, so the voltage at the FD point will not change during the integration time. The gate-source voltage V _GS of the charge compensation element 9 is much smaller than the threshold voltage -0.3V, so the charge compensation element 9 works in the cut-off region, and no current flows to the FD point.

2) With the increase of the light intensity or the extension of the integration time, the photo-generated charges accumulated in the clamping photodiode 1 during the integration process will have its own full well capacity, and the excess photo-generated charges will flow to the FD point through the charge transfer control transistor 2, An overflow current I _OV is formed, which is equal to the photo-generated current I _ph generated by the clamping photodiode 1 , and this current causes the voltage at the FD point to drop, and the voltage change value is proportional to the integration time.

Since the light intensity is not large enough at this time, the photogenerated charge flowing to the FD point is limited within a certain integration time, and the voltage at the FD point will not drop a lot. At this time, it is reflected that the voltage at the FD point is proportional to the light intensity. Before the integration ends, read the voltage value of FD once as the linear signal value LOG_S1 in logarithmic mode.

3) When the light intensity is too strong or the integration time is long, the photo-generated charge accumulated in the clamp photodiode 1 far exceeds its full well capacity, and the excess photo-generated charge will flow to the FD point through the charge transfer control transistor 2. And accumulated at the FD point, a continuous photo-generated overflow current I _OV is generated, which causes the voltage at the FD point to continue to drop, so that the V _GS of the charge compensation element continues to increase. Since the threshold voltage of the two transistors inside the charge compensation element 9 is adjusted to -0.3V, the _VGS value is close to the threshold voltage at this time, so that the two transistors enter the sub-threshold working region from the cut-off region, resulting in a current flowing from Vpix FD point. This current can cancel the photo-overflow current I _OV flowing from the clamp photodiode 1 to the FD point, so it is called the charge compensation current I _C . If the light intensity is strong enough or the integration time is long enough, the photo-generated overflow current I _OV and the charge compensation current _IC reach a balance state, then the voltage at the FD point will no longer change with the integration time. At this time, the charge compensation element 9 works in the sub-threshold region. After balancing, the charge compensation current is equal to the photo-generated overflow current. It can be obtained that the voltage value at the FD point is proportional to the logarithm of the incident light intensity. This voltage can be read out by the source follower 5, the row select transistor 6 and subsequent circuits as the signal value LOG_S2 in logarithmic mode.

Before the integration ends, perform a reset operation on the FD point again, and the internal transistors 7 and 8 of the charge compensation element are turned on respectively. When the gate control signal HDR of the new high dynamic range transistor 8 is at a high level of 4V, the image sensor readout circuit. The low gain reset value RST_L is read, then the HDR signal voltage drops to 0V, the readout circuit of the image sensor reads the high gain reset value RST_H, and finally the gate control signal HDR of the new high dynamic range transistor 8 drops to a low level 0V. At this point, the integration phase of the pixel circuit ends.

Step 3, the first charge transfer process.

First, the charge transfer control transistor 2 is turned on, and under the action of the potential difference, the photogenerated charges accumulated in the clamp photodiode 1 are transferred to the FD point through the charge transfer control transistor 2. At this time, the high gain signal value SIG_H of the FD point is read.

Step 4, the second charge transfer process.

After the first charge transfer, the new high dynamic range transistor 8 is turned on, and the FD and FDL points are short-circuited. During this period, the charge transfer control transistor 2 is turned on again, and the remaining photo-generated charges in the clamp photodiode 1 continue to be transferred through the charge transfer control transistor 2. to FD and FDL points. Read the signal value SIG_L with the low gain voltage value at the FD point.

Example 2

The pixel circuit structure of the high dynamic range image sensor described in Embodiment 2 is shown in FIG. 3 . The timing sequence and reading method of the pixel structure of the high dynamic range CMOS image sensor described in Embodiment 2 are shown in FIG. 7 . The working process of Example 2 is basically the same as that of Example 1. The difference is that the gate voltage value of the charge compensation element is not reduced to 0V, but to 1V during the integration process. The purpose is to increase the source voltage of the charge compensation element, that is, the FD point. voltage, making it easier for signal processing and readout by the readout circuitry after the pixel in the image sensor.

Example 3

The aforementioned charge compensation element in the high-dynamic CMOS image sensor pixel with both high and low gain and logarithmic response of the present invention is composed of two transistors. In this embodiment, the new reset transistor in the charge compensation element and the new high dynamic The range transistors are combined into one transistor to form a high dynamic range pixel with both a single-gain linear response and a logarithmic response. The circuit structure is shown in Figure 8.

The working timing and reading method of the pixel circuit structure described in Embodiment 3 are shown in FIG. 9 . The pixel circuit work is still divided into a reset phase, an integration phase and a charge transfer phase. In the reset stage, the charge compensation element 9 and the charge transfer control transistor 2 are turned on at the same time, the charge in the clamp photodiode 1 is emptied and the FD point is reset to 3.3V. Before the integration ends, the readout circuit samples the logarithmic signal LOG_SIG once, and then Perform a reset operation on the FD point, the readout circuit reads the linear reset signal value LIN_RST, and then the charge transfer control transistor 2 is turned on once to transfer the photogenerated charge in the clamp photodiode 1 to the FD point, and the readout circuit reads the linearity. Signal value LIN_SIG.

Claims (4)

1. A high dynamic CMOS image sensor with both high and low gain and logarithmic response is characterized in that the pixel structure comprises a clamping photodiode (1), a charge transfer control transistor (2), a charge compensation element (9), a source follower (5) and a row selection transistor (6);

the clamp photodiode (1) is used as a photoelectric detection element and can convert a received optical signal into an electric signal and accumulate photo-generated charges, the P end of the clamp photodiode (1) is connected with GND, and the N end of the clamp photodiode is connected with the source electrode of the charge transfer control transistor (2); the charge transfer control transistor (2) is used for transferring the photo-generated charge accumulated in the clamping photodiode to an FD point, a control signal TX of a grid electrode of the charge transfer control transistor (2) comes from a row control module in the image sensor system, and a drain electrode of the charge transfer control transistor is connected to the FD point; the charge compensation element (9) comprises a novel reset transistor (7) and a novel high dynamic range transistor (8), wherein the drain electrode of the novel reset transistor (7) is connected with the Vpix potential, the source electrode of the novel reset transistor is connected to the drain electrode of the novel high dynamic range transistor (8), and the source electrode of the novel high dynamic range transistor (8) is connected to the FD point; grid control signals RST and HDR of a charge compensation element 9 formed by the novel reset transistor (7) and the novel high dynamic range transistor (8) come from a row control module, the element works in a cut-off region under weak light and strong light, and works in a subthreshold region under super-strong light or super-long integration time, so that the dynamic range of the image sensor is increased; the source follower (5) and the row selection transistor (6) are used for outputting pixel signals to a subsequent readout circuit, the grid electrode of the source follower (5) is connected with an FD point, the drain electrode is connected to VDD, and the source electrode is connected with the drain electrode of the row selection transistor (6); a control signal SEL of a grid end of the row selection transistor (6) is from a row control module, and a source electrode of the control signal SEL is connected with a column bus and used for outputting a signal value of a pixel to a subsequent reading circuit of the image sensor system;

the charge transfer control transistor (2), the source follower (5) and the row selection transistor (6) are all manufactured by adopting a standard NMOS transistor process;

the novel reset transistor (7) and the novel high dynamic range transistor (8) are subjected to one additional ion implantation on the basis of a standard process to adjust the threshold voltage of the transistors to be lower than a normal value, so that the two transistors jointly form the charge compensation element 9; the element works in a sub-threshold region under super-strong light or long-time integration, photogenerated charges overflowing to an FD point of a charge compensation clamping photodiode (1) can be injected into the FD point, and signal saturation caused by the fact that the clamping photodiode reaches a full well is avoided; the characteristic that the current and the voltage of the transistor in the sub-threshold region are in logarithmic relation is utilized, so that logarithmic response is obtained on the basis of linear response of weak light and strong light, and the dynamic range of the image sensor is greatly expanded.

2. The timing control method and reading method of the high dynamic CMOS image sensor having both high and low gains and logarithmic response according to claim 1, wherein the specific steps are as follows:

step one, resetting operation;

firstly, the pixel enters a reset state, the charge transfer control transistor (2) and the charge compensation element (9) are simultaneously conducted once, the charge in the clamping photodiode (1) is cleared, and the FD point voltage is reset to Vpix;

step two, integral operation;

after the reset operation is finished, the grid control signal voltages of the charge transfer control transistor (2) and the charge compensation element (9) are respectively reduced to VTXL and VRL, the pixel enters an integration stage, and the clamp photodiode (1) starts to accumulate photo-generated charges;

1) when the exposure time under weak light or strong light is not long enough, the photo-generated charge generated in the clamping photodiode (1) is less than or equal to the full-well capacity of the clamping photodiode (1), the photo-generated charge is completely accumulated in the clamping photodiode (1), and no redundant photo-generated charge flows to an FD point through the charge transfer control transistor (2), so that the voltage of the FD point does not change within the integration time; gate-source voltage V of charge compensation element (9) _GS Much smaller than the threshold voltage, so that the charge compensation element (9) operates in the cut-off region, with no current flowing to the FD point;

2) with the increase of light intensity or the extension of integration time, the photo-generated charge accumulated in the clamping photodiode (1) in the integration process can exceed the full-well capacity of the clamping photodiode, and the redundant photo-generated charge can flow to an FD point through the charge transfer control transistor (2) to form an over-current I _OV The current is in parallel with a photo-generated current I generated by the clamped photodiode (1) _ph The number of the first and the second antennas is equal,

I _OV ＝I _ph ＝ηRP _in

wherein eta, R, P _in The quantum efficiency, the responsivity and the incident optical power of the clamping photodiode (1) respectively; the current causes the voltage at FD point to drop by a voltage change value DeltaV _FD In proportion to the integration time t,

ΔV _FD ＝ηRP _in ·t

because the light intensity is not large enough at the moment, the photo-generated charges flowing to the FD point are limited within a certain integration time, the voltage of the FD point cannot be reduced greatly, two transistors in the charge compensation element (9) are both in a closed state, and the working state is not changed; the voltage change of the FD point is directly proportional to the light intensity; the voltage value of FD is read out through a source follower (5), a row selection transistor (6) and a subsequent circuit and is used as a linear signal value LOG _ S1 of a logarithmic mode;

3) when the intensity of the light is too strong,or when the integration time is longer, the photo-generated charge accumulated in the clamping photodiode (1) far exceeds the full-trap capacity of the clamping photodiode, the excessive photo-generated charge flows to an FD point through the charge transfer control transistor (2) and is accumulated at the FD point, and continuous photo-generated over-current I is generated _OV Causing the voltage at the FD point to continuously decrease, so that the V of the charge compensation element (9) _GS Continuously increasing height; since the transistor in the charge compensation element (9) is subjected to an additional ion implantation based on the standard process, the threshold voltage is lower than the normal value, and V is the value _GS A value close to the threshold voltage such that the charge compensation element (9) enters the sub-threshold working region from the cut-off region, resulting in a current flowing from Vpix to the FD point; this current can cancel an excessive current I flowing from the clamp photodiode (1) to the FD point _OV And is therefore referred to as charge compensation current I _C (ii) a If the light intensity is strong enough or the integration time is long enough, the light-generated excessive current I _OV And a charge compensation current I _C When the balance state is reached, the voltage of the FD point does not change along with the integration time any more; in this case, the charge compensation element (9) operates in the subthreshold region, and the charge compensation current I _C The following formula:

wherein, I _S Is a constant, V, having a current dimension _RST Is the gate voltage, V, of the charge compensation element (9) _FD Is the voltage, V, of the FD point _TH Is the threshold voltage of the charge compensation element (9), m is the sub-threshold slope factor, V _T Is a thermal voltage;

after balancing, the charge compensation current is equal to the photo-generated overflow current,

I _OV ＝I _C ＝ηRP _in

can obtain V _FD Expression:

according to the above formula, the voltage value change of the FD point is directly proportional to the logarithm of the incident light intensity; the voltage can be read out through a source follower (5), a row selection transistor (6) and a subsequent circuit and is used as a LOG mode signal value LOG _ S2;

before the integration is finished, resetting operation is carried out on the FD point once again, a novel reset transistor (7) and a novel high dynamic range transistor (8) in the charge compensation element (9) are respectively conducted, when a grid control signal HDR of the novel high dynamic range transistor (8) is a high level VHDRH, the voltage of the FD point is used as a reset value RST _ L of low gain and can be read out through a source follower (5), a row selection transistor (6) and a subsequent circuit; then the voltage of the HDR signal is reduced to VRL, and the voltage of the FD point serves as a reset value RST _ H with high gain and can be read out through a source follower (5), a row selection transistor (6) and a subsequent circuit; ending the integration stage of the pixel circuit;

step three, a first charge transfer process;

firstly, a charge transfer control transistor (2) is conducted, and photo-generated charges accumulated in a clamping photodiode (1) are transferred to an FD point through the charge transfer control transistor (2) under the action of potential difference; reading a high-gain signal value SIG _ H of the FD point, wherein the voltage can be read out through a source follower (5), a row selection transistor (6) and a subsequent circuit;

step four, a second charge transfer process;

after the first charge transfer, the novel high dynamic range transistor (8) is started, the FD and the FDL points are in short circuit, the charge transfer control transistor (2) is conducted again in the period, and the rest photo-generated charges in the clamping photodiode (1) are continuously transferred to the FD and FDL points through the charge transfer control transistor (2); the voltage value at the FD point is read as a signal value SIG _ L with low gain, and the voltage can be read out through a source follower (5), a row selection transistor (6) and a subsequent circuit.

3. The timing control method and reading method according to claim 2, wherein the high dynamic pixel is divided into 4 working states according to the incident light intensity under a certain integration time: the states 1-HG and 2-LG are linear regions, the difference between the states is that the input light intensity corresponding to the state 1 is the weakest, at this time, because the novel high dynamic range transistor (8) of the pixel is closed, the capacitance value of the FD point is very small, and the CVG of the pixel is relatively large, so that a very high signal-to-noise ratio can be obtained under weak light; the state 2 corresponds to strong light, at the moment, the novel high dynamic range transistor (8) is started, the CVG of the pixel is small, and the full-well capacity is increased; state 3 is the transition between state 2 and state 4, where the output signal is still proportional to the light intensity; under the ultra-strong light, the pixel works in a state 4, the charge compensation element works in a subthreshold region, the current flowing to the FD from the clamping photodiode and the compensation current formed by the charge compensation element reach balance, so that the output signal is in direct proportion to the logarithm of the input light intensity, and the dynamic range is expanded; under a certain integration time, the light intensity range corresponding to the state 1 is 0.0001lux magnitude to 0.1lux magnitude, the light intensity range corresponding to the state 2 is 0.1lux magnitude to 10lux magnitude, the light intensity range corresponding to the state 3 still maintains 10lux magnitude, and the light intensity range corresponding to the state 4 is more than 10lux magnitude to 10000lux magnitude; therefore, 4 pictures with the same exposure time can be output under one frame of imaging by adopting the charge compensation element (9) and a control time sequence and signal reading mode, and the 4 pictures are respectively used for weak light, strong light and ultra-strong light.

4. The CMOS image sensor with high dynamic range and high gain simultaneously as claimed in claim 1, wherein the charge compensation device 9 formed by the novel reset transistor (7) and the novel high dynamic range transistor (8) can be replaced by combining the novel reset transistor and the novel high dynamic range transistor in the charge compensation device into one transistor to form a high dynamic range pixel with single gain linear response and logarithmic response simultaneously; the pixel circuit still comprises a reset stage, an integration stage and a charge transfer stage; the charge compensation element (9) and the charge transfer control transistor (2) are simultaneously conducted once in the reset stage, charges in the clamping photodiode (1) are emptied, the FD point is reset to Vpix, a readout circuit samples a logarithmic signal LOG _ SIG once before integration is finished, then the FD point is reset once again, the readout circuit reads a linear reset signal value LIN _ RST, then the charge transfer control transistor (2) is conducted once, photo-generated charges in the clamping photodiode (1) are transferred to the FD point, and the readout circuit reads the linear signal value LIN _ SIG.

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