CN115132701B - Semiconductor structure and method of forming the same - Google Patents
Semiconductor structure and method of forming the same Download PDFInfo
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- CN115132701B CN115132701B CN202110321709.1A CN202110321709A CN115132701B CN 115132701 B CN115132701 B CN 115132701B CN 202110321709 A CN202110321709 A CN 202110321709A CN 115132701 B CN115132701 B CN 115132701B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
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Abstract
一种半导体结构及其形成方法，其方法包括：提供衬底，所述衬底包括基底，和位于所述基底表面的金属层；在所述衬底上形成介质层以及位于所述介质层内的接触孔，所述接触孔暴露出部分所述金属层表面；对所述介质层表面和所述接触孔侧壁表面进行甲基化处理；所述甲基化处理后，对所述金属层表面进行氢气等离子体处理；所述氢气等离子体处理后，在所述接触孔内形成导电插塞，所述甲基化处理使所述羟基悬挂键被甲基键所代替，去除了羟基悬挂键的同时，不会引入氧离子，利于导电插塞材料在金属层表面的选择性生长，可以形成较低缺陷密度的导电插塞材料，从而提高形成的导电插塞的性能，得到较低电阻率的导电插塞。
A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a base and a metal layer located on the surface of the base; forming a dielectric layer and a contact hole located in the dielectric layer on the substrate, the contact hole exposing a portion of the surface of the metal layer; performing a methylation treatment on the surface of the dielectric layer and the sidewall surface of the contact hole; performing a hydrogen plasma treatment on the surface of the metal layer after the methylation treatment; and forming a conductive plug in the contact hole after the hydrogen plasma treatment, wherein the methylation treatment replaces the hydroxyl dangling bonds with methyl bonds, and while removing the hydroxyl dangling bonds, oxygen ions are not introduced, which is beneficial to the selective growth of the conductive plug material on the surface of the metal layer, and a conductive plug material with a lower defect density can be formed, thereby improving the performance of the formed conductive plug and obtaining a conductive plug with a lower resistivity.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The contact hole is a connecting channel between the device in the chip and the metal of the first layer, and the connection between different devices is displayed through etching of the contact hole and the metal layer. Tungsten is introduced as a via fill material into integrated circuit fabrication processes of submicron and below. However, as the dimensions of integrated circuit devices continue to shrink, the aspect ratio of the contact holes continues to increase, which presents a significant challenge to the existing tungsten fill process, CVD (Chemical Vapor Deposition ) has very good step coverage, and is therefore widely used in the fill process of contact holes, but faces the problem of high resistance of the conductive plugs formed.
The resistance of the conductive plug affects the speed of the chip, so that effective reduction of the resistance of the conductive plug has become an important issue in advanced semiconductor manufacturing processes.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a dielectric layer, a contact hole, a methyl bond and a conductive plug, wherein the substrate comprises a base, a metal layer is arranged on the surface of the base, the dielectric layer is arranged on the substrate, the contact hole is arranged in the dielectric layer, the contact hole exposes part of the surface of the metal layer, the methyl bond is arranged on the surface of the dielectric layer and the surface of the side wall of the contact hole, and the conductive plug is arranged in the contact hole.
Optionally, an etch stop layer is also included between the dielectric layer and the substrate.
Correspondingly, the technical scheme of the invention also provides a forming method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a dielectric layer and a contact hole in the dielectric layer on the substrate, wherein the substrate comprises a base and a metal layer positioned on the surface of the base, the contact hole exposes part of the surface of the metal layer, carrying out methylation treatment on the surface of the dielectric layer and the surface of the side wall of the contact hole, carrying out hydrogen plasma treatment on the surface of the metal layer after the methylation treatment, and forming a conductive plug in the contact hole after the hydrogen plasma treatment.
Optionally, the methylation treatment process comprises a dry treatment process or a wet treatment process.
Optionally, the dry treatment process comprises a plasma treatment process, and the process parameters of the plasma treatment process comprise that the adopted plasma gas comprises linear alkane.
Optionally, the technological parameters of the hydrogen plasma treatment process comprise energy ranging from 50 watts to 500 watts and temperature ranging from 50 ℃ to 600 ℃.
Optionally, the method for forming the contact hole comprises the steps of forming a dielectric material layer on the surface of the substrate, forming a patterned layer on the surface of the dielectric material layer, wherein the patterned layer exposes a part of the dielectric material layer on the metal layer, and etching the dielectric material layer by taking the patterned layer as a mask until the metal layer is exposed, so that the dielectric layer and the contact hole in the dielectric layer are formed.
Optionally, the dielectric material layer and the substrate surface are further provided with an etching stop material layer, the forming process of the contact hole further comprises the step that the etching stop material layer is etched to form an etching stop layer, and the contact hole is further located in the etching stop layer.
Optionally, the material of the etch stop layer comprises a combination of one or more of silicon nitride, silicon oxynitride, aluminum nitride, and nitrogen-doped carbon.
Optionally, the thickness of the etch stop layer ranges from 50 angstroms to 400 angstroms.
Optionally, the forming process of the conductive plug includes a selective deposition process.
Optionally, the forming process parameters of the conductive plug comprise that the flow ratio of tungsten hexafluoride to hydrogen is 1/20 to 1/150, the temperature is 200 ℃ to 600 ℃, and the pressure is 5 torr to 400 torr.
Optionally, the material of the conductive plug includes tungsten.
Optionally, the material of the dielectric layer includes silicon oxide.
Optionally, after the contact hole is formed, before the methylation treatment, the contact hole and the surface of the dielectric layer are further cleaned.
Optionally, the material of the metal layer includes cobalt, tungsten or copper.
Optionally, the depth of the contact hole in the direction vertical to the surface of the substrate ranges from 100 angstroms to 800 angstroms, and the size of the contact hole in the direction parallel to the surface of the substrate ranges from 10 nanometers to 50 nanometers.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the method for forming the semiconductor structure provided by the technical scheme of the invention, the surface of the dielectric layer and the surface of the side wall of the contact hole are subjected to methylation, after the methylation, the surface of the metal layer is subjected to hydrogen plasma treatment, the hydrogen plasma treatment can remove an oxide layer on the surface of the metal layer, and compared with the oxygen plasma treatment on the surface of the dielectric layer, the methylation enables the hydroxyl dangling bond to be replaced by a methyl bond (-CH 3), oxygen ions are not introduced while the hydroxyl dangling bond is removed, so that the hydroxyl dangling bond is not introduced again in the hydrogen plasma treatment process, and the subsequent growth of the conductive plug material on the side wall of the contact hole and the surface of the dielectric layer is not caused, namely, the selective growth of the conductive plug material on the surface of the metal layer is facilitated, and the conductive plug material with lower defect density can be formed, so that the performance of the formed conductive plug is improved, and the conductive plug with lower resistivity is obtained.
Drawings
FIGS. 1-5 are schematic cross-sectional views of a semiconductor structure forming process;
fig. 6-10 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background art, the method for forming the conductive plugs in the prior art needs to be improved.
Fig. 1-4 are schematic cross-sectional views of a semiconductor structure forming process.
Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 comprises a base 101 and a metal layer 102 on the surface of the base, a dielectric layer 103 and a contact hole 104 in the dielectric layer 103 are formed on the substrate 100, the contact hole 104 exposes a part of the surface of the metal layer 102, and the surface of the substrate 100 is cleaned.
Referring to fig. 2, oxygen plasma treatment is performed on the surface of the dielectric layer 103 and the surface of the sidewall of the contact hole 104 to remove the hydroxyl group a (-OH) on the surface of the dielectric layer 103 and the sidewall of the contact hole 104.
Referring to fig. 3, after the oxygen plasma treatment, a hydrogen plasma treatment is performed on the surface of the dielectric layer 103 and the surface of the sidewall of the contact hole 104.
Referring to fig. 4 or fig. 5, after the hydrogen plasma treatment, a conductive plug 105 is formed in the contact hole 104.
In the above method, the conductive plugs 105 are formed. In the case where the hydroxyl groups on the surface of the dielectric layer 103 and the sidewalls of the contact hole 104 are completely removed, the conductive plug 105 material may achieve selective growth on the surface of the metal layer 102, thereby forming a low defect conductive plug 105 as shown in fig. 4. However, in the method, after the surface of the substrate 100 is cleaned, the surface of the dielectric layer 103 and the sidewall of the contact hole 104 have a large amount of hydroxyl groups a (as shown in fig. 1), and the hydroxyl groups a are reduced by oxygen plasma treatment (as shown in fig. 2), but the exposed surface of the metal layer 102 is formed into the metal oxide layer 105 by the oxygen plasma treatment, and the hydrogen plasma treatment is used for removing the metal oxide layer 105, whereas the hydrogen plasma treatment increases the amount of hydroxyl groups a (as shown in fig. 3). Hydroxyl groups a may become nucleation sites for the growth of the conductive plug 106 material, and a large number of hydroxyl groups a may even disable the selective growth of the conductive plug 106 material on the surface of the metal layer 102, resulting in the conductive plug 106 shown in fig. 5. Part of the hydroxyl groups a (such as hydroxyl groups a at position I shown in fig. 3) may form defects b (shown in fig. 5) during formation of the conductive plugs 106, thereby causing the conductive plugs 106 to be formed to have higher defects, resulting in an increase in resistivity of the conductive plugs 106 and a decrease in electrical properties of the conductive plugs.
In order to solve the above problems, in the method for forming a semiconductor structure provided by the present invention, methylation is performed on the surface of the dielectric layer and the surface of the sidewall of the contact hole, after the methylation, hydrogen plasma treatment is performed on the surface of the metal layer, the hydrogen plasma treatment can remove an oxide layer on the surface of the metal layer, and compared with oxygen plasma treatment performed on the surface of the dielectric layer, the methylation makes the hydroxyl dangling bond replaced by a methyl bond (-CH 3), and oxygen ions are not introduced while the hydroxyl dangling bond is removed, so that the hydroxyl dangling bond is not reintroduced in the hydrogen plasma treatment process, thereby not causing the subsequent growth of conductive plug materials on the sidewall of the contact hole and the surface of the dielectric layer, that is, facilitating the selective growth of conductive plug materials on the surface of the metal layer, and forming a conductive plug material with lower defect density, thereby improving the performance of the formed conductive plug and obtaining a conductive plug with lower resistivity.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6-10 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 6, a substrate 200 is provided, the substrate 200 includes a base 201, and a metal layer 202 disposed on a surface of the base 201.
The substrate 200 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon, or semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., or insulating dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, etc. The substrate 200 may be a single-layer structure, the substrate 200 may be a composite structure, for example, a device (such as a transistor) may be formed in the substrate, or the substrate may be an insulating dielectric layer, a connection line for connecting the transistor is formed in the substrate, and the metal layer is located on the top surface of the connection line.
In this embodiment, the material of the metal layer 202 is cobalt. In other embodiments, the material of the metal layer 202 may be copper, tungsten, or other metals.
Referring to fig. 7, a dielectric layer 203 and a contact hole 204 located in the dielectric layer 203 are formed on the substrate 200, and the contact hole 204 exposes a portion of the surface of the metal layer 202.
The material of the dielectric layer 203 includes silicon oxide. In this embodiment, the material of the dielectric layer 203 is silicon oxide. In other embodiments, the material of the dielectric layer 203 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
The process of forming the dielectric layer 203 includes a chemical vapor deposition process. In this embodiment, the formation process of the dielectric layer 203 is a high-density plasma chemical vapor deposition process.
The contact hole 204 is formed by a dry etching process.
The depth of the contact hole 204 in a direction perpendicular to the surface of the substrate 200 ranges from 100 to 800 angstroms, and the size of the contact hole 204 in a direction parallel to the surface of the substrate 200 ranges from 10nm to 50 nm.
The method for forming the contact hole 204 includes forming a dielectric material layer (not shown) on the surface of the substrate 200, forming a patterned layer (not shown) on the surface of the dielectric material layer, wherein the patterned layer exposes a portion of the dielectric material layer on the metal layer 202, and etching the dielectric material layer with the patterned layer as a mask until the metal layer 202 is exposed, thereby forming the dielectric layer 203 and the contact hole 204 located in the dielectric layer 203.
In this embodiment, the dielectric material layer and the surface of the substrate 200 further have an etching stop material layer (not shown), and the process for forming the contact hole 204 further includes etching the etching stop material layer to form an etching stop layer 205, where the contact hole 204 is further located in the etching stop layer 205.
The material of the etch stop layer 205 includes a combination of one or more of silicon nitride, silicon oxynitride, aluminum nitride, and nitrogen-doped carbon. In this embodiment, the material of the etching stop layer 205 is silicon nitride.
The thickness of the etch stop layer 205 ranges from 50 a to 400 a.
And subsequently, carrying out methylation treatment on the surface of the dielectric layer 203 and the surface of the side wall of the contact hole 204.
In this embodiment, after the contact hole 204 is formed, the surfaces of the contact hole 204 and the dielectric layer 203 are also cleaned before the methylation treatment. The cleaning process is used to obtain a clean surface that facilitates subsequent formation of low defect conductive plugs within the contact holes 204.
However, when the dielectric layer 203 and the contact hole 204 are exposed to air, a large number of hydroxyl (-OH) dangling bonds c are formed on the side walls of the contact hole 204 and the surface of the dielectric layer 203, and in the subsequent conductive plug formation process, the hydroxyl dangling bonds c may cause the conductive plug material to grow on the surface of the dielectric layer 203 and the side walls of the contact hole 204, which is unfavorable for the formation of the conductive plug. In order to selectively grow the conductive plug material on the metal layer 202, a methylation treatment is subsequently performed on the surface of the dielectric layer 203 and the surface of the sidewall of the contact hole 204.
The metal layer 202 is also susceptible to the formation of a metal oxide layer 206 on the surface of the metal layer 202 due to exposure to air. Subsequently, before forming the conductive plugs in the contact holes 204, the metal oxide layer 206 needs to be removed to facilitate reducing the contact resistance between the conductive plugs and the metal layer 202.
Referring to fig. 8, the surface of the dielectric layer 203 and the surface of the sidewall of the contact hole 204 are subjected to methylation treatment.
The methylation treatment process comprises a dry treatment process or a wet treatment process.
The dry treatment process comprises a plasma treatment process, wherein the process parameters of the plasma treatment process comprise that the adopted plasma gas comprises linear alkane. The linear alkane has a chemical formula of C nH2n+2 (n < 10), and comprises gases such as methane, ethane and the like. In this embodiment, the methylation treatment process adopts a dry treatment process, and the plasma gas used is methane.
The wet treatment process comprises the step of adopting a trimethylmethoxysilane solution. Trimethylmethoxysilane can react with hydroxyl dangling bonds to form methyl bonds.
The methylation treatment replaces the hydroxyl dangling bond c with a methyl bond d (-CH 3), and oxygen ions are not introduced while the hydroxyl dangling bond c is removed. Subsequently, a hydrogen plasma treatment is performed on the surface of the dielectric layer 203 and the surface of the sidewall of the contact hole 204 to remove the metal oxide layer 206. Because oxygen ions are not introduced into the surface of the dielectric layer 203 and the surface of the contact hole 204 in the methylation treatment, hydroxyl dangling bonds are not introduced again in the hydrogen plasma treatment process, so that the subsequent growth of the conductive plug material on the side wall of the contact hole and the surface of the dielectric layer is not caused, the selective growth of the conductive plug material on the surface of the metal layer is facilitated, the conductive plug material with lower defect density can be formed, the performance of the formed conductive plug is improved, and the conductive plug with lower resistivity is obtained.
Referring to fig. 9, after the methylation process, a hydrogen plasma process is performed on the surface of the metal layer 202.
The hydrogen plasma treatment process comprises the following process parameters of 50-500 watts and 50-600 ℃ of energy.
The hydrogen plasma treatment is used to remove the metal oxide layer 206 from the surface of the metal layer 202. After the plasma treatment, a plurality of methyl bonds d exist on the surface of the dielectric layer 203 and the surface of the side wall of the contact hole 204.
Referring to fig. 10, after the hydrogen plasma treatment, a conductive plug 206 is formed in the contact hole 204.
The method for forming the conductive plugs 206 includes forming a conductive plug material (not shown) in the contact holes 204, filling the contact holes 204 with the conductive plug material, and planarizing the conductive plug material until the surface of the dielectric layer 203 is exposed.
The process parameters for forming the conductive plugs 206 include a flow ratio of tungsten hexafluoride to hydrogen ranging from 1/20 to 1/150, a temperature ranging from 200 degrees celsius to 600 degrees celsius, and a pressure ranging from 5 torr to 400 torr.
The material of the conductive plugs 206 includes tungsten.
The formation process of the conductive plug 206 includes a selective deposition process. The selective deposition process is advantageous for forming the conductive plugs 206 with low defects, and reduces the contact resistance between the conductive plugs 206 and the metal layer 202.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, and please continue to refer to fig. 10, which includes a substrate 200, wherein the substrate 200 includes a base 201, a metal layer 202 disposed on a surface of the base 201, a dielectric layer 203 disposed on the substrate 200, a contact hole 204 (as shown in fig. 9) disposed in the dielectric layer 203, wherein a portion of the surface of the metal layer 202 is exposed by the contact hole 204, methyl bonds disposed on a surface of the dielectric layer 203 and a surface of a sidewall of the contact hole 204, and a conductive plug 207 disposed in the contact hole 204.
In this embodiment, the semiconductor structure further comprises an etch stop layer 205 between the dielectric layer 203 and the substrate 200.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a base and a metal layer positioned on the surface of the base;
Forming a dielectric layer and a contact hole in the dielectric layer on the substrate, wherein the contact hole exposes part of the surface of the metal layer, and the side wall of the contact hole and the surface of the dielectric layer are provided with hydroxyl suspension bonds;
The surface of the dielectric layer and the surface of the side wall of the contact hole are subjected to methylation treatment, wherein the methylation treatment process comprises a dry treatment process, the dry treatment process comprises a plasma treatment process, and the process parameters of the plasma treatment process comprise that the adopted plasma gas comprises linear alkane, the methylation treatment enables the hydroxyl dangling bond to be replaced by a methyl bond, and oxygen ions are not introduced while the hydroxyl dangling bond is removed;
After the methylation treatment, carrying out hydrogen plasma treatment on the surface of the metal layer;
And after the hydrogen plasma treatment, forming a conductive plug in the contact hole.
2. The method of claim 1, wherein the hydrogen plasma treatment process comprises a process parameters including an energy range of 50 watts to 500 watts and a temperature range of 50 degrees celsius to 600 degrees celsius.
3. The method for forming a semiconductor structure according to claim 1, wherein the method for forming a contact hole comprises the steps of forming a dielectric material layer on the surface of the substrate, forming a patterned layer on the surface of the dielectric material layer, wherein the patterned layer exposes a part of the dielectric material layer on the metal layer, and etching the dielectric material layer by taking the patterned layer as a mask until the metal layer is exposed, so as to form the dielectric layer and the contact hole in the dielectric layer.
4. The method of claim 3, wherein the dielectric material layer and the substrate surface further have an etch stop material layer, and the contact hole forming process further comprises etching the etch stop material layer to form an etch stop layer, and the contact hole is further located in the etch stop layer.
5. The method of forming a semiconductor structure of claim 4, wherein the material of the etch stop layer comprises a combination of one or more of silicon nitride, silicon oxynitride, aluminum nitride, and nitrogen-doped carbon.
6. The method of forming a semiconductor structure of claim 4, wherein the etch stop layer has a thickness in a range of 50 angstroms to 400 angstroms.
7. The method of forming a semiconductor structure of claim 1, wherein the conductive plug forming process comprises a selective deposition process.
8. The method of claim 7, wherein the process parameters for forming the conductive plug comprise a flow ratio of tungsten hexafluoride to hydrogen in a range of 1/20 to 1/150, a temperature in a range of 200 degrees celsius to 600 degrees celsius, and a pressure in a range of 5 torr to 400 torr.
9. The method of forming a semiconductor structure of claim 1, wherein the conductive plug material comprises tungsten.
10. The method of forming a semiconductor structure of claim 1, wherein the material of the dielectric layer comprises silicon oxide.
11. The method of forming a semiconductor structure of claim 1, wherein after forming said contact hole, said contact hole and said dielectric layer surface are further cleaned prior to said methylation.
12. The method of forming a semiconductor structure of claim 1, wherein the material of the metal layer comprises cobalt, tungsten, or copper.
13. The method of forming a semiconductor structure of claim 1, wherein a depth of said contact hole in a direction perpendicular to said substrate surface ranges from 100 angstroms to 800 angstroms, and a dimension of said contact hole in a direction parallel to said substrate surface ranges from 10 nanometers to 50 nanometers.
14. A semiconductor structure formed by the method of any one of claims 1 to 13, comprising:
A substrate, wherein the substrate comprises a base and a metal layer positioned on the surface of the base;
the dielectric layer is positioned on the substrate, and the contact hole is positioned in the dielectric layer, and the contact hole exposes part of the surface of the metal layer;
plasma methyl bonds located on the surface of the dielectric layer and the surface of the side wall of the contact hole;
and the conductive plug is positioned in the contact hole.
15. The semiconductor structure of claim 14, further comprising an etch stop layer between said dielectric layer and said substrate.
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| TW541659B (en) * | 2002-04-16 | 2003-07-11 | Macronix Int Co Ltd | Method of fabricating contact plug |
| CN101989570A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Forming method of contact hole structure |
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| CN115132701A (en) | 2022-09-30 |
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