CN115129519A - Method and system for realizing multiple write operations of chip with efuse structure and SOC (system on chip) - Google Patents
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Abstract
The application discloses a method, a system and an SOC for realizing multiple write operations of a chip with an efuse structure, wherein the method comprises the following steps: dividing a chip area into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area; after the data writing in the first area is finished, the written data in the first area is corrected; and if the data writing error of the first bit in the first area occurs, acquiring correct data from the second area to correct the data of the first bit, wherein the first bit is any bit in the first area. When writing operation is performed on the chip of the efuse structure, if data writing errors occur or a dead pixel exists in a writing bit area, the data of the writing data error bit area can be corrected through the backup area, so that a fault tolerance opportunity is provided for the chip of the efuse structure, convenience is brought, and meanwhile the yield is improved.
Description
Technical Field
The application relates to the technical field of SOC chips, in particular to a method and a system for realizing multiple write operations of a chip with an efuse structure and an SOC.
Background
efuse is also called one-time programmable memory, and unlike SRAM arrays used by most FPGAs, efuse can only be programmed one fuse at a time, which is why there is a limited range of configuration capabilities of this approach. When used in combination with the increasingly sophisticated built-in self-test (BIST) engine, these fuses become powerful tools to reduce the cost of testing and self-repair, which is a significant challenge for complex chip designs.
When the efuse is applied to the chip, the operation efficiency of a circuit in the chip can be improved by thousands of times, and because the efuse is low in cost, the stored information cannot be lost due to power failure, so that a plurality of low-cost chips adopt the efuse to replace NVR (network video recorder) at present, and the efuse is widely applied to the chip to store key information data.
each BIT of efuse corresponds to a fuse wire, information is stored in a state without being fused or not, and the fuse wires cannot be restored after being fused, so that secondary programming operation cannot be performed. Once a write error occurs, it cannot be re-written after being erased like NVR. If a problem occurs in the CP test process or in the mass production of users, or a defect occurs in the chip manufacturing process (some bits cannot operate), the yield is reduced.
Disclosure of Invention
In order to solve the technical problems, the following technical scheme is provided:
in a first aspect, an embodiment of the present application provides a method for implementing multiple write operations on a chip with an efuse structure, where the method includes: dividing a chip area into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area; after the data writing in the first area is finished, the written data in the first area is corrected; and if the data writing error of the first bit in the first area occurs, acquiring correct data from the second area to correct the data of the first bit, wherein the first bit is any bit in the first area.
With reference to the first aspect, in a first possible implementation manner of the first aspect, if data of a first bit in the first area is wrongly written, acquiring correct data from the second area to correct the data of the first bit includes: when data is written in the first area, writing operation is not carried out on the second area; and if the first bit data in the first area is wrongly written, correcting the first bit data from any bit data in the second area.
With reference to the first aspect, in a second possible implementation manner of the first aspect, if data of a first bit in the first area is wrongly written, acquiring correct data from the second area to correct the data of the first bit includes: setting the bit positions of the first region and the second region to be equal in length; when data writing is carried out in a first area, writing second data opposite to the first data into a second area according to the first data written into the first area; and if the first bit data in the first area is wrongly written, selecting bit data at a corresponding position from the second area to correct the first bit data.
With reference to the first or second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the efuse is defaulted to a high level 1 after being powered on, and if a bit of the efuse has a bad point, the efuse writing operation is 1 and cannot be written to 0.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the correcting the first bit data includes: judging the bit data state in the first area and the second area; determining correct first bit data according to the bit data state; mapping the first bit of data to the first bit of data.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the determining correct first bit data according to the bit data state includes: when the first bit data of the first area is bad, 1 can not be written into 0 during the writing operation, and the state of the second bit data in the second area is further judged; writing the second bit data as 0 as data mapped to the first bit if the second bit data in the second region is good; or, if the second bit data in the second area is bad, and the second bit data 1 cannot be modified, any bit data of 0 is selected from the second area as the data mapped to the first bit.
In a second aspect, an embodiment of the present application provides a system for implementing multiple write operations on a chip with an efuse structure, where the system includes: the chip dividing module is used for dividing the area of a chip into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area; the checking module is used for checking the written data of the first area after the data of the first area is written; and the data correction module is used for acquiring correct data from the second area to correct the first bit data if the data write error of the first bit in the first area occurs, wherein the first bit is any bit in the first area.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the data correction module includes: the first write operation unit is used for not writing the second area when the data is written in the first area; and the first data correction unit is used for correcting the first bit data from any bit data in the second area if the first bit data in the first area is wrongly written.
With reference to the second aspect, in a second possible implementation manner of the second aspect, the data correction module includes: a setting unit, configured to set the bits of the first region and the second region to be equal in length; a second write operation unit configured to write, when data is written in a first area, second data opposite to the first data in the second area according to the first data written in the first area; and the second data correction unit is used for selecting bit data at a corresponding position from the second area to correct the first bit data if the first bit data in the first area has a write error.
With reference to the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the data correcting unit includes: a judging subunit, configured to judge bit data states in the first area and the second area; a determining subunit, configured to determine a correct first bit data according to the bit data state, including: when the first bit data of the first area is bad, 1 can not be written into 0 during the writing operation, and the state of the second bit data in the second area is further judged; writing the second bit data as 0 as data mapped to the first bit if the second bit data in the second region is good; or if the second bit data in the second area is bad, the second bit data 1 cannot be modified, and any bit data of 0 is selected from the second area as the data mapped to the first bit; a mapping subunit configured to map the first bit of data to the first bit of data.
In a third aspect, an embodiment of the present application provides an SOC, including a processor and an eFuse structure chip, where the processor executes the method described in the first aspect or any one of the possible implementation manners of the first aspect to implement multiple write operations to the eFuse structure chip.
Compared with the prior art, the technical scheme of the application has the following beneficial effects at least:
when writing operation is carried out on the chip with the efuse structure, if data writing errors exist or a dead pixel exists in a writing bit area, data in the writing data error bit area can be corrected through the backup area, the fault-tolerant opportunity is provided for the chip with the efuse structure, convenience is brought, and meanwhile the yield is improved.
Drawings
Fig. 1 is a schematic flowchart of a method for implementing multiple write operations on a chip with an efuse structure according to an embodiment of the present application;
fig. 2 is a schematic diagram of a system for implementing multiple write operations on a chip with an efuse structure according to an embodiment of the present application;
fig. 3 is a schematic diagram of an SOC framework according to an embodiment of the present application.
Detailed Description
The present invention will be described with reference to the accompanying drawings and embodiments.
Fig. 1 is a schematic flow chart of a method for implementing multiple write operations on a chip with an efuse structure according to an embodiment of the present application, and referring to fig. 1, the method for implementing multiple write operations on a chip with an efuse structure according to the embodiment includes:
s101, dividing a chip area into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area.
In this embodiment, when the chip area is divided, the first area determines the number of bits according to the data to be written, and therefore the length of the first area is generally related to the data to be written, and the length is fixed. In the second area, there are at least two cases:
the first is to set the length of the backup area of the second area to be long enough to correct the bit data of the first area. For example, the first region has 24 bits, and the second region has 8 bits reserved.
The second is to set the length of the backup area of the second area to be the same as that of the first area, that is, the first area has 16 bits, and the second area has 16 bits.
S102, after the data writing in the first area is finished, the written data in the first area is corrected.
After the data writing operation of the efuse is completed, the bit data read after the writing in the first area is compared with the original data stored in the system, and during the comparison, according to the written data sequence, data correction is performed from the bit at the beginning of writing to the last bit one by one, so that the problem bit data is screened.
S103, if the data writing of the first bit in the first area is wrong, correct data is obtained from the second area to correct the data of the first bit, and the first bit is any bit in the first area.
In an exemplary embodiment, when data is written to the first area, no write operation is performed to the second area. And if the first bit data in the first area is wrongly written, correcting the first bit data from any bit data in the second area.
The corresponding situation in this embodiment is the first situation in S101, and the length of the backup area in the second area is set to be sufficient, and only the bit data error correction of the first area needs to be satisfied. As shown in table 1:
TABLE 1 initial value of efuse bit
The efuse defines that the length of the written data is 32 bits, each Bit is initially 1, 1 of the corresponding Bit is changed into 0 through the efuse control during the writing operation, and the written data cannot be modified again after being fused, that is, cannot be erased again. According to the specification requirement, a certain number of efuses are defined by a common chip, and a backup area (BKP area) is defined at the same time, wherein the BKP area is also located in the efuses and is mapped to any bit of any address of the efuses area through address mapping.
Since the BKP area is also efuse in nature, the default of power-on is 1. Since the efuse write operation only changes 1 to 0, if the efuse write has an error, it indicates that a bit should be 1 correctly, and is wrongly written to 0, a bit in the BKP area can be mapped to the bit in the write operation area that is erroneous.
If 0x3ffffffc is written to address XXX during production, the correct result should be as shown in Table 2:
TABLE 2 efuse bit theoretical write value
| Bit31 | Bit30 | Bit29 | Bit28 | …… | Bit1 | Bit0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
In practice, the situation of table 3 actually occurs:
TABLE 3 actual write value of efuse bit
This may be the case, either as a production problem or as an unexpected disturbance or timing error in the writing process. However, if the data is important, the client must be used and the software needs to load the data after power-up. It is likely that the system will not run up because the data is corrupted. To compensate for this problem, one or two BITs of the BKP region may be addressed to BITs BIT30 and BIT29, while the mapping to the BIT30 region is written as 0. Thus BITs that are not consecutive addresses constitute new data, which can be read by software.
In another exemplary embodiment, the bits of the first region and the bits of the second region are set to be of equal length. When data writing is carried out in a first area, writing second data opposite to the first data into a second area according to the first data written into the first area; and if the first bit data in the first area is wrongly written, selecting bit data at a corresponding position from the second area to correct the first bit data.
The corresponding situation in this embodiment is the second in S101, and in this embodiment, the write data length is defined as 16 bits, and the efuse has 32 bits. The division of the efuse area for 32 bits into an upper 16-bit code reversal area and a lower 16-bit data area is shown in table 4.
TABLE 4 efuse area partitioning
When writing the first area of the efuse, the hardware automatically calculates the complement value of the BIT corresponding to the second area, writes the complement value into the corresponding address area together with the data of the first area, then the hardware can automatically read the data area, and compares the inverted low 16-BIT data with the read high 16-BIT data and resets the state BIT. The status bit can be read by software when being powered on, if the status bit indicates that the efuse data is normal, the data area can be directly read, if the efuse data is abnormal, the code reversal area with 16 high bits can be read, and the data is reversed to obtain real data.
As described above, the entire efuse data area is divided into the first area (data area) and the second area (decoding area), and the decoding area is obtained by inverting the data in the data area.
When the efuse is not programmed by default, each BIT value is 1, 1 is changed into 0 in the writing process, after the writing operation of the data area is completed, hardware can automatically read the value of the efuse and compare the value with the written data, if the value is equal, the written 0 is successfully written, and meanwhile, the default value of the code reversal area is also 1, namely the code reversal of 0, and the process is ended. If the comparison result is not equal, it indicates whether the bit is 1, and writing 0 is not successful. Then the hardware further writes to the anti-code region at this point, changing the 1 of the anti-code region to 0.
Because efuse is defaulted to high level 1 after power-on, if bit of efuse has a bad point, efuse write operation is 1 and cannot be written to 0. Then, in this embodiment, correcting the first bit data includes: and judging the bit data states in the first area and the second area, determining correct first bit data according to the bit data states, and mapping the first bit data to the first bit.
For single BIT, there are four cases of first region BIT data (original code) and second region BIT data (inverse code). Namely, good decoding of the first original code of the scene, good decoding of the second original code of the scene, good decoding of the third original code of the scene, and bad decoding of the fourth original code of the scene. If the original code is good for the first two cases, the '1' can be changed to '0', so the inverse code only needs to keep the default '1', does not need any operation, and is not considered in the present embodiment.
For the latter two cases, when the original code is bad, 1 cannot be written as 0 in the write operation, and the state of the complement in the second area is further judged. If the anticode is good in the second region, the anticode is written as 0 as the data mapped to the first bit. And if the code reversal in the second area is bad, the code reversal 1 cannot be modified, and any code reversal which is 0 is selected from the second area to be used as the data mapped to the first bit.
That is, if the original code is good when the code is bad, the original code can be deduced by changing '1' of the code to 0. For the case where the original code is bad and the inverse code is also bad, both can be seen as '1'. After the power is on, the software can read out the efuse data to judge whether the original code and the inverse code are inverse codes to each other, if the original code and the inverse code are both '1', the situation is that the original code and the inverse code are both bad, and at this time, the '0' can be used for replacing the real data.
For example, the following steps are carried out:
example 1: a bit address of a certain data area has a dead pixel, and 0 cannot be really written. In the process of writing operation, the hardware judges that the defect point is the bad point, and then the decoding area is written. After the write operation, if the code is 0 according to the inverse code reading, and the code is 1 according to the original code reading, the scenario three is described above. After power is supplied again, the software can judge the real data according to the value
Example 2: the bit address and the anti-code area of a certain data area have bad points, and 0 can not be really written. For the situation, the reading of the inverse code and the original code is 1, any inverse code of 0 is selected from the inverse code area to be used as a bit mapped to a data area with a dead pixel, and the software can obtain a true value of 0 according to the value when the software is electrified.
The above situation is directed at the fault of chip production, and the yield can be improved to a certain extent. If the problem is not the problem of the chip itself, and data is wrongly written or the data is written due to interference, the problem can be solved by programming the anti-code again, and the idea is basically similar.
In the chip manufacturing process, if the efuse yield rate occurs, the structure can solve the yield rate problem to a certain extent, and certain economic benefit is generated. And when the efuse code is debugged in the initial stage, certain fault tolerance is achieved, and the defect that the efuse can only be programmed once is avoided.
The present application further provides an embodiment of a system for implementing multiple write operations on a chip with an efuse structure.
Referring to fig. 2, a system 20 for implementing chip write operations of the efuse architecture includes: a chip dividing module 201, a proofreading module 202 and a data correcting module 203.
The chip dividing module 201 is configured to divide an area of a chip into a first area and a second area, where the first area is a data writing area, and the second area is a backup area. The checking module 202 is configured to check the written data of the first area after the data of the first area is written. A data correcting module 203, configured to, if a data write error occurs in a first bit in the first area, obtain correct data from the second area to correct the first bit, where the first bit is any bit in the first area.
In an exemplary embodiment, the data correction module 203 includes: a first write operation unit and a first data correction unit. And the first writing operation unit is used for not writing the second area when the data is written in the first area. And the first data correction unit is used for correcting the first bit data from any bit data in the second area if the first bit data in the first area is wrongly written.
In another exemplary embodiment, the data correction module includes: the device comprises a setting unit, a second writing operation unit and a second data correction unit. And the setting unit is used for setting the bits of the first area and the second area to be equal in length. And the second write operation unit is used for writing second data opposite to the first data into the second area according to the first data written into the first area when the data is written into the first area. And the second data correction unit is used for selecting bit data at a corresponding position from the second area to correct the first bit data if the first bit data in the first area has a write error.
In this embodiment, the data correction unit includes: a judgment subunit, a determination subunit and a mapping subunit.
And the judging subunit is used for judging the bit data state in the first area and the second area. A determining subunit, configured to determine a correct first bit data according to the bit data state, including: when the first bit data of the first area is bad, 1 can not be written into 0 during the writing operation, and the state of the second bit data in the second area is further judged; writing the second bit data to 0 as data mapped to the first bit if the second bit data in the second region is good; or, if the second bit data in the second area is bad, and the second bit data 1 cannot be modified, any bit data of 0 is selected from the second area as the data mapped to the first bit. A mapping subunit configured to map the first bit of data to the first bit of data.
Referring to fig. 3, an embodiment of the present application further provides an SOC, where the SOC includes a processor 301 and an efuse structure chip 302, and when performing write processing on the efuse structure chip 302, the processor 301 executes the method in the foregoing embodiment to divide an area of the chip into a first area and a second area, where the first area is a data write area, and the second area is a backup area; after the data writing in the first area is finished, the written data in the first area is corrected; and if the data writing error of the first bit in the first area occurs, acquiring correct data from the second area to correct the data of the first bit, wherein the first bit is any bit in the first area.
When writing operation is carried out on the chip with the efuse structure, if data writing errors exist or a dead pixel exists in a writing bit area, data in the writing data error bit area can be corrected through the backup area, the fault-tolerant opportunity is provided for the chip with the efuse structure, convenience is brought, and meanwhile the yield is improved.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Of course, the above description is not limited to the above examples, and technical features that are not described in the present application may be implemented by or using the prior art, and are not described herein again; the above embodiments and drawings are only for illustrating the technical solutions of the present application and not for limiting the present application, and the present application is only described in detail with reference to the preferred embodiments instead, it should be understood by those skilled in the art that changes, modifications, additions or substitutions within the spirit and scope of the present application may be made by those skilled in the art without departing from the spirit of the present application, and the scope of the claims of the present application should also be covered.
Claims (10)
1. A method for realizing multiple write operations of a chip with an efuse structure is characterized by comprising the following steps:
dividing a chip area into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area;
after the data writing in the first area is finished, the written data in the first area is corrected;
and if the data writing error of the first bit in the first area occurs, acquiring correct data from the second area to correct the data of the first bit, wherein the first bit is any bit in the first area.
2. The method for realizing chip multiple write operation of the efuse structure according to claim 1, wherein if the data of the first bit in the first area is wrongly written, acquiring correct data from the second area to correct the data of the first bit comprises:
when data is written in the first area, writing operation is not carried out on the second area;
and if the first bit data in the first area is wrongly written, correcting the first bit data from any bit data in the second area.
3. The method for realizing chip multiple write operation of the efuse structure according to claim 1, wherein if the data of the first bit in the first area is wrongly written, acquiring correct data from the second area to correct the data of the first bit comprises:
setting the bit positions of the first region and the second region to be equal in length;
when data writing is carried out in a first area, writing second data opposite to the first data into a second area according to the first data written into the first area;
and if the first bit data in the first area is wrongly written, selecting bit data at a corresponding position from the second area to correct the first bit data.
4. The method for realizing multiple write operations of the chip with the efuse structure according to claim 2 or 3, wherein the efuse is defaulted to high level 1 after being powered on, and if there is a bad point in a bit of the efuse, the efuse write operation is 1 and cannot be written to 0.
5. The method for realizing the chip multiple write operation of the efuse structure according to claim 4, wherein the correcting the first bit data comprises:
judging the bit data state in the first area and the second area;
determining correct first bit data according to the bit data state;
mapping the first bit of data to the first bit of data.
6. The method for realizing chip multiple write operations of an efuse structure according to claim 5, wherein the determining the correct first bit data according to the bit data state comprises:
when the first bit data of the first area is bad, 1 can not be written into 0 during the writing operation, and the state of the second bit data in the second area is further judged;
writing the second bit data as 0 as data mapped to the first bit if the second bit data in the second region is good; or,
and if the second bit data in the second area is bad and the second bit data 1 cannot be modified, selecting any bit data of 0 from the second area as the data mapped to the first bit.
7. A system for implementing a chip multiple write operation of an efuse architecture, the system comprising:
the chip dividing module is used for dividing the area of the chip into a first area and a second area, wherein the first area is a data writing area, and the second area is a backup area;
the correction module is used for correcting the written data of the first area after the data writing of the first area is finished;
and the data correction module is used for acquiring correct data from the second area to correct the first bit data if the data write error of the first bit in the first area occurs, wherein the first bit is any bit in the first area.
8. The system for realizing chip multiple write operation of efuse structure according to claim 7, wherein the data correction module comprises:
the first write operation unit is used for not writing the second area when the data is written in the first area;
and the first data correction unit is used for correcting the first bit data from any bit data in the second area if the first bit data in the first area is wrongly written.
9. The system for realizing chip multiple write operation of efuse structure according to claim 7, wherein the data correction module comprises:
a setting unit, configured to set the bits of the first region and the second region to be equal in length;
a second write operation unit configured to write, when data is written in a first area, second data opposite to the first data in the second area according to the first data written in the first area;
and the second data correction unit is used for selecting bit data at a corresponding position from the second area to correct the first bit data if the first bit data in the first area has a write error.
10. The system for realizing chip multiple write operation of efuse structure according to claim 9, wherein the data correcting unit includes:
a judging subunit, configured to judge bit data states in the first area and the second area;
a determining subunit, configured to determine a correct first bit data according to the bit data state, including:
when the first bit data of the first area is bad, 1 can not be written into 0 during the writing operation, and the state of the second bit data in the second area is further judged;
writing the second bit data to 0 as data mapped to the first bit if the second bit data in the second region is good; or,
if the second bit data in the second area is bad, the second bit data 1 cannot be modified, and any bit data of 0 is selected from the second area as data mapped to the first bit;
a mapping subunit configured to map the first bit of data to the first bit of data.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115499104A (en) * | 2022-10-24 | 2022-12-20 | 上海泰矽微电子有限公司 | Communication method between chip die |
| CN115954037A (en) * | 2023-03-10 | 2023-04-11 | 上海泰矽微电子有限公司 | Method, device and equipment for improving yield of efuse chip and storage medium |
| CN117573155A (en) * | 2024-01-16 | 2024-02-20 | 成都电科星拓科技有限公司 | Product information processing method and chip |
| CN118098327A (en) * | 2024-04-29 | 2024-05-28 | 珠海正和微芯科技有限公司 | EFUSE error correction method and device, storage medium and electronic equipment |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
| CN103839591A (en) * | 2014-03-05 | 2014-06-04 | 福州瑞芯微电子有限公司 | Automatic fault detection and fault-tolerant circuit of memory as well as control method |
| CN108899061A (en) * | 2018-07-20 | 2018-11-27 | 北京嘉楠捷思信息技术有限公司 | Memory built-in self-test method and system in power supply normally-open chip |
| CN109634919A (en) * | 2018-10-16 | 2019-04-16 | 西北铁道电子股份有限公司 | A kind of file management system |
| CN111078462A (en) * | 2019-12-26 | 2020-04-28 | 海光信息技术有限公司 | Data checking method and circuit |
| CN112181709A (en) * | 2020-09-08 | 2021-01-05 | 国电南瑞科技股份有限公司 | A fault tolerance method for single event effect in RAM storage area of FPGA chip |
| CN112802534A (en) * | 2020-12-28 | 2021-05-14 | 杭州晋旗电子科技有限公司 | Automatic error correction data storage method for electronic detonator chip |
| CN112825265A (en) * | 2019-11-21 | 2021-05-21 | 爱思开海力士有限公司 | Memory, memory system, operation method of memory, and operation of memory system |
| CN114530189A (en) * | 2022-01-27 | 2022-05-24 | 成都宏熠电子科技有限公司 | Chip repairing method, chip repairing device and chip |
-
2022
- 2022-09-02 CN CN202211067624.6A patent/CN115129519A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777013A (en) * | 2009-01-12 | 2010-07-14 | 成都市华为赛门铁克科技有限公司 | Solid state disk and data read-write method |
| CN103187095A (en) * | 2011-12-30 | 2013-07-03 | 联芯科技有限公司 | Efuse module control method and chip with efuse module |
| CN103839591A (en) * | 2014-03-05 | 2014-06-04 | 福州瑞芯微电子有限公司 | Automatic fault detection and fault-tolerant circuit of memory as well as control method |
| CN108899061A (en) * | 2018-07-20 | 2018-11-27 | 北京嘉楠捷思信息技术有限公司 | Memory built-in self-test method and system in power supply normally-open chip |
| CN109634919A (en) * | 2018-10-16 | 2019-04-16 | 西北铁道电子股份有限公司 | A kind of file management system |
| CN112825265A (en) * | 2019-11-21 | 2021-05-21 | 爱思开海力士有限公司 | Memory, memory system, operation method of memory, and operation of memory system |
| CN111078462A (en) * | 2019-12-26 | 2020-04-28 | 海光信息技术有限公司 | Data checking method and circuit |
| CN112181709A (en) * | 2020-09-08 | 2021-01-05 | 国电南瑞科技股份有限公司 | A fault tolerance method for single event effect in RAM storage area of FPGA chip |
| CN112802534A (en) * | 2020-12-28 | 2021-05-14 | 杭州晋旗电子科技有限公司 | Automatic error correction data storage method for electronic detonator chip |
| CN114530189A (en) * | 2022-01-27 | 2022-05-24 | 成都宏熠电子科技有限公司 | Chip repairing method, chip repairing device and chip |
Non-Patent Citations (2)
| Title |
|---|
| --: "《MEMs for Improved Power Management》", 22 February 2005 * |
| --: "《Selectable Memory Mapping of Redundant Efuse Address Space》", 3 December 2008 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115499104A (en) * | 2022-10-24 | 2022-12-20 | 上海泰矽微电子有限公司 | Communication method between chip die |
| CN115954037A (en) * | 2023-03-10 | 2023-04-11 | 上海泰矽微电子有限公司 | Method, device and equipment for improving yield of efuse chip and storage medium |
| CN117573155A (en) * | 2024-01-16 | 2024-02-20 | 成都电科星拓科技有限公司 | Product information processing method and chip |
| CN117573155B (en) * | 2024-01-16 | 2024-04-09 | 成都电科星拓科技有限公司 | Product information processing method and chip |
| CN118098327A (en) * | 2024-04-29 | 2024-05-28 | 珠海正和微芯科技有限公司 | EFUSE error correction method and device, storage medium and electronic equipment |
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