CN115128418B - Wafer level high-speed signal testing device - Google Patents
Wafer level high-speed signal testing device Download PDFInfo
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- CN115128418B CN115128418B CN202210683591.1A CN202210683591A CN115128418B CN 115128418 B CN115128418 B CN 115128418B CN 202210683591 A CN202210683591 A CN 202210683591A CN 115128418 B CN115128418 B CN 115128418B
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- 238000012360 testing method Methods 0.000 title claims abstract description 54
- 238000002513 implantation Methods 0.000 claims abstract description 7
- 239000000523 sample Substances 0.000 claims description 37
- 238000002788 crimping Methods 0.000 claims description 6
- 239000003351 stiffener Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 22
- 239000000758 substrate Substances 0.000 description 8
- 238000003780 insertion Methods 0.000 description 7
- 230000037431 insertion Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000003014 reinforcing effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application provides a wafer-level high-speed signal testing device, and relates to the technical field of semiconductor testing. The device comprises: the PCB, the supporting plate and the conductive soft plate can be bent into a convex structure, so that the conductive soft plate is integrally in a trapezoid shape; the high-speed connector is fixed on the supporting plate, and an electrical interface of the high-speed connector is electrically connected with the edge of the conductive soft board; a through hole is formed in the center of the PCB, the supporting plate is positioned at the bottom of the PCB, the high-speed connector is arranged in the through hole, and the conductive flexible board is positioned above the through hole; the upper bottom surface of the trapezoid body of the conductive soft board is provided with a needle implantation area. The application can reduce the complexity of a high-speed interconnection structure, effectively improve the quality of signals and realize the high-frequency test performance within 67GHz of a wafer level.
Description
Technical Field
The application relates to the technical field of semiconductor testing, in particular to a wafer-level high-speed signal testing device.
Background
In the course of semiconductor fabrication, wafers must undergo numerous fabrication processes to form integrated circuits. After the Wafer (Wafer) is manufactured, there is a certain amount of defective products in the DIE (DIE) distributed on Wafer due to various manufacturing defects introduced by the process. The CP test aims to find out the defective products before packaging, thereby improving the yield of the factory and reducing the cost of subsequent packaging and testing.
The current mainstream CP test scheme requires a probe card for testing, and the probe card can be divided into a cantilever probe card and a vertical probe card. The cantilever probe has a relatively long needle and is suspended, and the control of signal integrity is very difficult, so that the highest transmission rate of general data is only 100-400 Mbps, and the test of high-speed signals is almost impossible. The structure of the vertical probe card is shown in fig. 1, and a PCB is required to be used as a carrier board, a substrate, an interposer, and auxiliary structure fixing members in the wafer test. The inter-probe contains probes (probes) for connecting substrates and wafer. subtstrate is mainly for space conversion, and the small pitch at the chip bump is converted to BGA (Ball Grid Array) ball of large pitch. The high-speed signal is required to pass through interposer, substrate from the wafer and then to the pcb (Printed Circuit Board printed circuit board) to be led out of the cable for testing, the structure is very complex, the signal integrity is greatly affected, and the insertion loss and return loss results of the current vertical probe card structure are shown in fig. 2 and 3. It can be seen that the return loss of the vertical probe card can only meet the requirements of-14 dB in 4GHz and-10 dB in 10 GHz. At signal rates greater than 4GHz, the signal quality may be extremely degraded in such transmission paths. Resulting in serious signal integrity problems such that defective products cannot be properly screened out during the CP test phase.
Disclosure of Invention
In view of the above, the embodiment of the application provides a wafer-level high-speed signal testing device, which can reduce the complexity of a high-speed interconnection structure, effectively improve the quality of signals and realize the high-frequency testing performance within 67GHz of a wafer level.
The embodiment of the application provides the following technical scheme: a wafer level high speed signal testing apparatus comprising: a PCB board, a supporting board and a conductive soft board,
the conductive soft board can be bent into a convex structure, so that the whole conductive soft board is a trapezoid;
the high-speed connector is fixed on the supporting plate, and an electrical interface of the high-speed connector is electrically connected with the edge of the conductive soft board;
a through hole is formed in the center of the PCB, the supporting plate is positioned at the bottom of the PCB, the high-speed connector is arranged in the through hole, and the conductive flexible board is positioned above the through hole;
the upper bottom surface of the trapezoid body of the conductive soft board is provided with a needle implantation area.
According to an implementation of the embodiment of the present application, the conductive flexible board is a flexible circuit board.
According to one implementation of the embodiment of the application, the support plate is a rigid plastic plate.
According to one implementation of the embodiment of the application, a cable is connected to the high-speed connector, and the cable is led out from the bottom of the PCB.
According to an implementation of the embodiment of the application, the support plate further comprises a reinforcing rib, wherein the reinforcing rib is fixed at the bottom of the support plate.
According to an implementation of the embodiment of the application, the device further comprises a boss, wherein the boss is fixed on the front surface of the supporting plate, so that the boss is positioned in the trapezoid body of the conductive flexible board, and the upper bottom surface of the trapezoid body of the conductive flexible board is fixed on the end surface of the boss.
According to an implementation of the embodiment of the present application, the planting needle area is planted with MEMS probes for connecting bumps on a wafer.
According to one implementation of the embodiment of the application, the high-speed connector is a crimp-type connector.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least: the testing device provided by the embodiment of the application adopts the FPC flexible board to complete the electrical connection from the wafer to the testing instrument, reduces the complexity of a high-speed interconnection structure, improves the quality of signals, and realizes the high-frequency testing performance within 67GHz of the wafer level. The measured data shows that the signal return loss is less than-14.5 dB within 67GHz, the signal insertion loss can be used for adjusting the wiring length and part of the structure according to the situation, and passive devices such as resistors, capacitors, inductors and the like can be added on the flexible printed circuit board to complete impedance matching. The embodiment of the application can realize the simple connection test and low-speed digital circuit test in wafer test stage, can screen out chips with poor high-speed performance through high-speed test, can support the high-speed test requirement of 67GHz and above, and avoids the waste of engineering cost in later stage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional vertical probe card;
FIG. 2 is a graph showing the insertion loss test results of a conventional vertical probe card;
FIG. 3 is a return loss test result of a conventional vertical probe card;
FIG. 4 is a schematic diagram of the front structure of a testing device according to an embodiment of the present application;
FIG. 5 is a schematic diagram of the back structure of a testing device according to an embodiment of the present application;
FIG. 6 is a side cross-sectional view of a test device according to an embodiment of the present application;
FIG. 7 is an insertion loss test result of a test apparatus according to an embodiment of the present application;
FIG. 8 is a return loss test result of a test apparatus according to an embodiment of the present application;
wherein, 1: PCB board, 2: substrate, 3: interposser (interposer), 4: probe (probe), 5: wafer (wafer), 3-1: conductive flexible board, 3-2: PCB board, 3-3: high speed connector, 3-4: cable (cable), 3-5: needle implantation area, 3-6: reinforcing ribs, 3-7: support plate, 3-8: boss, a: insertion loss; b: return loss.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The technical solution of the present application will be clearly and completely described below in detail with reference to the accompanying drawings in combination with the embodiments, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 4 to 6, an embodiment of the present application provides a wafer level high-speed signal testing apparatus, including: the PCB, the supporting plate and the conductive soft plate can be bent into a convex structure, so that the conductive soft plate is integrally in a trapezoid shape; the high-speed connector is fixed on the supporting plate, and an electrical interface of the high-speed connector is electrically connected with the edge of the conductive soft board; a through hole is formed in the center of the PCB, the supporting plate is positioned at the bottom of the PCB, the high-speed connector is arranged in the through hole, and the conductive flexible board is positioned above the through hole; the upper bottom surface of the trapezoid body of the conductive soft board is provided with a needle implantation area, and the needle implantation area is implanted with MEMS probes for connecting with bumps on a wafer.
Preferably, the conductive flexible board of the embodiment is a flexible circuit board; the support plate is a hard plastic plate.
The conductive soft board of the embodiment adopts a grid copper design mode, and needs to be made of materials as thin as possible, and the purpose of the conductive soft board is to increase the softness of the soft board and facilitate installation.
The conductive flexible board can be added with passive matching devices for improving signal quality, such as resistance, capacitance, inductance and the like.
The production mode of the probe on the conductive soft board comprises electroplating, printing, chemical etching and physical molding. The specific process is that the probe form is produced through printing and electroplating technology, at this time, the probe form is similar to a cylinder or a cube, then the probe tip is etched out through chemical microetching, at this time, the probe form is similar to a pyramid, at this time, the size of the probe tip is 20-30um, finally, physical plasticity is adopted, the probe tip is further reduced to 5-10um, the physical shaping method is that the probe is pricked on special plastic materials, and the probe tip is ground to the required size through repeated pricking.
On the high-speed channel, more attention is paid to impedance continuity, and signal reflection is reduced, so that the high-speed signal on the conductive flexible board of the device is not added with a via hole which is a discontinuous impedance structure, only an impedance control structure of a microstrip line is adopted, the microstrip line belongs to a uniform transmission line, and the impedance continuity is improved.
In the embodiment, a through hole is formed in the surface of the PCB, the high-speed connector is fixed on the support plate and is disposed in the through hole, and the conductive flexible board is located above the through hole. And connecting a cable on the high-speed connector, wherein the cable is led out from the bottom of the PCB.
As shown in fig. 6, in another implementation manner of this embodiment, the probe further includes a boss fixed on the supporting plate, the boss is fixed on the front surface of the supporting plate, the boss is located inside the trapezoid body of the conductive flexible board, and the upper bottom surface of the trapezoid body of the conductive flexible board is fixed on the end surface of the boss, so as to support the conductive flexible board, and achieve flatness control of the top probe.
In order to further ensure the stability and reliability of the probe, in another implementation manner of this embodiment, as shown in fig. 5, the probe further includes a reinforcing rib, where the reinforcing rib is fixed to the bottom of the supporting plate, so as to perform a better reinforcing and stabilizing function on the supporting plate.
In another implementation of this embodiment, the high-speed connector is a crimp-type connector. The high-speed connector which is connected through the crimping scheme is selected on the selection of the high-speed connector, the reliable connection of the signal pin on the conductive soft board and the pin of the connector can be realized through the screw at the mounting hole of the fixed connector, and the uncontrollable impedance brought by the traditional welding scheme at the welding point is avoided. In order to achieve reliable contact of signals, a supporting plate is designed at the bottom of the conductive soft board, mounting screws of the high-speed connector penetrate through the conductive soft board and the supporting plate, and finally the high-speed connector and the conductive soft board are fixed on the supporting plate.
In addition, if the chip needs to be externally provided with a matching device during test, the matching device can be directly placed on the slope surface of the soft board, and the device is placed closer to the chip, so that a better matching effect can be achieved.
The embodiment adopts FPC (flexible circuit board) soft board technology, realizes the interconnection on the 3D structure by utilizing the deformation of the soft board, and directly connects the signals on the soft board with the high-speed connector without passing through the rigid PCB. The impedance control of the flexible board is similar to that of a PCB, and the impedance control precision of the wiring is high. Since the flexible board can realize the bump on the structure, the needle of the MEMS (Micro-Electro-Mechanical System) can be designed to be very short, the probe belongs to a non-uniform transmission line structure, and the signal integrity is very affected by too long path. Here shortening the MEMS probe length greatly reduces the impact of impedance discontinuities in the probe.
In the wafer-level chip test process, a submount is usually added to realize the space conversion from small pitch to large pitch. Many vias are designed on the Substrate to ensure interconnection of signals from top layer to bottom layer, so control over impedance continuity is also very difficult. However, the flexible board can realize the manufacturing feasibility of small pitch in the process, the substrate in the vertical probe card is not needed to be used, and the influence caused by impedance discontinuity in the substrate is removed.
When in high-speed test, a high-speed signal is required to be connected to a testing instrument through a high-speed connector, the traditional technical scheme is that the high-speed signal on the flexible board is transmitted to the rigid PCB in a crimping or welding mode, then is connected to the high-speed connector through a wiring on the rigid PCB, and finally is transmitted to the testing instrument through a cable. The channel structure is complex, and the high-speed measurement quality of the signals is greatly affected. The high-speed wire of the embodiment does not pass through the rigid PCB, the flexible board is provided with a surface layer direct wiring structure, and the surface layer direct wiring structure is directly connected to the connector and connected with the test instrument through a cable, so that the electrical connection from the test chip bump to the test instrument is completed, and the 67GHz high-frequency test performance is realized. The high-speed wiring structure is particularly simple, and compared with a vertical probe card, the influence caused by impedance mismatch of some joints and substrates is reduced, so that the insertion loss and return loss performance of the channel are greatly improved.
For other low-speed and power signals, the signals can be fanned out from the soft board in a just-around combination mode, and the low-speed signals have no requirement on channel impedance, so that the wiring has no strict requirement, and the signals can be fanned out through surface layer wiring and inner layer wiring. The soft board is connected with signals of the PCB and power pins in a crimping or welding mode, the power and the signals are transmitted to the PCB, and finally the PCB is connected to a testing machine to realize power supply of the power and testing of low-speed signals.
The test results of the embodiment of the application are shown in fig. 7 and 8, and it can be seen that the insertion loss is particularly smooth, no obvious oscillation exists, and the return loss can reach less than-14.5 dB within 67 GHz. The performance of the channel is directly improved to 67GHz and above, and the performance of the wafer level high-speed test is improved. Therefore, chips which do not meet the requirements are screened out, and packaging and later engineering costs are saved.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (5)
1. A wafer level high speed signal testing apparatus, comprising: a PCB board, a supporting board and a conductive soft board,
the conductive soft board can be bent into a convex structure, so that the whole conductive soft board is a trapezoid;
the high-speed connector is fixed on the supporting plate, an electrical interface of the high-speed connector is electrically connected with the edge of the conductive soft board, the high-speed connector adopts a crimping connector, and a screw at a mounting hole of the crimping connector is fixed to realize reliable connection between a signal pin on the conductive soft board and a needle of the crimping connector;
the center of the PCB is provided with a through hole, the supporting plate is positioned at the bottom of the PCB, the high-speed connector is arranged in the through hole, the conductive soft board is positioned above the through hole, a cable is connected to the high-speed connector, and the cable is led out from the bottom of the PCB;
the upper bottom surface of the trapezoid body of the conductive soft board is provided with a needle implantation area, and the needle implantation area is implanted with MEMS probes for connecting with the bumps on the wafer.
2. The wafer level high-speed signal testing device of claim 1, wherein the electrically conductive flexible board is a flexible circuit board.
3. The wafer level high-speed signal testing device of claim 1, wherein the support plate is a rigid plastic plate.
4. The wafer level high-speed signal testing device according to claim 1, further comprising a stiffener fixed to a bottom of the support plate.
5. The wafer level high-speed signal testing device according to claim 1, further comprising a boss fixed to the front surface of the support plate such that the boss is located inside the trapezoid body of the conductive flexible board, and the upper bottom surface of the trapezoid body of the conductive flexible board is fixed to the end surface of the boss.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210683591.1A CN115128418B (en) | 2022-06-17 | 2022-06-17 | Wafer level high-speed signal testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210683591.1A CN115128418B (en) | 2022-06-17 | 2022-06-17 | Wafer level high-speed signal testing device |
Publications (2)
| Publication Number | Publication Date |
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| CN115128418A CN115128418A (en) | 2022-09-30 |
| CN115128418B true CN115128418B (en) | 2023-10-24 |
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| CN202210683591.1A Active CN115128418B (en) | 2022-06-17 | 2022-06-17 | Wafer level high-speed signal testing device |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5412329A (en) * | 1991-11-18 | 1995-05-02 | Tokyo Electron Yamanashi Limited | Probe card |
| CN1450633A (en) * | 2002-03-14 | 2003-10-22 | 日本电气株式会社 | Semiconductor device |
| CN201382962Y (en) * | 2009-04-13 | 2010-01-13 | 旺矽科技股份有限公司 | Cantilever Probe Card |
| CN102759701A (en) * | 2011-04-28 | 2012-10-31 | 旺矽科技股份有限公司 | Integrated high-speed test module |
| CN202837349U (en) * | 2012-08-23 | 2013-03-27 | 旺矽科技股份有限公司 | High-speed module for wafer-level probe card and probe card using the high-speed module |
| CN108710009A (en) * | 2018-08-02 | 2018-10-26 | 上海泽丰半导体科技有限公司 | A kind of cantalever type probe card |
| CN209218453U (en) * | 2018-09-10 | 2019-08-06 | 上海泽丰半导体科技有限公司 | A kind of test board of ATE |
| JP3224967U (en) * | 2019-03-18 | 2020-02-06 | 中華精測科技股▲ふん▼有限公司Ｃｈｕｎｇｈｗａ Ｐｒｅｃｉｓｉｏｎ Ｔｅｓｔ Ｔｅｃｈ．Ｃｏ．，Ｌｔｄ | Probe card and its signal transfer module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007205960A (en) * | 2006-02-03 | 2007-08-16 | Tokyo Electron Ltd | Probe card and probe device |
| JP2012529007A (en) * | 2009-06-02 | 2012-11-15 | 東京エレクトロン株式会社 | Probe card |
| WO2010141316A1 (en) * | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit wafer probe diagnostic tool |
| US8264249B2 (en) * | 2009-08-02 | 2012-09-11 | Chunghwa Precision Test Tech. Co., Ltd. | Vertical probe card |
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2022
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Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5412329A (en) * | 1991-11-18 | 1995-05-02 | Tokyo Electron Yamanashi Limited | Probe card |
| CN1450633A (en) * | 2002-03-14 | 2003-10-22 | 日本电气株式会社 | Semiconductor device |
| CN201382962Y (en) * | 2009-04-13 | 2010-01-13 | 旺矽科技股份有限公司 | Cantilever Probe Card |
| CN102759701A (en) * | 2011-04-28 | 2012-10-31 | 旺矽科技股份有限公司 | Integrated high-speed test module |
| CN202837349U (en) * | 2012-08-23 | 2013-03-27 | 旺矽科技股份有限公司 | High-speed module for wafer-level probe card and probe card using the high-speed module |
| CN108710009A (en) * | 2018-08-02 | 2018-10-26 | 上海泽丰半导体科技有限公司 | A kind of cantalever type probe card |
| CN209218453U (en) * | 2018-09-10 | 2019-08-06 | 上海泽丰半导体科技有限公司 | A kind of test board of ATE |
| JP3224967U (en) * | 2019-03-18 | 2020-02-06 | 中華精測科技股▲ふん▼有限公司Ｃｈｕｎｇｈｗａ Ｐｒｅｃｉｓｉｏｎ Ｔｅｓｔ Ｔｅｃｈ．Ｃｏ．，Ｌｔｄ | Probe card and its signal transfer module |
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| Publication number | Publication date |
|---|---|
| CN115128418A (en) | 2022-09-30 |
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