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CN115086504A - Clock synchronization system and method for operating clock synchronization system - Google Patents

Clock synchronization system and method for operating clock synchronization system Download PDF

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Publication number
CN115086504A
CN115086504A CN202110274896.2A CN202110274896A CN115086504A CN 115086504 A CN115086504 A CN 115086504A CN 202110274896 A CN202110274896 A CN 202110274896A CN 115086504 A CN115086504 A CN 115086504A
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clock
count
circuit
slave circuit
signal
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韦伯霖
陈庆隆
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

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  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The clock synchronization system comprises a master control circuit and a slave circuit. The main control circuit comprises a first clock generator, a first input/output interface, a first communication interface and a first processor. The first clock generator generates a first clock signal. The first processor outputs the trigger signal through the first input/output interface, records the first clock count of the first clock generator, and outputs the first clock count from the first communication interface. The slave circuit comprises a second clock generator, a second input/output interface, a second communication interface and a second processor. The second clock generator generates a second clock signal. When the trigger signal is received, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.

Description

时钟同步系统及操作时钟同步系统的方法Clock synchronization system and method of operating the clock synchronization system

技术领域technical field

本发明涉及一种时钟同步系统，特别是一种能够使内部电路的操作时间同步的时钟同步系统。The present invention relates to a clock synchronization system, in particular to a clock synchronization system capable of synchronizing the operation time of internal circuits.

背景技术Background technique

在播放多媒体资料时，为了让影像中的动作与声音能够同步，音频文件和影像文件的播放通常会参考相同的时钟信号。在现有技术中，通常会利用系统级芯片(System onChip，SoC)来处理多媒体资料中的音频文件及影像文件，因此可以共用相同的时钟发生器，并接收同步的时钟发生器。When playing multimedia materials, in order to synchronize the action in the video with the sound, the playback of the audio file and the video file usually refers to the same clock signal. In the prior art, a system-on-chip (SoC) is usually used to process audio files and video files in multimedia data, so the same clock generator can be shared and synchronized clock generators can be received.

然而，随着使用者对于影像及声音的品质要求越来越高，在处理多媒体资料时，也常会使用不同的电路来分别对音频文件及影像文件做较为细致的处理。由于不同的电路会根据不同的时钟信号来操作，因此如何使两者的播放时间能够同步以确保影像与声音能够相匹配，就成为了有待解决的问题。However, as users have higher and higher requirements for the quality of video and audio, when processing multimedia data, different circuits are often used to separately process audio files and video files in a more detailed manner. Since different circuits operate according to different clock signals, how to synchronize the playback time of the two to ensure that the image and sound can be matched has become a problem to be solved.

发明内容SUMMARY OF THE INVENTION

本发明的一实施例提供一种时钟同步系统，时钟同步系统包括主控电路及从属电路。An embodiment of the present invention provides a clock synchronization system. The clock synchronization system includes a master control circuit and a slave circuit.

主控电路包括第一时钟发生器、第一输入输出接口、第一通信接口及第一处理器。第一时钟发生器产生第一时钟信号。在对时操作期间，第一处理器通过第一输入输出接口输出触发信号，同时记录第一时钟发生器的第一时钟计数，及将第一时钟计数自第一通信接口输出。The main control circuit includes a first clock generator, a first input and output interface, a first communication interface and a first processor. A first clock generator generates a first clock signal. During the time synchronization operation, the first processor outputs a trigger signal through the first input and output interface, simultaneously records the first clock count of the first clock generator, and outputs the first clock count from the first communication interface.

从属电路包括第二时钟发生器、第二输入输出接口、第二通信接口及第二处理器。第二时钟发生器产生第二时钟信号。第二输入输出接口耦接于第一输入输出接口，而第二通信接口耦接于第一通信接口。当自第二输入输出接口接收到触发信号时，第二处理器记录第二时钟发生器的第二时钟计数，及根据第一时钟计数及第二时钟计数计算第一时钟信号及第二时钟信号之间的时间差。The slave circuit includes a second clock generator, a second input-output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. The second input-output interface is coupled to the first input-output interface, and the second communication interface is coupled to the first communication interface. When receiving the trigger signal from the second I/O interface, the second processor records the second clock count of the second clock generator, and calculates the first clock signal and the second clock signal according to the first clock count and the second clock count time difference between.

本发明的另一实施例提供一种时钟同步系统的操作方法，时钟同步系统包括主控电路及从属电路，主控电路包括第一时钟发生器，从属电路包括第二时钟发生器Another embodiment of the present invention provides a method for operating a clock synchronization system, the clock synchronization system includes a master control circuit and a slave circuit, the master control circuit includes a first clock generator, and the slave circuit includes a second clock generator

时钟同步系统的操作方法包括第一时钟发生器产生第一时钟信号，第二时钟发生器产生第二时钟信号，主控电路输出触发信号至从属电路，在发出触发信号时，主控电路同时记录第一时钟发生器的第一时钟计数，主控电路将第一时钟计数输出至从属电路，当从属电路接收到触发信号时，从属电路记录第二时钟发生器的第二时钟计数，及从属电路根据第一时钟计数及第二时钟计数计算第一时钟信号及第二时钟信号之间的时间差。The operation method of the clock synchronization system includes that a first clock generator generates a first clock signal, a second clock generator generates a second clock signal, the master control circuit outputs a trigger signal to the slave circuit, and when the trigger signal is sent, the master control circuit simultaneously records The first clock count of the first clock generator, the master control circuit outputs the first clock count to the slave circuit, when the slave circuit receives the trigger signal, the slave circuit records the second clock count of the second clock generator, and the slave circuit The time difference between the first clock signal and the second clock signal is calculated according to the first clock count and the second clock count.

附图说明Description of drawings

图1是本发明一实施例的时钟同步系统的示意图；1 is a schematic diagram of a clock synchronization system according to an embodiment of the present invention;

图2是本发明另一实施例的时钟同步系统的示意图；2 is a schematic diagram of a clock synchronization system according to another embodiment of the present invention;

图3是本发明一实施例的时钟同步系统的操作方法流程图。FIG. 3 is a flowchart of an operation method of a clock synchronization system according to an embodiment of the present invention.

具体实施方式Detailed ways

图1是本发明一实施例的时钟同步系统100的示意图。时钟同步系统100包括主控电路110及从属电路120。在有些实施例中，主控电路110可以例如是电视内部的主控芯片，而从属电路120可以是用以处理特殊影像的辅助芯片(companion chip)。举例来说，主控电路110可以处理影像文件及音频文件。然而，主控电路110只能够处理解析度为4K的影像画面，因此若使用者希望能够有更高的画质，例如希望呈现解析度为8K的影像画面时，就需要利用从属电路120来处理。然而，在此情况下，音频文件仍然会由主控电路110处理，因此两者的内部时间必须能够同步，才能够确保对应的影像及音讯内容能够同步输出。FIG. 1 is a schematic diagram of a clock synchronization system 100 according to an embodiment of the present invention. The clock synchronization system 100 includes a master circuit 110 and a slave circuit 120 . In some embodiments, the master control circuit 110 may be, for example, a master control chip inside the TV, and the slave circuit 120 may be a companion chip for processing special images. For example, the main control circuit 110 can process video files and audio files. However, the main control circuit 110 can only process images with a resolution of 4K. Therefore, if the user wishes to have a higher image quality, for example, if he wishes to display an image with a resolution of 8K, the slave circuit 120 needs to be used for processing. . However, in this case, the audio file will still be processed by the main control circuit 110, so the internal time of the two must be synchronized to ensure that the corresponding video and audio content can be output synchronously.

主控电路110可包括时钟发生器112、输入输出接口114、通信接口116及处理器118。时钟发生器112可产生时钟信号CLK1，而处理器118则可根据时钟信号CLK1来进行操作。从属电路120可包括时钟发生器122、输入输出接口124、通信接口126及处理器128。时钟发生器122可产生时钟信号CLK2，而处理器128则可根据时钟信号CLK2来进行操作。输入输出接口124可耦接于输入输出接口114，而通信接口126可耦接于通信接口116。在有些实施例中，输入输出接口可以例如但不限于是通用型输入输出(General Purpose Input/Output，GPIO)，而通信接口116及126可以例如但不限于是通用串行总线接口(UniversalSerial Bus，USB)、集成电路总线(Inter-Integrated Circuit，I2C)接口或通用同步异步收发器(Universal Synchronous Asynchronous Receiver Transmitter，USART)接口。The main control circuit 110 may include a clock generator 112 , an input/output interface 114 , a communication interface 116 and a processor 118 . The clock generator 112 can generate the clock signal CLK1, and the processor 118 can operate according to the clock signal CLK1. Slave circuit 120 may include clock generator 122 , input-output interface 124 , communication interface 126 , and processor 128 . The clock generator 122 can generate the clock signal CLK2, and the processor 128 can operate according to the clock signal CLK2. The input-output interface 124 can be coupled to the input-output interface 114 , and the communication interface 126 can be coupled to the communication interface 116 . In some embodiments, the input and output interfaces may be, for example, but not limited to, general purpose input/output (GPIO), and the communication interfaces 116 and 126 may be, for example, but not limited to, universal serial bus interfaces (Universal Serial Bus, USB), integrated circuit bus (Inter-Integrated Circuit, I 2 C) interface or Universal Synchronous Asynchronous Receiver Transmitter (Universal Synchronous Asynchronous Receiver Transmitter, USART) interface.

在有些实施例中，主控电路110及从属电路120可以执行对时操作来计算两者所使用的时钟信号CLK1及CLK2之间的时间差，而从属电路120则可以根据时间差回推主控电路110的时间，使得两者所处理的多媒体档案可以在相同的时间点播放，达到影像与声音同步的效果。In some embodiments, the master circuit 110 and the slave circuit 120 can perform a time synchronization operation to calculate the time difference between the clock signals CLK1 and CLK2 used by the two, and the slave circuit 120 can push back the master circuit 110 according to the time difference. time, so that the multimedia files processed by the two can be played at the same time point to achieve the effect of synchronizing the image and the sound.

在有些实施例中，时钟发生器112可以在时钟信号CLK1的每个正边缘或每个负边缘将时钟计数递增，例如但不限于加1，来更新时钟计数(clock count)。也就是说，时钟计数CC1可以用来表示时钟信号CLK1的周期数，因此处理器118可以根据时钟计数CC1来判定内部时间。相似地，处理器128也根据时钟信号CLK2的时钟计数CC2来判断内部时间。然而，由于时钟信号CLK1及CLK2并未同步，因此处理器118的内部时间与处理器128的内部时间会有时间差。In some embodiments, the clock generator 112 may update the clock count by incrementing the clock count, such as but not limited to 1, at each positive edge or each negative edge of the clock signal CLK1. That is, the clock count CC1 can be used to represent the number of cycles of the clock signal CLK1, so the processor 118 can determine the internal time according to the clock count CC1. Similarly, the processor 128 also determines the internal time based on the clock count CC2 of the clock signal CLK2. However, since the clock signals CLK1 and CLK2 are not synchronized, there is a time difference between the internal time of the processor 118 and the internal time of the processor 128 .

在对时操作期间，处理器118可以通过输入输出接口114输出触发信号SIGTRG，同时记录时钟发生器112的时钟计数CC1，并且可以通过通信接口116将时钟计数CC1输出。处理器128则可以在自输入输出接口124接收到触发信号SIGTRG时，记录时钟发生器122的时钟计数CC2。在有些实施例中，处理器118可以通过下拉输入输出接口114电压的方式传送触发信号SIGTRG，因此当从属电路120感测到输入输出接口124的电压变化时，就可以立即记录当时的时钟计数CC2。也就是说，时钟计数CC1及时钟计数CC2会对应到相同或是非常接近的真实时间。During the timing operation, the processor 118 can output the trigger signal SIG TRG through the input-output interface 114 while recording the clock count CC1 of the clock generator 112 , and can output the clock count CC1 through the communication interface 116 . The processor 128 may record the clock count CC2 of the clock generator 122 when receiving the trigger signal SIG TRG from the input/output interface 124 . In some embodiments, the processor 118 can transmit the trigger signal SIG TRG by pulling down the voltage of the I/O interface 114, so when the slave circuit 120 senses the voltage change of the I/O interface 124, it can immediately record the current clock count CC2. That is, the clock count CC1 and the clock count CC2 correspond to the same or very close real time.

从属电路120可以根据时钟计数CC1及时钟计数CC2计算时钟信号CLK1及时钟信号CLK2之间的时间差。举例来说，当时钟计数CC1为100时，时钟计数CC2是250，此时处理器128可以将时钟计数CC2减去时钟计数CC1以计算出两者的时间差为150。如此一来，若处理器118将预计在第一播放时间播放的多媒体资料交由处理器128处理时，处理器128便可将第一播放时间加上时间差150以计算出处理器128在从属电路120中应播放该多媒体资料的第二播放时间。The slave circuit 120 may calculate the time difference between the clock signal CLK1 and the clock signal CLK2 according to the clock count CC1 and the clock count CC2. For example, when the clock count CC1 is 100 and the clock count CC2 is 250, the processor 128 may subtract the clock count CC1 from the clock count CC2 to calculate a time difference of 150. In this way, if the processor 118 passes the multimedia data expected to be played at the first playback time to the processor 128 for processing, the processor 128 can add the time difference 150 to the first playback time to calculate the value of the processor 128 in the slave circuit. In 120, the second play time of the multimedia material should be played.

由于时钟同步系统100中的从属电路120可以根据相同真实时间下时钟计数CC1及CC2计算出两者的时间差，因此在接收到主控电路110所传来的多媒体资料时，就能够推算出该多媒体资料对应于从属电路120的第二播放时间，因此可以确保主控电路110及从属电路120能够在相同的时间播放对应的多媒体资料，达到影像及声音同步的效果。Since the slave circuit 120 in the clock synchronization system 100 can calculate the time difference between the clock counts CC1 and CC2 under the same real time, when receiving the multimedia data from the master control circuit 110, it can calculate the multimedia data. The data corresponds to the second playback time of the slave circuit 120 , so it can be ensured that the master control circuit 110 and the slave circuit 120 can play the corresponding multimedia data at the same time to achieve the effect of synchronizing images and sounds.

在图1中，处理器128可在接收到触发信号SIGTRG时进入中断(Interrupt)模式，并在中断模式下自时钟发生器122读取时钟计数CC2。然而，在有些实施例中，若处理器128进入中断模式所需要的时间较长，就可能导致时钟计数CC1及CC2对应到不同的真实时间，使得主控电路110与从属电路120的同步效果不佳。在此情况下，从属电路120可以利用其他的硬件电路来感测触发信号SIGTRG，以在接收到触发信号SIGTRG时能够更加即时的反应。In FIG. 1 , the processor 128 may enter an Interrupt mode upon receiving the trigger signal SIG TRG , and read the clock count CC2 from the clock generator 122 in the interrupt mode. However, in some embodiments, if it takes a long time for the processor 128 to enter the interrupt mode, it may cause the clock counts CC1 and CC2 to correspond to different real times, so that the synchronization effect between the master control circuit 110 and the slave circuit 120 is not effective. good. In this case, the slave circuit 120 can use other hardware circuits to sense the trigger signal SIG TRG , so as to be able to react more immediately when the trigger signal SIG TRG is received.

图2是本发明另一实施例的时钟同步系统200的示意图。时钟同步系统100及时钟同步系统200具有相似的结构，并且可根据相似的原理操作，然而在从属电路220还可包括触发处理电路229。触发处理电路229可以感测触发信号SIGTRG的信号边缘，例如正边缘或负边缘，而当触发处理电路229感测到触发信号SIGTRG的信号边缘时，触发处理电路229就可以立即选取时钟发生器122的时钟计数CC2，而处理器228则可自触发处理电路229读取时钟计数CC2。由于从属电路220可以利用触发处理电路229立即地对触发信号SIGTRG作出应对，因此可确保时钟计数CC1及CC2能够对应到非常接近的真实时间。FIG. 2 is a schematic diagram of a clock synchronization system 200 according to another embodiment of the present invention. Clock synchronization system 100 and clock synchronization system 200 have similar structures and may operate according to similar principles, however, trigger processing circuit 229 may also be included in slave circuit 220 . The trigger processing circuit 229 can sense the signal edge of the trigger signal SIG TRG , such as a positive edge or a negative edge, and when the trigger processing circuit 229 senses the signal edge of the trigger signal SIG TRG , the trigger processing circuit 229 can immediately select the clock generation The clock count CC2 of the processor 122 is read, and the processor 228 can read the clock count CC2 from the trigger processing circuit 229 . Since the slave circuit 220 can immediately respond to the trigger signal SIG TRG with the trigger processing circuit 229, it is ensured that the clock counts CC1 and CC2 can correspond to very close real time.

图3是本发明一实施例的时钟同步系统100的操作方法300的流程图。方法300可包括步骤S310至S390。FIG. 3 is a flowchart of an operation method 300 of the clock synchronization system 100 according to an embodiment of the present invention. The method 300 may include steps S310 to S390.

S310：时钟发生器112产生时钟信号CLK1；S310: the clock generator 112 generates the clock signal CLK1;

S320：时钟发生器122产生时钟信号CLK2；S320: the clock generator 122 generates the clock signal CLK2;

S330：主控电路110输出触发信号SIGTRG至从属电路120；S330: the master control circuit 110 outputs the trigger signal SIG TRG to the slave circuit 120;

S332：在发出触发信号SIGTRG时，主控电路110同时记录时钟发生器112的时钟计数CC1；S332: when the trigger signal SIG TRG is sent, the main control circuit 110 simultaneously records the clock count CC1 of the clock generator 112;

S340：主控电路110将时钟计数CC1输出至从属电路120；S340: the master control circuit 110 outputs the clock count CC1 to the slave circuit 120;

S350：当从属电路120接收到触发信号SIGTRG时，从属电路120记录时钟发生器122的时钟计数CC2；S350: when the slave circuit 120 receives the trigger signal SIG TRG , the slave circuit 120 records the clock count CC2 of the clock generator 122;

S360：从属电路120根据时钟计数CC1及时钟计数CC2计算时钟信号CLK1及时钟信号CLK2之间的时间差Δt；S360: The slave circuit 120 calculates the time difference Δt between the clock signal CLK1 and the clock signal CLK2 according to the clock count CC1 and the clock count CC2;

S370：主控电路110产生对应于第一播放时间的多媒体资料；S370: The main control circuit 110 generates multimedia data corresponding to the first playback time;

S380：主控电路110将多媒体资料传送至从属电路120；S380: the master control circuit 110 transmits the multimedia data to the slave circuit 120;

S390：当从属电路120接收到多媒体资料时，从属电路120根据时间差及第一播放时间换算出多媒体资料对应于时钟发生器122的第二播放时间。S390: When the slave circuit 120 receives the multimedia data, the slave circuit 120 converts the multimedia data according to the time difference and the first play time to convert the multimedia data to the second play time corresponding to the clock generator 122.

通过方法300，时钟同步系统100中的从属电路120可以根据相同真实时间下时钟计数CC1及CC2计算出两者的时间差，因此在接收到主控电路110所传来的多媒体资料时，就能够推算出该多媒体资料对应于从属电路120的播放时间，因此可以确保主控电路110及从属电路120能够在相同的时间播放对应的多媒体资料，达到影像及声音同步的效果。此外，在有些实施例中，时钟同步系统200也可以通过方法300来操作。Through the method 300, the slave circuit 120 in the clock synchronization system 100 can calculate the time difference between the two clock counts CC1 and CC2 according to the same real time. Therefore, when receiving the multimedia data from the master control circuit 110, it can calculate the time difference. The multimedia data corresponds to the playback time of the slave circuit 120, so it can be ensured that the master control circuit 110 and the slave circuit 120 can play the corresponding multimedia data at the same time to achieve the effect of video and sound synchronization. Additionally, in some embodiments, the clock synchronization system 200 may also operate by the method 300 .

综上所述，本发明的实施例所提供的时钟同步系统及操作时钟同步系统的方法可以记录在相同或十分接近的真实时间点上，主控电路的时钟计数及从属电路的时钟计数，并计算出两者的时间差，以进行同步的操作。因此可以在主控电路及从属电路分别使用不同时钟发生器的情况下，同步地输出对应的多媒体资料，达到影像及声音能够同步的效果。To sum up, the clock synchronization system and the method for operating the clock synchronization system provided by the embodiments of the present invention can record the clock count of the master control circuit and the clock count of the slave circuit at the same or very close real time point, and Calculate the time difference between the two for synchronous operation. Therefore, when the master control circuit and the slave circuit use different clock generators respectively, the corresponding multimedia data can be output synchronously, so as to achieve the effect that the image and the sound can be synchronized.

以上所述仅为本发明的优选实施例，凡依本发明权利要求书所做的均等变化与修饰，均应属于本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

附图标记说明：Description of reference numbers:

100、200：时钟同步系统100, 200: Clock synchronization system

110：主控电路110: main control circuit

120、220：从属电路120, 220: Slave circuit

112、122：时钟发生器112, 122: Clock generator

114、124：输入输出接口114, 124: Input and output interface

116、126：通信接口116, 126: Communication interface

118、128、228：处理器118, 128, 228: processors

229：触发处理电路229: Trigger processing circuit

CLK1、CLK2：时钟信号CLK1, CLK2: clock signal

SIGTRG：触发信号SIG TRG : trigger signal

CC1、CC2：时钟计数CC1, CC2: Clock count

300：方法300: Method

S310至S390：步骤S310 to S390: Steps

Claims (10)

1. A clock synchronization system, comprising:
a master control circuit, comprising:
a first clock generator for generating a first clock signal;
a first input/output interface;
a first communication interface; and
a first processor for outputting a trigger signal through the first input/output interface during a clock-to-clock operation, simultaneously recording a first clock count of the first clock generator, and outputting the first clock count from the first communication interface; and
a slave circuit, comprising:
a second clock generator for generating a second clock signal;
a second input/output interface coupled to the first input/output interface;
a second communication interface coupled to the first communication interface; and
the second processor is used for recording a second clock count of the second clock generator when the trigger signal is received from the second input/output interface, and calculating a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
2. The clock synchronization system of claim 1, wherein:
the master control circuit is also used for generating multimedia data corresponding to a first playing time and transmitting the multimedia data to the slave circuit; and
the slave circuit is further configured to convert a second playing time of the multimedia data corresponding to the second clock generator according to the time difference and the first playing time when receiving the multimedia data.
3. The clock synchronization system of claim 2, wherein:
the second processor subtracting the first clock count from the second clock count to calculate the time difference; and
the second processor adds the first playing time to the time difference to calculate the second playing time.
4. The clock synchronization system of claim 1, wherein:
the first communication interface is a universal serial bus interface, and the second communication interface is a universal serial bus interface;
the first communication interface is an integrated circuit bus interface, and the second communication interface is an integrated circuit bus interface; or
The first communication interface is a universal synchronous asynchronous receiver/transmitter interface and the second communication interface is a universal synchronous asynchronous receiver/transmitter interface.
5. The clock synchronization system of claim 1, wherein the first input/output interface is a general purpose input/output interface and the second input/output interface is a general purpose input/output interface.
6. The clock synchronization system of claim 1, wherein:
the slave circuit further comprises a trigger processing circuit for sensing a signal edge of the trigger signal and selecting the second clock count of the second clock generator when the signal edge is sensed;
the second processor reads the second clock count from the trigger processing circuit; and
the signal edge is a positive edge or a negative edge.
7. The clock synchronization system of claim 1, wherein:
the second processor enters an interrupt mode upon receiving the trigger signal and reads the second clock count from the second clock generator in the interrupt mode.
8. A method of operating a clock synchronization system, the clock synchronization system comprising a master circuit and a slave circuit, the master circuit comprising a first clock generator, the slave circuit comprising a second clock generator, and the method comprising:
the first clock generator generates a first clock signal;
the second clock generator generates a second clock signal;
the master control circuit outputs a trigger signal to the slave circuit;
when the trigger signal is sent out, the main control circuit simultaneously records a first clock count of the first clock generator;
the master circuit outputting the first clock count to the slave circuit;
when the slave circuit receives the trigger signal, the slave circuit records a second clock count of the second clock generator; and
the slave circuit calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
9. The method of claim 8, further comprising:
the main control circuit generates a multimedia data corresponding to a first playing time;
the master circuit transmits the multimedia data to the slave circuit; and
when the slave circuit receives the multimedia data, the slave circuit converts a second playing time of the multimedia data corresponding to the second clock generator according to the time difference and the first playing time.
10. The method of claim 9, wherein:
the slave circuit calculating the time difference between the first clock signal and the second clock signal from the first clock count and the second clock count comprises the second processor subtracting the first clock count from the second clock count to calculate the time difference; and
when the slave circuit receives the multimedia data, the slave circuit converts the second playing time of the multimedia data corresponding to the second clock generator according to the time difference and the first playing time, and the second processor adds the first playing time to the time difference to calculate the second playing time.
CN202110274896.2A 2021-03-15 2021-03-15 Clock synchronization system and method for operating clock synchronization system Pending CN115086504A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109977056A (en) * 2017-12-26 2019-07-05 三星电子株式会社 Digital processing system, master chip and digital processing method
CN111147907A (en) * 2019-12-26 2020-05-12 深圳市优必选科技股份有限公司 Method, device and system for synchronously playing multiple intelligent terminals and intelligent terminal
CN112162591A (en) * 2020-10-30 2021-01-01 上海兆芯集成电路有限公司 Electronic device with multiple processors and synchronization method thereof
TWI720791B (en) * 2020-01-20 2021-03-01 大陸商南京深視光點科技有限公司 Global clock synchronization transmission method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109977056A (en) * 2017-12-26 2019-07-05 三星电子株式会社 Digital processing system, master chip and digital processing method
CN111147907A (en) * 2019-12-26 2020-05-12 深圳市优必选科技股份有限公司 Method, device and system for synchronously playing multiple intelligent terminals and intelligent terminal
TWI720791B (en) * 2020-01-20 2021-03-01 大陸商南京深視光點科技有限公司 Global clock synchronization transmission method
CN112162591A (en) * 2020-10-30 2021-01-01 上海兆芯集成电路有限公司 Electronic device with multiple processors and synchronization method thereof

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