CN115085745A - VDE-TER-based digital diversity communication system - Google Patents

Abstract

The invention discloses a digital diversity communication system based on VDE-TER, which is used for realizing ship-shore communication according to a VDES G1139 protocol. The transceivers of the communication system all provide various modulation modes (pi/4-QPSK and 16QAM), provide various communication bandwidths (100KHz and 25KHz), the transmission rate can reach 307.2kbps and 76.8kbps theoretically, and the communication modes can be switched at any time through an upper computer interface in the using process, and the performance of the receiver is improved by adopting the diversity reception technology so as to adapt to the communication requirements under different scenes. The invention carries out the design of a communication system based on the VDES protocol requirement, has the advantages of multiple modulation modes, selectable communication bandwidth, good performance index of a transceiver and the like, reduces the resource occupation by the FPGA design, and can bear the requirement of the communication service between VDES offshore ships and shore.

Description

A Digital Diversity Communication System Based on VDE-TER

technical field

The invention relates to the technical field of water communication, in particular to a digital diversity communication system based on VDE-TER.

Background technique

VDES is mainly used for automatic ship identification in the field of maritime mobile services. On the basis of retaining the AIS function of the original maritime communication system, the VDES system introduces the special application message (ASM) function and the broadband very high frequency data exchange function (VDE). ), which strengthens the communication capability of the surface ships, realizes the communication between ship-ship, ship-shore, ship-satellite and satellite-ground, and because it is a newly proposed protocol standard, in terms of communication between satellite and ship , reserved enough spectrum resources, and laid the foundation for the expansion of more services in the future. With the rapid development of modern information communication technology and radio technology, intelligence, integration and digitization are the current development directions of maritime radio communication. If the current channel of water communication is adjusted according to the VDES protocol, the pressure on the communication to transmit AIS data will be greatly reduced, the utilization rate of the frequency band and the communication capability can be improved, and the safety of ship navigation will be guaranteed to a greater extent. The application can be combined with the Beidou satellite navigation system, applied to smart ships or unmanned ships, real-time transmission and update of electronic chart display and information systems, and help ship traffic services and e-navigation strategies.

At present, South Africa's Stone Three is developing VDES terminal products, and has carried out the land performance measurement of VDE-TER and the compatibility test with AIS in conjunction with Canada; British CML Microsystems has developed VDES development kit VDES1000 based on software radio; Japan Wireless Co., Ltd. The company (JRC) carried out the research and development of the VDES shipborne prototype, and completed the point-to-point experiment and broadcast experiment; Beijing Kaidun Huanyu Co., Ltd. completed the development of the VDES base station hardware test platform and tested it at sea; Shanghai Yizhen Technology Co., Ltd. developed the VDES base station Test platform and conduct reception performance tests on water. In general, the international standards of VDES are basically dominated by foreign teams. There is no significant gap between relevant domestic institutions and universities in terms of VDES technology development and productization, but most products are still in the stage of development and testing.

As a communication system, the key technology of VDE-TER system is the research of signal modulation and demodulation, signal synchronization and other related technologies. In 2015, Zhu Wenlong studied the modulation and demodulation technology of 16QAM in VDE-TER in "Research on Modulation and Demodulation Algorithm and Implementation of VDES", and implemented it based on FPGA, and proposed to use it in VDE-TER. The possibility of the OFDM system; in 2018, Huang Jianlin proposed a carrier synchronization technology suitable for the VDE-TER system in "Research on VDE-TER Carrier Synchronization Technology", using a combination of frequency coarse synchronization and fine synchronization. In 2020, Zhao Ruxue applied the OFDM modulation system to the VDES system in "Research on OFDM Synchronization Technology Based on Training Sequence in VDES", and conducted related simulation and research on its synchronization technology; "Research on VDES Modulation and Demodulation" proposed a method based on software radio technology to realize 16QAM transceiver and processing in VDE-TER; Fan Jiahui proposed a VDE-TER in "Research on Frequency Offset Estimation and Phase Tracking Algorithm in VDES" The key algorithm for frequency offset estimation and phase tracking when receiving signals in medium 16QAM.

The existing VDE-TER communication system is still in the stage of R&D and testing, and there are very few professional VDES technology development boards, such as VDES1000, but they are expensive; most of the VDE-TER products in other R&D tests only implement the VDE-TER standard protocol. The required single modulation mode and single data rate cannot be switched between modulation modes and communication bandwidths in different channel environments; products with multi-rate and multi-modulation modes have problems such as excessive hardware resource occupation and large processing delay; the developed The product is generally a base station or a terminal. No system research and development has been carried out on the base station and terminal, and the performance of the developed communication system has not been compared with the performance required by the VDE-TER standard protocol, and it is not clear whether it meets the performance requirements of the protocol.

Therefore, there is currently a lack of a communication system capable of applying the VDE-TER standard protocol.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a digital diversity communication system based on VDE-TER, the communication system is used to realize the communication between ship and shore according to the VDES G1139 protocol.

In order to achieve the above object, the technical scheme of the present invention is: a digital diversity communication system based on VDE-TER, including a transmitter and a receiver; a set of digital diversity communication systems are respectively set on the terminal and the base station.

The transmitter consists of the transmitter link layer, the transmitter physical layer and the transmitter hardware equipment; the transmitter link layer is used to send data from the upper computer; the transmitter physical layer includes a RAM data buffer module, a 1/2 Turbo coding module, a 3 /4Turbo encoding module, 19.2ksps data framing module, 76.8ksps data framing module, first time base control module, second time base control module, modulation module, interpolation module and up-conversion module; the transmitter hardware equipment includes a serial Secondary connected DAC, amplifier and antenna.

After the transmitter link layer sends the data, the sent data enters the RAM data buffer module. The RAM data buffer module outputs two channels of data to the 1/2 Turbo coding module and the 3/4 Turbo coding module respectively. The outputs of the 1/2 Turbo coding module are respectively Access the 19.2ksps data framing module and the 76.8ksps data framing module, the output of the 19.2ksps data framing module is connected to the first time base control module, the output of the 76.8ksps data framing module is connected to the second time base control module, the first Both the first time base control module and the second time base control module are connected to the modulation module, and the output end of the modulation module is connected to the interpolation module and the up-conversion module in sequence.

The receiver consists of the receiver link layer, the receiver physical layer and the receiver hardware device; the receiver hardware device consists of dual receive antennas, low noise amplifiers, numerically controlled attenuators and ADC connected in sequence; the receiver physical layer consists of JESD204b Interface, first receiving channel, second receiving channel, pi/4-QPSK demodulation module, 16QAM demodulation module, 1/2Turbo decoding module and 3/4Turbo decoding module.

The receiver receives the signal through the dual receiving antennas, and the analog-to-digital information conversion is realized by the dual-channel ADC through the hardware equipment of the dual-channel low-noise amplifier and the digital attenuator; after passing through the JESD204b interface that communicates with the ADC, the received signal is divided into two parts. The two channels enter the first receiving channel and the second receiving channel respectively. After the corresponding signal processing, the two signals are superimposed. After the superposition, they enter the pi/4-QPSK demodulation module and the 16QAM demodulation module respectively for demodulation operation. The output of the pi/4-QPSK demodulation module is connected to the 1/2Turbo decoding module, the output of the 16QAM demodulation module is connected to the 3/4Turbo decoding module; the inputs of the 1/2Turbo decoding module and the 3/4Turbo decoding module enter the receiver chain The road layer is used as the upper computer to read data.

Further, the 1/2 Turbo coding module is composed of a first CRC calculation module, a first Turbo coding module and a first scrambling module connected in sequence, and performs CRC calculation, Turbo coding and scrambling operations on the delivered data respectively.

In the 1/4 Turbo coding module, the second CRC calculation module, the second Turbo coding module and the second scrambling module respectively perform CRC calculation, Turbo coding and scrambling operations on the transmitted data.

Further, the 19.2ksps data framing module and the 76.8ksps data framing module are both framing modules.

The framing module forms a complete frame according to the frame structure given by VDES and the other parts of the frame structure, that is, the rising and falling protection time, training sequence, Link ID and protection time specified by the VDES protocol. The data of a complete frame obtained by framing is passed to the next module.

According to different data rates, the length of a frame is different, and the framing module is divided into two channels to be implemented separately, namely the 19.2ksps data framing module and the 76.8ksps data framing module; the two data framing modules have the same structure and both contain two frame lengths. Twice the dual-port RAM and two ROMs, each RAM and ROM implement a modulation method for framing, the RAM implements the function of ping-pong RAM cache, and alternately stores the issued data according to one frame and one frame. It is continuously sent to the next-level data processing module. The ROM stores the synchronization sequence and the data used for the receiver to determine the modulation mode and other information. After being read from the ROM, the data read out from the ping-pong RAM is in accordance with the frame structure. Formed and sent to the next module.

Further, the first time base control module and the second time base control module are both time base control modules, and the time base control module is based on the relationship between the symbol rates and the rate of the clock, and according to the time slot counting method specified by the VDES protocol, The current time slot number and the current symbol position in a frame during the transmission process are given. The symbol position controls the address of the ping-pong RAM to read the data at the correct rate, which is convenient for the modulation module to determine the frame and time slot related data. Part of the processing and control; the time base control module set on the terminal needs to keep the time slot synchronized with the base station, so according to the reception and capture of the broadcast packet, the time slot number and the counter are set. and Doppler frequency shift, and continuously adjust the count of the current time slot to realize the synchronization of the time slot between the terminal and the base station.

Further, the outputs of the first time base control module and the second time base control module both enter the modulation module. After the data stream enters the modulation module, the modulation module performs different control on the data according to the current modulation mode and data rate. Constellation diagram, two-bit mapping pi/4-QPSK or four-bit mapping 16QAM is performed on the bit stream data to obtain I-channel and Q-channel two-channel signals.

Before the interpolation module, the rate of the I channel and the Q channel is 19.2ksps or 76.8ksps. When performing the interpolation operation, the FIR filter and the polyphase filter are used for design. The interpolation method is: the data rate mode of 19.2ksps and the The data rate mode of 76.8ksps shares FIR filters with interpolation multiples of 16 times, 5 times, and 4 times. The difference is that the data rate mode of 19.2ksps needs to go through one more FIR filter with 4 times of interpolation.

Further, in the receiver, the receiving channel includes a first receiving channel and a second receiving channel.

The receiving channel includes two processing links, namely 19.2ksps data processing link and 75.8ksps data processing link, which are adapted to 19.2ksps and 76.8ksps data for processing respectively, and the processing methods are the same.

The processing methods of the 19.2ksps data processing link and the 75.8ksps data processing link are as follows:

The signal is subjected to a digital down-conversion module. After the down-conversion, the signal is extracted by the extraction module. On the one hand, the power of the extracted signal is counted, and the current power value corresponds to the attenuation value of the numerical control attenuator. Adjustment; on the other hand, the extracted signal undergoes frequency offset correction, phase offset correction and bit synchronization processing, and after processing, pi/4-QPSK modulation or 16QAM modulation is performed to obtain the output of the receiving channel.

Beneficial effects:

1. The present invention proposes a VDE-TER digital diversity communication system based on the VDES communication protocol standard. The communication system is implemented based on FPGA and includes base stations and terminal equipment. The communication system is based on the VDES G1139 protocol for ship-shore communication. The transceivers of the communication system all provide a variety of modulation methods (pi/4-QPSK and 16QAM), and provide a variety of communication bandwidths (100KHz and 25KHz). The communication mode can be switched at any time through the host computer interface, and the technology of diversity reception is used to improve the performance of the receiver to meet the communication needs in different scenarios.

2. The present invention designs the communication system based on the requirements of the VDES protocol, and has the advantages of multiple modulation modes, selectable communication bandwidths, and good performance indicators of the transceiver, and the FPGA design reduces resource occupation and can carry VDES between ships and shores at sea needs of communication services.

3. The digital diversity communication system based on the VDE-TER standard protocol provided by the present invention, according to the VDES standard protocol, VDE-TER will use the VHF frequency band to transmit in three bandwidths of 25KHz, 50KHz and 100KHz. The modulation methods to be used are: pi/4-QPSK, 16QAM, 8PSK, etc. VDE-TER must select pi/4-QPSK modulation mode with 25KHz bandwidth, 16QAM modulation mode with 100KHz bandwidth and pi/4-QPSK modulation mode with 100KHz bandwidth, other modes are Optional mode. Therefore, the present invention provides three VDE-TER must-select modes. Compared with pi/4QPSK, 16QAM is more susceptible to noise, but its bandwidth occupancy rate is very small and the spectrum utilization rate is extremely high, which can be used under better channel conditions. Guarantee the throughput of the channel, select the bandwidth and modulation mode according to the channel environment, and realize the communication function of ship-to-ship and ship-to-shore data.

4. In the digital diversity communication system based on the VDE-TER standard protocol provided by the present invention, in order to improve the performance of the receiver of the communication system and reduce noise interference, the receiver of the communication system adopts the diversity receiving technology to realize the receiver signal under limited hardware resources. Dual-channel processing, and proposed a frequency offset correction and phase offset correction algorithm suitable for pi/4-QPSK and 16QAM at the same time, reducing the demand for hardware resources.

Description of drawings

Fig. 1 is a flow chart of physical layer data framing;

Figure 2 is a block diagram of the design and implementation of the VDE-TER transmitter;

3 is a schematic diagram of an interpolation module;

Fig. 4 is a block diagram of VDE-TER receiver design and implementation;

Figure 5(a) is a block diagram of the design and implementation of the 19.2ksps link of the receiving channel in the VDE-TER receiver;

Figure 5(b) is a block diagram of the design and implementation of the 76.8ksps link link of the receiving channel in the VDE-TER receiver;

Figure 6 is a schematic diagram of a phase-locked loop tracking frequency offset correction algorithm for pi/4-QPSK modulation;

Figure 7 is a schematic diagram of a sliding window fine frequency offset correction algorithm suitable for 16QAM modulation.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

As a digital communication system, the present invention mainly provides the functions of the physical layer in the VDES system, such as signal modulation and demodulation, signal encoding and decoding, etc., and completes the data exchange with the link layer, and realizes this digital communication system based on FPGA design. , including transmitter and receiver in function. For base station and terminal equipment, the design of transmitter and receiver is different. Next, the design and implementation method of transmitter and receiver are introduced respectively.

According to the requirements of the VDE-TER standard protocol, the physical layer part of the transmitter should be implemented according to the physical layer data framing flow chart in Figure 1. After the link layer sends the data, the data is first filled with 0s. After CRC calculation, Turbo After coding, scrambling, and modulation, the data is processed by other processing, and then transmitted through hardware devices such as amplifiers and antennas. According to the flow chart in Figure 1, the pi/4-QPSK modulation mode with 25KHz bandwidth and 16QAM with 100KHz bandwidth are simultaneously realized. Modulation mode and pi/4-QPSK modulation mode of 100KHz bandwidth, the transmitter of the present invention is designed and implemented as shown in FIG. 2 .

As shown in Figure 2, the function of the physical layer is implemented based on the FPGA. The data to be transmitted is sent to the physical layer by the host computer according to the interface protocol, and the end mark of the completion of a frame of data is given at the end, and the FPGA is sent to the FPGA at the same time. (such as the modulation mode and data rate of this transmission, etc.) and the control word required by the hardware chip (such as A/D, D/A chip, etc.).

The FPGA part first uses the dual-port RAM to buffer the data of one frame length, and controls the length of the data read from the RAM according to the control word of the mark modulation mode and data rate, and sends the data to the encoding module.

If it is pi/4-QPSK modulation, it is sent to the 1/2 Turbo coding module. Since there are two data rates to choose from in the pi/4-QPSK modulation mode, the data length of one frame is different, so it is encoded here. The module should adjust the length of the 1/2 Turbo encoding according to the flag modulation mode and the data rate control word issued by the upper layer, so as to realize the sharing of encoding modules for different data rates to save FPGA resources; if it is 16QAM modulation, it is sent to the 3/4 Turbo encoding module. In addition to Turbo coding, the coding module also implements CRC check and scrambling of data before and after Turbo coding according to the flow chart in FIG. 1 . Next, the information flow enters the framing module.

The main function of the framing module is to combine the transmitted data according to the frame structure given by VDES, and the other parts of the frame structure, that is, the rising and falling protection time, training sequence, Link ID and protection time (specified by the VDES protocol). The data of a complete frame is transmitted to the next module (the time base control module performs time slot control). Because the length of a frame is different for different data rates, the framing module is divided into two channels to be implemented separately. In the 19.2ksps data framing module, it includes two dual-port RAMs with twice the frame length and two ROMs. Each RAM and ROM implements a modulation method of framing, and the RAM implements the function of ping-pong RAM cache. One frame alternately stores the sent data. The purpose is to continuously send the data to the next-level data processing module. The ROM stores the synchronization sequence and the data used for the receiver to determine the modulation mode and other information, and reads from the ROM. After the output, the data read out from the ping-pong RAM is grouped according to the frame structure and sent to the next module.

In order to control the data rate, the time base control module is designed and implemented. This module gives the current position in the transmission process according to the relationship between the symbol rate and the clock rate, and according to the time slot counting method specified by the VDES protocol. The time slot number and the current symbol position in a frame, the symbol position controls the address of the ping-pong RAM to read the data at the correct rate, which is convenient for other modules (such as modulation modules) to process and control the frame and time slot related parts . And the design and implementation of the time base control module of the base station and the terminal are not exactly the same. Since the terminal needs to keep the time slot synchronized with the base station, it will set the time slot number and counter according to the reception and capture of the broadcast packet. Factors such as the frequency difference of the carrier and the Doppler frequency shift will also continuously adjust the count of the current time slot to realize the synchronization of the time slot between the terminal and the base station.

After the data stream enters the modulation module, the modulation module controls the data differently according to the current modulation mode and data rate, and performs two-bit mapping (pi/4-QPSK) or four-bit mapping (pi/4-QPSK) or four-bit mapping ( 16QAM) to obtain two signals of I road and Q road.

Before the interpolating module, the rate of I and Q is 19.2ksps or 76.8ksps, and the sampling rate of the D/A used on the hardware platform is 983.04MSa/s. In order to achieve rate matching, the digital signal needs to be interpolated before being processed by the DAC. When performing interpolation operations, FIR filters and polyphase filters can be used for design to achieve the purposes of shaping filtering, interpolation and anti-image filtering. The interpolation method is shown in Figure 3. The data rate mode of 19.2ksps and the data rate mode of 76.8ksps share FIR filters with interpolation multiples of 16 times, 5 times, and 4 times to save FPGA resources. The difference is 19.2ksps The data rate mode of 1 is subjected to one more FIR filter with 4x interpolation.

After a series of interpolations are performed on the data, since the data rate is already the same as the FPGA master clock rate, the multi-phase up-conversion method is adopted to perform 8-fold interpolation to obtain data matching the DAC rate. The upper layer configures the frequency control word and the phase accumulation word. After obtaining the sinusoidal signal, the signal is multiplied by the multiplier, and the real part of the signal is input to the DAC. After amplification by the power amplifier, the signal is transmitted through the antenna.

The receiver designed and implemented by the present invention is shown in Fig. 4. Through dual-channel diversity reception, three modes (pi/4-QPSK modulation mode with 25KHz bandwidth, 16QAM modulation mode with 100KHz bandwidth and 100KHz bandwidth pi/4-QPSK modulation mode) signal reception, and can adjust the signal mode according to the current power of the current signal to achieve rate adaptation.

First, the receiver receives the signal through dual antennas, and the analog-to-digital information conversion is realized by dual-channel ADC through the hardware device of dual-channel low-noise amplifier and numerically controlled attenuator. After passing through the JESD204b interface that communicates with the ADC, the received data is divided into two channels, which are divided into receiving channel 1 and receiving channel 2. The two channels of signals are superimposed after corresponding signal processing. The reason for using diversity is that if the phases of the two channels of signals are in phase At the same time, by superimposing the amplitude, the power value can be increased by 4 times, while the noise is only increased by 2 times the power superposition, so as to obtain a 3dB signal-to-noise ratio gain, and due to the use of dual antenna reception, it can also resist multipath fading.

In dual-channel reception, the signals of the dual channels are multiple copies of the same signal, and the processing methods are basically the same. Therefore, in terms of design and implementation, the signal processing part of the receiver of the present invention is mainly divided into two major modules, which are the receiving channel 1 and the Receive channel 2. Since the signal of the VDE-TER system is burst, the rate of the signal is unknown when the signal is received, so in order to adapt to the 19.2ksps and 76.8ksps signals, each channel is divided into two different data processing chains according to the rate. The data processing method between each link is basically the same, so the main part of the data processing is described by taking the 76.8ksps data processing link in the receiving channel 1 as an example. Figure 4 is the block diagram of the design and implementation of the VDE-TER receiver, Figure 5(a) is the block diagram of the design and implementation of the 19.2ksps link in the receiving channel in the VDE-TER receiver; Figure 5(b) is the receiving channel in the VDE-TER receiver 76.8ksps link link design and implementation block diagram.

In order to process the signal, firstly, the signal should be digitally down-converted to remove the carrier. The method is to use DDS to generate the carrier frequency signal. Real and imaginary parts. In order to realize the automatic gain control of the system, the power statistics of the signal are performed at the same time, and the current power value corresponds to the attenuation value of the numerically controlled attenuator to realize the real-time adjustment of the signal power. In order to facilitate signal processing, the signal rate is reduced by the decimation module (the decimation multiples of the FIR filters passed by the processing links of different data rates are different). There are 16 sampling points, and due to the influence of carrier frequency difference and Doppler frequency shift, the signal still has frequency offset, and then the signal is processed for frequency offset correction, phase offset correction and bit synchronization.

According to the standard protocol of VDE-TER, although the modulation methods of payload data are different in different modes, the synchronization sequence and the LINK ID identifying the information of this frame are all pi/4-QPSK modulation methods. When processing pi/4-QPSK modulation or 16QAM, part of the data buffer module, coarse frequency offset estimation module, synchronization sequence frequency offset compensation module and bit synchronization module can be shared, while the fine frequency offset estimation module is performed separately. Design and implementation.

Since the modulation mode of the training sequence is pi/4-QPSK modulation, the signal information of this modulation mode is correlated by the phase of the signal and not affected by the amplitude, so the data is firstly processed by amplitude normalization. When estimating the rough frequency offset of the signal, since the data of 27 training sequences should be taken at the same time for calculation and estimation, but the data is streaming, a new data will arrive every 100 clocks, so a dual-port RAM pair is used. The data is cached to facilitate subsequent fetching and calculation. The reason for using the delay cache RAM is that the processing cycle of the previous algorithm has exceeded 100 clocks when the fine frequency offset estimation is performed on the data. Therefore, the data is delayed and the processing cycle is extended. for 200 clocks.

According to the principle of selecting an optimal sampling point for each symbol, 27 received data are read out from the buffer RAM. Since the synchronization sequence is a double Barker code sequence, after a lot of simulations and actual tests, the coarse frequency offset estimation module adopts the double Barker code sequence. A low-complexity universal frequency offset estimation algorithm for codes. The specific method is as follows. It is now assumed that timing synchronization has been completed and the training sequence has been extracted by the receiver. According to the modulation rule of pi/4-QPSK, the synchronization sequence is denoted as t, t(i)=±1, and the training sequence after local modulation is expressed as

The training sequence received by the receiver is expressed as:

为信道引入的相偏，T表示符号周期，n(j)为信道噪声。where r represents the received training sequence, f _d represents the frequency offset,

is the phase offset introduced by the channel, T is the symbol period, and n(j) is the channel noise.

In VDE-TER communication, pi/4-QPSK is alternately mapped between star and square constellations. Therefore, the constellation map mapped to each bit of the 13-bit Barker code and its inverse code is different. To simplify the calculation, before operating on the training sequence, it is uniformly converted into a star constellation diagram. The way to convert is as simple as this:

The traditional double-Barker code frequency offset estimation algorithm needs to use the special data characteristics of the double-Barker code as inverse codes and good autocorrelation to obtain the phase difference separated by 13 points and then average to obtain the frequency offset estimate value. In order to simplify the calculation, The FPGA resource is saved, and the method has good generality. The invention proposes and realizes a low-complexity general frequency offset estimation algorithm based on double Barker codes. The specific method is to discard the last 3 groups in the 13 groups of Barker codes. Phase differences are averaged between the 2nd to 11th symbols and the 18th to 27th symbols in the training sequence. Since the local modulation phases of these two groups of symbols are inconsistent, the phase difference is first performed on the symbols with inconsistent phases in one group. Rotate to form new two sets of double Barker codes as follows:

r _bark1 (k)=r _new (k)k=17,18,...,26

Then the phase difference separated by 16 points is

The estimated coarse frequency offset value can be obtained by averaging the phase differences separated by 16 points.

In the FPGA implementation, the division with 16 as the divisor can be directly implemented by shifting, and the two rotation phase operations can be combined into one operation, which greatly saves resources and computational complexity compared with the double Barker code frequency offset estimation algorithm. Spend.

After obtaining the rough frequency offset estimation value, the rough frequency offset correction is performed on the 27 symbol points received in the cache RAM, and since the signal has not been bit synchronized at this time, the starting position of the signal and the optimal sampling point are unknown, so Several coarse frequency offset values are cached with RAM.

In the bit synchronization module, in order to determine the starting position of the signal and the best sampling point, the received signal is continuously correlated with the local sequence. If the synchronization sequence is received, the correlation value will appear in a peak area. When the correlation value is higher than When the threshold value is set, the data is cached, and the value with the largest correlation result in the data above the threshold value is selected as the best sampling point, and the data is obtained from the cache RAM according to the rule of extracting a point for each symbol, and then Get the next complete packet of data. Such an algorithm realizes the bit synchronization of burst communication such as VDES. In order to obtain the initial phase offset introduced by the channel, the phase angle can be obtained directly from the cross-correlation result value. This result is the same as the coarse frequency offset value. Several values are cached in RAM, and after determining the optimal sampling point and signal start position point , the two parameter values can be provided to the fine frequency offset estimation module for further signal correction.

After the received signal is subjected to coarse frequency compensation and initial phase offset compensation, due to the influence of the accuracy of the coarse frequency compensation, there is usually a small frequency offset left. This part of the frequency offset will gradually rotate the constellation diagram, resulting in bit errors in signal judgment rate decreased. Therefore, the present invention adopts a phase-locked loop tracking frequency offset correction algorithm for pi/4-QPSK modulation, and a sliding window frequency offset correction algorithm for 16QAM modulation to compensate the signal for fine frequency offset/phase offset.

Firstly, the phase-locked loop tracking frequency offset correction algorithm used in pi/4-QPSK modulation is introduced. As shown in Figure 6, the algorithm is improved based on the DD phase offset estimation algorithm.

The first signal value after bit synchronization reads the parameters from the coarse frequency offset buffer RAM and the initial phase offset buffer RAM to perform coarse frequency offset phase offset correction, and then demodulate this point to obtain the standard position point on the constellation diagram. , calculate the phase angle deviation between the received signal value and the standard position value. The phase angle deviation phase_adj is caused by the residual frequency deviation. The phase_adj is tracked by the second-order loop filter for phase-locked loop tracking, as shown in the following formula:

phase_temp(n)=phase_temp(n-1)·exp(-j·C2·phase_adj(n))

phase_acc(n)=phase_temp(n)·exp(-1j·C1·phase_adj(n))

The phase_acc obtained each time is fed back and used for the frequency offset correction of the next signal point, thus realizing the frequency offset phase offset correction of the pi/4-QPSK modulated signal.

After recovering the LINK ID after the training sequence, the modulation mode and signal rate of the current signal can be determined. Each link gives the recovery result of the LINK ID to the upper computer, and determines whether the link continues to perform subsequent signal processing. , such as demodulation and decoding. If it is determined to be pi/4-QPSK modulation, continue to use the phase-locked loop tracking frequency offset correction algorithm to restore the payload data; if it is 16QAM modulation, use the sliding window frequency offset correction algorithm to restore the signal.

Next, the sliding window fine frequency offset correction algorithm suitable for 16QAM modulation is introduced. Suppose the signal after coarse frequency offset correction and initial phase offset correction is expressed as the following formula:

Among them, Δf _d ' is the small residual frequency offset, Δφ' is the small residual phase offset, the effect of the residual frequency offset on demodulation can be regarded as the effect of the residual phase offset caused by it on demodulation, so the residual phase offset can be expressed as

Δφ”=2πΔf _d 'mT+Δφ'

further have

r(m)=b(m)·e ^jΔφ″ +n(m)

Now the residual Δφ" is de-phased, that is, the fine frequency offset correction is realized.

The sliding window fine frequency offset correction algorithm suitable for 16QAM modulation is shown in Figure 4. After the bit synchronization is completed, the starting position of the valid signal is determined. When the first symbol after the training sequence is received, the sliding window fine frequency correction algorithm is performed. The offset correction algorithm, for the first received symbol, firstly compensate the coarse frequency offset and residual phase offset and perform demodulation mapping. The demodulation mapping value and 27 local training sequence groups are a local packet of data, and the window width is set to 28. The received signal also takes 27 received training sequences and the first symbol group as the received signal packet, and finds the residual phase offset according to the method of finding the initial phase offset. The specific method is to first normalize the data and reduce the amplitude pair. Calculate the impact, then cross-correlate the two packets of data and obtain the phase angle to obtain the residual phase offset, perform coarse frequency offset and residual phase offset compensation for the second received symbol, and then perform demodulation and mapping, and output to the next module. , and fed back to the front channel for local data packets of the sliding window group, and so on. Similar to making a window with a width of 28 symbols on a whole frame of data, sliding from the starting position of the synchronization sequence to the end of the data one by one, the demodulated signal is used as the local sequence in the window, and the received signal is correlated with the local sequence. Realize the de-phase offset processing of the data and keep the phase tracking state, so as to achieve the effect of fine frequency offset correction. It should be noted that when the received signal is a LINK ID, the demodulation mapping should be performed according to pi/4-QPSK. After the LINK ID is determined, if the payload data is 16QAM modulation, the payload data is demodulated and mapped according to 16QAM.

Fig.7 Sliding window fine frequency offset correction algorithm suitable for 16QAM modulation

At this point, each data link has completed the recovery of all data in a frame, and carries the basic information of the frame data, such as modulation mode and data rate. Before demodulating the data, it is also necessary to complete the dual-channel diversity reception. Consolidation of data. It is necessary to use the power statistics module of the power statistics value of the signal. The basis of this module is that the sum of the square of the signal amplitude of the I channel plus the square of the Q channel signal amplitude is proportional to the signal power. The algorithm for merging dual-channel data is based on the signal power as the weight, the superposition of the dual-channel I-channel signals to obtain the combined I-channel signal value, and the superposition of the dual-channel Q-channel signals to obtain the combined Q-channel signal value, using the new I-channel signal value. , The Q signal value completes the constellation map mapping and demodulation, further completes the decoding of the inverse process with the transmission chain, and restores the original bit data.

When the decoding is completed, the upper computer has read the current modulation mode and data rate, reads the data according to the specified frame length, and determines the information mode applicable to the current channel situation according to the current power statistics value. Mode adjustment to achieve adaptive information rate.

To sum up, the above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A digital diversity communication system based on VDE-TER, comprising a transmitter and a receiver; a set of digital diversity communication system is respectively arranged on the terminal and the base station;

the transmitter consists of a transmitter link layer, a transmitter physical layer and transmitter hardware equipment; the transmitter link layer is used for sending data by an upper computer; the physical layer of the transmitter comprises a RAM data buffer module, an 1/2Turbo coding module, a 3/4Turbo coding module, a 19.2ksps data framing module, a 76.8ksps data framing module, a first time base control module, a second time base control module, a modulation module, an interpolation module and an up-conversion module; the transmitter hardware equipment comprises a DAC, a power amplifier and an antenna which are connected in sequence;

the receiver consists of a receiver link layer, a receiver physical layer and receiver hardware equipment; the receiver hardware equipment consists of a double receiving antenna, a low noise amplifier, a numerical control attenuator and an ADC which are connected in sequence; the physical layer of the receiver is composed of a JESD204b interface, a first receiving channel, a second receiving channel, a pi/4-QPSK demodulation module, a 16QAM demodulation module, a 1/2Turbo decoding module and a 3/4Turbo decoding module.

2. The digital diversity communication system of claim 1, wherein after the transmitter link layer transmits data, the transmitted data enters a RAM data buffer module, the RAM data buffer module outputs two paths of data to access 1/2Turbo coding module and 3/4Turbo coding module respectively, the 1/2Turbo coding module outputs access 19.2ksps data framing module and 76.8ksps data framing module respectively, the 19.2ksps data framing module outputs connect a first time base control module, the 76.8ksps data framing module outputs access a second time base control module, the first time base control module and the second time base control module both access a modulation module, the modulation module output end connects an interpolation module and an up-conversion module in sequence;

the receiver receives signals through the double receiving antennas, and the conversion of analog-digital information is realized through the double-channel ADC through the double-channel low-noise amplifier and the hardware equipment of the digital control attenuator; after passing through a JESD204b interface communicated with an ADC, a received signal is divided into two paths, the two paths of signals respectively enter a first receiving channel and a second receiving channel, the two paths of signals are superposed after being processed by corresponding signals, and the superposed signals respectively enter a pi/4-QPSK demodulation module and a 16QAM demodulation module for demodulation operation, wherein the output of the pi/4-QPSK demodulation module is accessed to a 1/2Turbo decoding module, and the output of the 16QAM demodulation module is accessed to a 3/4Turbo decoding module; 1/2Turbo decoding module and 3/4Turbo decoding module input into receiver link layer as upper computer reading data.

3. The digital diversity communication system according to claim 1 or 2, wherein the 1/2Turbo coding module is composed of a first CRC calculation module, a first Turbo coding module and a first scrambling module connected in sequence, and performs CRC calculation, Turbo coding and scrambling operations on the transmitted data respectively;

the 3/4Turbo coding module is composed of a second CRC calculation module, a second Turbo coding module and a second scrambling module, and is used for performing CRC calculation, Turbo coding and scrambling operation on the transmitted data respectively.

4. The digital diversity communication system of claim 1 or 2, wherein the 19.2ksps data framing module and the 76.8ksps data framing module are both framing modules;

the framing module is used for forming a complete frame by the issued data and other parts of the frame structure, namely the rising and falling protection time, the training sequence, the LinkID and the protection time specified by the VDES protocol according to the frame structure given by the VDES, and transmitting the data of the complete frame obtained by framing to the next module;

according to different data rates and different frame lengths, the framing module is divided into two paths to be respectively realized, namely a 19.2ksps data framing module and a 76.8ksps data framing module; the two data framing modules have consistent structures and respectively comprise a double-port RAM and two ROMs, the length of each RAM is twice that of the corresponding frame, each RAM and each ROM realize framing of one modulation mode, the RAM realizes the function of ping-pong RAM cache, issued data are alternately stored according to one frame and one frame, the purpose is to continuously send the data to a next-level data processing module, the ROM stores synchronous sequences and data used for judging information such as modulation modes and the like by a receiving end, and after the data are read from the ROM, the data read from the ping-pong RAM and the data are well grouped according to the frame structure and sent to the next module.

5. The digital diversity communication system according to claim 4, wherein the first time base control module and the second time base control module are time base control modules, the time base control module gives the number of the current time slot and the symbol position in the current frame during the transmission process according to the relationship between the symbol rates and the rate of the clock and the time slot counting mode specified by the VDES protocol, the symbol position controls the address of the ping-pong RAM to read out the data at the correct rate, which facilitates the modulation module to process and control the frame and the time slot related part; the time base control module arranged on the terminal needs to keep the time slot synchronous with the base station, so the time slot number and the counter are counted according to the receiving and capturing condition of the broadcast packet, and the counting of the current time slot is continuously adjusted due to the frequency difference and the Doppler frequency shift of the carrier waves between the equipment, thereby realizing the synchronization of the time slot of the terminal and the base station.

6. The digital diversity communication system according to claim 1, 2 or 5, wherein the outputs of the first time base control module and the second time base control module enter the modulation module, after the data stream enters the modulation module, the modulation module performs different control on the data according to the current modulation mode and the data rate, and performs two-bit mapping pi/4-QPSK or four-bit mapping 16QAM on the bit stream data according to a constellation diagram specified by a protocol to obtain two-path signals of an I path and a Q path;

before the interpolation module, the I path and Q path rate is 19.2ksps or 76.8ksps, when the interpolation operation is carried out, the FIR filter and the polyphase filter are used for design, and the interpolation method is as follows: the 19.2ksps data rate mode shares FIR filters with interpolation multiples of 16, 5, and 4 with the 76.8ksps data rate mode, except that the 19.2ksps data rate mode has one more stage of a 4-fold interpolated FIR filter.

7. A digital diversity communication system according to claim 1 or 2, wherein in the receiver, the reception path comprises a first reception path and a second reception path;

the receiving channel comprises two processing links, namely a 19.2ksps data processing link and a 75.8ksps data processing link, and the two processing links are respectively suitable for processing 19.2ksps data and 76.8ksps data and have consistent processing modes;

the processing modes of the 19.2ksps data processing link and the 75.8ksps data processing link are as follows:

the signal is subjected to a digital down-conversion module, the down-converted signal is subjected to signal extraction through an extraction module, on one hand, power statistics is carried out on the extracted signal, and the real-time adjustment of the power of the signal is realized through the attenuation value of the numerical control attenuator corresponding to the current power value; and on the other hand, the extracted signal is subjected to frequency offset correction, phase offset correction and bit synchronization, and pi/4-QPSK modulation or 16QAM modulation is performed after the processing to obtain the output of the receiving channel.

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