CN115085514A - Intelligent power module - Google Patents
Intelligent power module Download PDFInfo
- Publication number
- CN115085514A CN115085514A CN202210878701.XA CN202210878701A CN115085514A CN 115085514 A CN115085514 A CN 115085514A CN 202210878701 A CN202210878701 A CN 202210878701A CN 115085514 A CN115085514 A CN 115085514A
- Authority
- CN
- China
- Prior art keywords
- circuit
- diode
- triode
- bridge arm
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 239000011241 protective layer Substances 0.000 claims abstract description 5
- 238000001914 filtration Methods 0.000 claims description 19
- 238000006073 displacement reaction Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 102100030393 G-patch domain and KOW motifs-containing protein Human genes 0.000 description 5
- 101150090280 MOS1 gene Proteins 0.000 description 5
- 101100401568 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MIC10 gene Proteins 0.000 description 5
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 5
- 239000004904 UV filter Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 101100461812 Arabidopsis thaliana NUP96 gene Proteins 0.000 description 3
- 101100262446 Arabidopsis thaliana UBA1 gene Proteins 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 101100508768 Arabidopsis thaliana IMPA3 gene Proteins 0.000 description 2
- 101100478187 Arabidopsis thaliana MOS4 gene Proteins 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 101001009694 Homo sapiens G-patch domain and KOW motifs-containing protein Proteins 0.000 description 1
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Power Conversion In General (AREA)
Abstract
The invention provides an intelligent power module, comprising: the device comprises a metal substrate layer, an insulating layer, a circuit layer, an HIVC (high-performance metal VC) driving logic circuit, a cache circuit, an upper bridge arm driving circuit, a lower bridge arm driving circuit, a switching tube assembly, a working protection circuit, a driving enabling circuit, a fault detection and output circuit and a protective layer, wherein the HIVC driving logic circuit is electrically connected with the upper bridge arm driving circuit and the lower bridge arm driving circuit respectively; the switch tube assembly comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode and a sixth triode which are connected in parallel, an upper bridge arm driving circuit is respectively connected with the first triode, the second triode and the third triode, and a lower bridge arm driving circuit is respectively connected with the fourth triode, the fifth triode and the sixth triode. The invention has small volume, simple process and high production efficiency.
Description
Technical Field
The invention relates to the technical field of intelligent power modules, in particular to an intelligent power module.
Background
Intelligent Power Module (IPM) is a Power-driven semiconductor product that combines Power electronics with integrated circuit HVIC technology. The power switch device and the high-voltage driving device are integrated inside the circuit, and fault detection circuits such as overvoltage, overcurrent and overheat are concealed in the circuit, so that the circuit is widely applied to systems such as frequency converters, welding machines and servo driving systems. The interior of the bridge is divided into an upper bridge arm, a lower bridge arm, a logic circuit, a protection circuit and the like, and the drive control and the protection feedback are realized through a logic chip of an integrated circuit. During work, the intelligent power module receives a control signal of the MCU to drive a subsequent circuit to work on the one hand, and sends a state detection signal of the system back to the MCU for processing on the other hand, so that the IPM working dynamics such as sudden overcurrent, overvoltage and overtemperature can be detected in real time, and the IPM can be protected and actuated in time.
With the rapid development of industry, the IPM intelligent power module is widely applied to various fields, especially in the field of white appliances, and with the trend of intellectualization and miniaturization of household products and the miniaturization of the volume design of the variable-frequency electric control main board, the traditional IPM intelligent power module is difficult to adapt to the development requirements.
The intelligent power module IPM used at present is generally composed of a freewheeling diode FRD, a triode IGBT/MOSFET and an HVIC, the number of devices is large, the required design area is relatively large, the cost is high, and particularly under the trend of application miniaturization of a terminal, the miniaturization requirement of an integrated device is higher and higher.
Therefore, the existing intelligent power module is overlarge in size, troublesome in production process, low in production efficiency and small in application range.
Disclosure of Invention
Aiming at the defects of the related technologies, the invention provides the intelligent power module which is small in size, low in manufacturing cost, simple in production process and convenient for improving the production efficiency.
In order to solve the above technical problem, an embodiment of the present invention provides an intelligent power module, including: the circuit comprises a metal substrate layer, an insulating layer arranged on the metal substrate layer, a circuit layer arranged on the insulating layer, an HIVC (high-voltage alternating-current) driving logic circuit, a cache circuit, an upper bridge arm driving circuit, a lower bridge arm driving circuit, a switch tube assembly, a working protection circuit, a driving enabling circuit, a fault detection and output circuit and a protective layer arranged on the circuit layer, wherein the HIVC driving logic circuit is respectively and electrically connected with the upper bridge arm driving circuit and the lower bridge arm driving circuit, and the upper bridge arm driving circuit and the lower bridge arm driving circuit are respectively and electrically connected with the switch tube assembly;
the switching tube assembly comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode and a sixth triode which are connected in parallel, the upper bridge arm driving circuit is respectively connected with the first triode, the second triode and the third triode, and the lower bridge arm driving circuit is respectively connected with the fourth triode, the fifth triode and the sixth triode.
Preferably, the HIVC driving logic circuit includes: the protection circuit is respectively electrically connected with the power circuit and the error reporting circuit, the interlocking circuit is respectively electrically connected with the upper bridge driving circuit and the lower bridge driving circuit, and the enabling circuit is respectively electrically connected with the upper bridge driving circuit, the protection circuit, the error reporting circuit and the lower bridge driving circuit.
Preferably, the FRD freewheel circuit includes: the first diode, the second diode, the third diode, the fourth diode, the fifth diode and the sixth diode are respectively connected with the fourth diode, the fifth diode and the sixth diode in series, the cathode of the first diode is connected with a power supply, the anode of the first diode is connected with the cathode of the fourth diode and outputs the output to a U phase, the anode of the fourth diode is connected with an output end NU, the cathode of the second diode is connected with the power supply, the anode of the second diode is connected with the cathode of the fifth diode and outputs the output to a V phase, the anode of the fifth diode is connected with the output end NV, the cathode of the third diode is connected with the power supply, the anode of the third diode is connected with the cathode of the sixth diode and outputs the output to a W phase, the anode of the sixth diode is connected to the output terminal NW.
Preferably, the first diode, the second diode, the third diode, the fourth diode, the fifth diode and the sixth diode are free-wheeling diodes FRD.
Preferably, the HIVC driving logic circuit further includes a high-voltage side driving circuit and a low-voltage side driving circuit.
Preferably, the high-side driver circuit includes: the circuit comprises a first Schmitt trigger, a first filtering unit, a first potential displacement circuit, a first NAND logic gate, a pulse production circuit, a filter circuit, a latch, a NOR logic gate, a second NAND logic gate, a third NAND logic gate, a first filtering circuit, a plurality of MOS tubes and a plurality of current limiting resistors.
Preferably, the plurality of MOS includes a first MOS, a second MOS, a third MOS and a fourth MOS, the output end of the pulse generation circuit is connected to the gates of the first MOS and the second MOS, the drain of the first MOS is connected to the input end of the filter circuit, the drain of the second MOS is connected to the first filter circuit, the output end of the filter circuit is connected to the input end S of the latch, and the output end of the first filter circuit is connected to the input end R of the latch.
Preferably, the plurality of limiting resistors includes a first current limiting resistor and a second current limiting resistor.
Preferably, the low-voltage side drive circuit includes: the output end of the first Schmitt trigger is connected with the input end of the second filter circuit, the output end of the second filter circuit is connected with the input end of the second potential displacement circuit, the output end of the second potential displacement circuit is connected with the input end of the dead zone interlocking circuit, the output end of the dead zone interlocking circuit is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the input end of the comparator, and the output end of the comparator is respectively connected with the grid electrodes of the fifth MOS and the sixth MOS.
Compared with the prior art, the insulation layer is arranged between the metal substrate layer and the circuit layer, so that the insulation effect is achieved, and the HIVC driving logic circuit, the cache circuit, the upper bridge arm driving circuit, the lower bridge arm driving circuit, the switching tube assembly, the work protection circuit, the drive enabling circuit and the fault detection and output circuit are integrated on the circuit layer, so that the power device is more miniaturized, the production process is simpler, and the production efficiency is convenient to improve; the protective layer arranged on the circuit layer is used for protecting internal components, the HIVC driving logic circuit is respectively and electrically connected with the upper bridge arm driving circuit and the lower bridge arm driving circuit, and the upper bridge arm driving circuit and the lower bridge arm driving circuit are respectively and electrically connected with the switch tube assembly; the upper bridge arm driving circuit is respectively connected with the first triode, the second triode and the third triode, the lower bridge arm driving circuit is respectively connected with the fourth triode, the fifth triode and the sixth triode, HVIC and 6 FRD are generated on the same silicon substrate through an SOI process, and 6 IGBT with large heat emission are installed on the module substrate, so that the heat dissipation effect is good, and the service life is convenient to improve.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings:
FIG. 1 is a circuit diagram of an intelligent power module of the present invention;
FIG. 2 is an internal circuit diagram of the smart power module of the present invention;
FIG. 3 is a schematic diagram of a smart power module according to the present invention;
FIG. 4 is a schematic diagram of the internal circuit of the high voltage driving HVIC of the SOI process of the present invention;
FIG. 5 is a schematic diagram of the internal structure of the smart power module of the present invention;
FIG. 6 is a block diagram of a smart power module of the present invention;
FIG. 7 is an assembled view of the smart power module of the present invention;
fig. 8 is a schematic diagram of the internal structure of the smart power module according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments described herein are specific embodiments of the present invention, are intended to be illustrative and exemplary of the concepts of the present invention, and should not be construed as limiting the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
Example one
Referring to fig. 1-8, the present invention provides an intelligent power module 100, including: the circuit comprises a metal substrate layer 603, an insulating layer 602 arranged on the metal substrate layer 603, a circuit layer 601 arranged on the insulating layer 602, an HIVC (high-voltage alternating-current) driving logic circuit 10, a cache circuit 11, an upper bridge arm driving circuit 12, a lower bridge arm driving circuit 13, a switch tube assembly 17, a work protection circuit 14, a driving enabling circuit 15, a fault detection and output circuit 16 and a protection layer 600 arranged on the circuit layer 601, wherein the HIVC driving logic circuit 10 is respectively and electrically connected with the upper bridge arm driving circuit 12 and the lower bridge arm driving circuit 13, and the upper bridge arm driving circuit 12 and the lower bridge arm driving circuit 13 are respectively and electrically connected with the switch tube assembly 17; the switch tube assembly 17 includes a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, a fifth triode Q5 and a sixth triode Q6, which are connected in parallel, the upper bridge arm driving circuit 12 is respectively connected with the first triode Q1, the second triode Q2 and the third triode Q3, and the lower bridge arm driving circuit 13 is respectively connected with the fourth triode Q4, the fifth triode Q5 and the sixth triode Q6.
Specifically, the insulating layer 602 is arranged between the metal substrate layer 603 and the circuit layer 601, so that an insulating effect is achieved, and the HIVC drive logic circuit 10, the cache circuit 11, the upper bridge arm drive circuit 12, the lower bridge arm drive circuit 13, the switch tube assembly 17, the work protection circuit 14, the drive enabling circuit 15 and the fault detection and output circuit 16 are integrally arranged on the circuit layer 601, so that the power device is more miniaturized, the production process is simpler, and the production efficiency is convenient to improve; the protective layer 600 arranged on the circuit layer 601 is used for protecting internal components, the HIVC driving logic circuit 10 is respectively and electrically connected with the upper bridge arm driving circuit 12 and the lower bridge arm driving circuit 13, and the upper bridge arm driving circuit 12 and the lower bridge arm driving circuit 13 are respectively and electrically connected with the switch tube assembly 17; the upper bridge arm driving circuit 12 is respectively connected with the first triode Q1, the second triode Q2 and the third triode Q3, the lower bridge arm driving circuit 13 is respectively connected with the fourth triode Q4, the fifth triode Q5 and the sixth triode Q6, HVIC and 6 FRD are generated on the same silicon substrate through an SOI (silicon on insulator) process, and 6 IGBTs which generate heat greatly are installed on the module substrate, so that the heat dissipation effect is good, and the service life is convenient to prolong.
Specifically, the HIVC driver logic circuit is an HIVC driver logic circuit of the intelligent power module, and is configured to receive and feed back a PWM input control signal of the MCU, and drive the upper bridge arm driver circuit 12 and the lower bridge arm driver circuit 13, so that the Q1, Q2, Q3, Q4, Q5, and Q6 switch tube assemblies in the switch tube assembly 17 work, thereby achieving the purpose of driving the motor.
The buffer circuit 11 is a buffer circuit for driving the PWM signals by the upper and lower bridge arms of the intelligent power module, and after receiving the MCU signals of the peripheral circuit, the buffer circuit outputs the signals to the corresponding switching tube driving circuits through filtering and amplification.
The upper bridge arm driving circuit 12 is a driving circuit of an upper bridge arm of the intelligent power module, and is included in a bootstrap circuit, an undervoltage protection circuit, a UPU driving circuit, a UPV driving circuit, and a UPW driving circuit.
The lower bridge arm driving circuit 13 is a driving circuit of a lower bridge arm of an intelligent power module, and directly drives the switching tubes of Q4, Q5 and Q6 after the signals of the 11 are received and are subjected to filtering and amplification processing.
The working protection circuit 14 is a working protection circuit of upper and lower bridge arms of the intelligent power module and is responsible for monitoring the working states of switching tubes of the modules Q1, Q2, Q3, Q4, Q5 and Q6, when a FAULT occurs and an ITRIP detects that a signal is abnormal, the signal is fed back to the MCU, action is immediately taken, the signal is cut off, and a FAULT signal has a high level and is converted into a low level state, so that the function of protecting the modules is achieved.
The driving enabling circuit 15 is an intelligent power module driving enabling circuit, has effective high level and is responsible for starting and shutting down the module execution function, when monitoring the working fault state of the modules Q1, Q2, Q3, Q4, Q5 and Q6, the driving enabling circuit can keep a low level state and disconnect a power supply to protect the whole module circuit, when the fault disappears and the internal RCIN recovery time reaches a design value, the high level state is recovered at this time, and the modules are electrified and enter a working preparation state;
the FAULT detection and output circuit 16 is an intelligent power module FAULT detection and output circuit, when the system detects that the voltage under-voltage protection (UV), over-temperature protection (OT), over-current protection (OC) and short-circuit protection (SC) signals are abnormal, the FAULT signal has a high level and is converted into a low level state, the signal is fed back to the MCU, action is immediately taken, the signal is cut off, and the module stops working.
The 17 switch tube assemblies are switch tubes of upper bridge arms Q1, Q2, Q3 and lower bridge arms Q4, Q5 and Q6 of the intelligent power module, and drive an external variable frequency motor after receiving a driving signal.
In this embodiment, the HIVC driving logic circuit 10 includes: power supply circuit, protection circuit, report wrong circuit, interlock circuit, upper bridge drive circuit, lower bridge drive circuit, enable circuit and FRD afterflow circuit 18, protection circuit respectively with power supply circuit reaches report wrong circuit electric connection, interlock circuit respectively with upper bridge drive circuit reaches lower bridge drive circuit electric connection, enable circuit respectively with upper bridge drive circuit protection circuit report wrong circuit and lower bridge drive circuit electric connection.
In the present embodiment, the FRD freewheel circuit 18 includes: a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5 and a sixth diode D6, wherein the first diode D1, the second diode D2 and the third diode D3 are respectively connected in series with the fourth diode D4, the fifth diode D5 and the sixth diode D6, a power source is connected to a cathode of the first diode D1, an anode of the first diode D1 is connected to a cathode of the fourth diode D4 for output to a U phase, an anode of the fourth diode D4 is connected to an output terminal NU, a cathode of the second diode D2 is connected to the power source, an anode of the second diode D2 is connected to a cathode of the fifth diode D5 for output to a V phase, an anode of the fifth diode D5 is connected to the output terminal NV 3, and a cathode of the third diode D3 is connected to the power source, an anode of the third diode D3 is connected to a cathode of the sixth diode D6, and outputs the result to phase W, and an anode of the sixth diode D6 is connected to an output NW.
In the present embodiment, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5 and the sixth diode D6 are all free-wheeling diodes FRD.
Specifically, the protection circuit is electrically connected with the power circuit and the error reporting circuit respectively, the interlock circuit is electrically connected with the upper bridge driving circuit and the lower bridge driving circuit respectively, and the enable circuit is electrically connected with the upper bridge driving circuit, the protection circuit, the error reporting circuit and the lower bridge driving circuit respectively. The upper bridge driving circuit comprises a bootstrap circuit, an upper bridge under-voltage protection circuit and a pulse circuit, wherein the pulse circuit is electrically connected with the enabling circuit, the bootstrap circuit, the upper bridge under-voltage protection circuit and the interlocking circuit respectively. The freewheeling diode circuit 18 includes D1, D2, D3, D4, D5, D6, D1, D2, D3 are upper bridge freewheeling tubes, D4, D5, D6 are lower bridge freewheeling tubes, the cathode of D1 is connected to the power supply DCBUS, the anode is connected to the cathode of D4 and outputs to the U phase, the anode of D4 is connected to the output terminal NU, the cathode of D2 is connected to the power supply DCBUS, the anode is connected to the cathode of D5 and outputs to the V phase, the anode of D5 is connected to the output terminal NV, the cathode of D3 is connected to the power supply DCBUS, the anode is connected to the cathode of D6 and outputs to the W phase, and the anode of D6 is connected to the output terminal NW. The freewheeling diode circuit 18 is not connected to other internal circuits, and is an independent freewheeling circuit.
The FRD freewheeling diode refers to D1-D6 and is integrated in an HVIC, wherein D1-3 is a Q1-3 freewheeling diode FRD of an upper bridge arm of the power IPM module, and D4-6 is a Q4-6 freewheeling diode FRD of a lower bridge arm of the power IPM module.
In this embodiment, the module 406 is an intelligent power module, and has an internal power portion and a driving control portion, where 407 is 6 freewheeling tubes of the power portion switch tube, 408 is 6 triode transistors of the power portion switch tube, and 409 is an HVIC of the driving control portion.
The module 401 is an intelligent power module, and includes an SOI technology HVIC402 portion and a power switch 403 portion.
The power switch tube 403 is a high-current power switch tube, Q1, Q2, Q3, Q4, Q5, Q6.
In this embodiment, the HIVC driver logic circuit 10 further includes a high-side driver circuit 326 and a low-side driver circuit.
In this embodiment, the high-side driving circuit 326 includes: the circuit comprises a first Schmitt trigger 300, a first filtering unit 301, a first potential shift circuit 302, a first NAND logic gate 303, a pulse generation circuit 304, a filter circuit 305, a latch 306, a NOR logic gate 307, a second NAND logic gate 308, a third NAND logic gate 309, a first filtering circuit 311, a plurality of MOS transistors and a plurality of current limiting resistors.
In this embodiment, the plurality of MOS includes a first MOS, a second MOS, a third MOS and a fourth MOS, the output terminal of the pulse generating circuit 304 is connected to the gates of the first MOS and the second MOS, the drain of the first MOS is connected to the input terminal of the filter circuit 305, the drain of the second MOS is connected to the first filter circuit 311, the output terminal of the filter circuit 305 is connected to the input terminal S of the latch 306, and the output terminal of the first filter circuit 311 is connected to the input terminal R of the latch 306.
In the present embodiment, the plurality of limiting resistors includes a first current limiting resistor RS1 and a second current limiting resistor RS 2.
Specifically, the high-voltage side driving circuit 326 includes a first schmitt trigger 300, a first filtering unit 301, a potential shift circuit 302, a nand logic gate 303, a pulse generating circuit 304, a dv/dt filter circuit 305, a latch 306, a nor logic gate 307, a nand logic gate 308, a nand logic gate 309, a UV filter circuit 311, and MOS1, MOS2, MOS3, MOS4, a current limiting resistor RS1, and RS 2. The input end of the schmitt trigger 300 is the input end of the high-voltage side driving circuit 326, and the output end of the first schmitt trigger 300 is interconnected with the input end of the first filtering unit 301; the output end of the first filter circuit 301 is interconnected with the input end of the potential shift circuit 302; the output end of the potential shift circuit 302 is interconnected with a first input terminal of the dead-zone interlock circuit 303 and a first input terminal of the dead-zone interlock circuit 308; the output terminal of the dead zone interlock circuit 308 is interconnected with the input terminal of the dead zone interlock circuit 303; the output end of the dead zone interlocking circuit 303 is interconnected with the input end of the pulse generating circuit 304;
the output end of the pulse generating circuit 304 is interconnected with the gates of the MOS1 and the MOS2, and the drain end of the MOS1 is interconnected with the input end of the dv/dt filter circuit 305; the drain terminal of MOS2 is interconnected to UV filter circuit 311, and the output terminal of dv/dt filter circuit 305 is interconnected to input terminal S of latch 306; the output of UV filter circuit 311 is interconnected with input R of latch 306;
the output Q of the latch 306 is interconnected with the input of the nor logic gate 307; the output end of the not logic gate 307 is interconnected with the gates of the MOS3 and the MOS 4.
In the transmission control process of signals, the mitt trigger 300 is used for filtering PWM control signals output by the peripheral main control board MCU and then stably outputting the PWM control signals to the first filter circuit 302 at the subsequent stage, the first filter circuit is used for filtering high-frequency and narrow-wave received control signals and inverting the control signals and outputting the control signals to the potential displacement circuit 302, and the potential displacement circuit is used for generating interference to interface voltage due to the direct current change when the amplitude of the coupled signals is large, correspondingly compensating the coupled signals and increasing the direct current level adjustment function, so that stable output of signals to the dead zone to generate the interlock circuits 303 and 308 can be realized; the pulse generating circuit 304 is used for outputting a high level signal output by the dead zone generating interlocking circuit 303 to the gates of the MOS1 and MOS2 tubes for driving conduction after receiving the high level signal, the gate and the source of the MOS tube are short-circuited to realize unidirectional conduction, and voltage is output to VB through the bootstrap resistors RS1 and RS 2; the DV/DT filter 305 is used for receiving drain voltages of MOS1 and MOS2 tubes, and carrying out filtering rectification so as to stabilize the voltages; the UV filter circuit 311 receives the voltage-divided point level signal of the bootstrap resistor to perform filtering rectification; the latch 306 is used for receiving signals of the filter 305 and the filter 311 for temporary storage, and finally synchronizing level signal output; the nor gate 307 is used for receiving the latch 306 signal, and controlling the MOS3 and MOS4 to drive the on condition by comparing the input heating high and low levels.
In this embodiment, the low-side driver circuit includes: the output end of the second schmitt trigger 312 is connected with the input end of the second filter circuit 313, the output end of the second filter circuit 313 is connected with the input end of the second potential displacement circuit 314, the output end of the second potential displacement circuit 314 is connected with the input end of the dead zone interlocking circuit 309, the output end of the dead zone interlocking circuit 309 is connected with the input end of the delay circuit 310, the output end of the delay circuit 310 is connected with the input end of the comparator 315, and the output end of the comparator 315 is respectively connected with the gates of the fifth MOS and the sixth MOS.
Specifically, the low-voltage side driver includes a mitt trigger 312, a second filter circuit 313, a potential shift circuit 314, a dead zone interlock circuit portion 309, a delay circuit 310, a comparator 315, a MOS5, and a MOS6 transistor. The input end of the first schmitt trigger 312 is a signal LIN input end, and the output end of the schmitt trigger 321 is interconnected with the input end of the filtering unit 313; the output end of the filter unit 313 is interconnected with the input end of the potential shift circuit 314, and the output end of the potential shift circuit 314 is interconnected with the input end of the dead zone generation interlocking circuit 309; the output of the dead-zone generating interlock circuit 309 is interconnected with the delay circuit 310; the output terminal of the delay circuit 310 is interconnected with the input terminal of the comparator 315; the output end of the comparator 315 is interconnected with the gates of the MOS5 and the MOS 6.
In the transmission control process of the signals, the mitt trigger 300 is used for filtering the PWM control signals output by the peripheral main control board MCU and then stably outputting the filtered PWM control signals to the second filtering circuit 313 at the rear stage, and the second filtering unit 313 is used for performing high-frequency and narrow-wave filtering on the received control signals, inverting the control signals, outputting the control signals to the potential displacement circuit 314, and outputting the control signals to the dead zone generation interlocking circuits 308 and 309. The delay unit 310 is configured to perform delay output on the control signal output by the dead zone generation interlock circuit 309, so as to avoid a short-circuit fault occurring in the power inverter bridge circuits MOS5 and MOS6 due to simultaneous conduction between the lower arm power transistor and the upper arm power transistor of the high-voltage side drive circuit.
The enable end of the low-voltage signal EN comprises a Mitt trigger 316, a third filter circuit 317 and an enable driving circuit 318; the high level is effective, and when the control system has a fault, the high level is converted into the low level for output.
The low-voltage signal ITRIP end comprises a Mitt trigger 319, a fourth filter circuit 320 and a potential displacement circuit 321; the low level is effective, and when the control system has a fault, the low level is converted into the high level to be output.
The low-voltage signal PFCTRIP end comprises a Mitt trigger 322, a fourth filter circuit 323 and a potential displacement circuit 324; the low level is effective, and when the control system has a fault, the low level is converted into the high level to be output.
The low-voltage signal VCC end comprises a Mitt trigger 325, a fifth filter circuit 325 and a power supply undervoltage protection circuit, and in a conventional drive control system, if a power supply is lower than 12.5V (a typical value), a module has undervoltage protection, a Fault control system triggers a Fault end, and the module stops working after low level output.
The low-voltage signal FAULT end comprises a Mitt trigger 328, a FAULT output circuit 329 and a sixth filter circuit 330; the high level is effective, and when the control system has a fault, the high level is converted into the low level for output.
The power section flow continuing tube 332 comprises 333 and 334 parts, namely an upper bridge flow continuing tube D1, D2 and D3 and a lower bridge flow continuing tube D4, D5 and D6.
In this embodiment, the module 505 is an intelligent power module, and is composed of a power portion 507 and a driving control portion 506, wherein the follow current tube of the power portion is integrated in the HVIC.
In this embodiment, the devices and FRDs inside the HVIC are placed on the circuit layer 601 of fig. 8, where the circuit layer is a silicon layer, also called active layer, which is the main circuit design layer to facilitate electrical node output. The insulating layer 602 is a buried oxide layer, and separates the electrical connection between the silicon layer and the metal substrate layer 600, which can bring advantages of small parasitic effect, high speed, low power consumption, high integration level, strong radiation resistance, and the like. The metal silicon substrate 603 is generally thicker, and its primary function is to provide mechanical support for the two layers above (i.e., the top silicon layer and the buried oxide layer).
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (9)
1. A smart power module, comprising: the device comprises a metal substrate layer, an insulating layer arranged on the metal substrate layer, a circuit layer arranged on the insulating layer, an HIVC (high-voltage alternating current) driving logic circuit, a cache circuit, an upper bridge arm driving circuit, a lower bridge arm driving circuit, a switch tube assembly, a working protection circuit, a driving enabling circuit, a fault detection and output circuit and a protective layer arranged on the circuit layer, wherein the HIVC driving logic circuit is respectively and electrically connected with the upper bridge arm driving circuit and the lower bridge arm driving circuit, and the upper bridge arm driving circuit and the lower bridge arm driving circuit are respectively and electrically connected with the switch tube assembly;
the switching tube assembly comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode and a sixth triode which are connected in parallel, the upper bridge arm driving circuit is respectively connected with the first triode, the second triode and the third triode, and the lower bridge arm driving circuit is respectively connected with the fourth triode, the fifth triode and the sixth triode.
2. The smart power module of claim 1, wherein the HIVC drive logic circuit comprises: power supply circuit, protection circuit, report wrong circuit, interlock circuit, upper bridge drive circuit, lower bridge drive circuit, enabling circuit and FRD afterflow circuit, protection circuit respectively with power supply circuit reaches report wrong circuit electric connection, interlock circuit respectively with upper bridge drive circuit reaches lower bridge drive circuit electric connection, enabling circuit respectively with upper bridge drive circuit protection circuit report wrong circuit and lower bridge drive circuit electric connection.
3. The smart power module of claim 2, wherein the FRD freewheeling circuit comprises: the first diode, the second diode, the third diode, the fourth diode, the fifth diode and the sixth diode are respectively connected with the fourth diode, the fifth diode and the sixth diode in series, the cathode of the first diode is connected with a power supply, the anode of the first diode is connected with the cathode of the fourth diode and outputs the output to a U phase, the anode of the fourth diode is connected with an output end NU, the cathode of the second diode is connected with the power supply, the anode of the second diode is connected with the cathode of the fifth diode and outputs the output to a V phase, the anode of the fifth diode is connected with the output end NV, the cathode of the third diode is connected with the power supply, the anode of the third diode is connected with the cathode of the sixth diode and outputs the output to a W phase, the anode of the sixth diode is connected to the output terminal NW.
4. The smart power module of claim 3, wherein the first diode, the second diode, the third diode, the fourth diode, the fifth diode, and the sixth diode are free-wheeling diodes (FRDs).
5. The smart power module of claim 1 wherein the HIVC driver logic circuit further comprises a high side driver circuit and a low side driver circuit.
6. The smart power module of claim 5, wherein the high side driver circuit comprises: the circuit comprises a first Schmitt trigger, a first filtering unit, a first potential displacement circuit, a first NAND logic gate, a pulse generation circuit, a filter circuit, a latch, a NOR logic gate, a second NAND logic gate, a third NAND logic gate, a first filtering circuit, a plurality of MOS tubes and a plurality of current-limiting resistors.
7. The smart power module of claim 6 wherein the plurality of MOS devices includes a first MOS device, a second MOS device, a third MOS device and a fourth MOS device, the output of the pulse generator circuit is connected to the gates of the first MOS device and the second MOS device, respectively, the drain of the first MOS device is connected to the input of the filter circuit, the drain of the second MOS device is connected to the first filter circuit, the output of the filter circuit is connected to the input S of the latch, and the output of the first filter circuit is connected to the input R of the latch.
8. The smart power module of claim 7, wherein the plurality of limiting resistors comprises a first current limiting resistor and a second current limiting resistor.
9. The smart power module of claim 5, wherein the low side driver circuit comprises: the output end of the first Schmitt trigger is connected with the input end of the second filter circuit, the output end of the second filter circuit is connected with the input end of the second potential displacement circuit, the output end of the second potential displacement circuit is connected with the input end of the dead zone interlocking circuit, the output end of the dead zone interlocking circuit is connected with the input end of the delay circuit, the output end of the delay circuit is connected with the input end of the comparator, and the output end of the comparator is respectively connected with the grid electrodes of the fifth MOS and the sixth MOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210878701.XA CN115085514A (en) | 2022-07-25 | 2022-07-25 | Intelligent power module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210878701.XA CN115085514A (en) | 2022-07-25 | 2022-07-25 | Intelligent power module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115085514A true CN115085514A (en) | 2022-09-20 |
Family
ID=83243380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210878701.XA Pending CN115085514A (en) | 2022-07-25 | 2022-07-25 | Intelligent power module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115085514A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116169633A (en) * | 2023-04-25 | 2023-05-26 | 广东汇芯半导体有限公司 | Current protection semiconductor circuit |
-
2022
- 2022-07-25 CN CN202210878701.XA patent/CN115085514A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116169633A (en) * | 2023-04-25 | 2023-05-26 | 广东汇芯半导体有限公司 | Current protection semiconductor circuit |
| CN116169633B (en) * | 2023-04-25 | 2023-07-25 | 广东汇芯半导体有限公司 | Current protection semiconductor circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8213146B2 (en) | Semiconductor power conversion apparatus | |
| US8791662B2 (en) | Power semiconductor module, electric-power conversion apparatus, and railway vehicle | |
| CN106104993B (en) | Driving circuits for power semiconductor elements | |
| US10651719B2 (en) | Method and control device for controlling a commutation process of a load current between switching modules | |
| JP6646870B2 (en) | Chopper device | |
| CN106688183A (en) | Short-circuit protection circuit for self-arc-extinguishing semiconductor components | |
| CN109510176B (en) | Intelligent power module driving protection circuit | |
| JP2014117112A (en) | Semiconductor control device, and power conversion equipment | |
| EP3029821B1 (en) | Semiconductor device and power conversion device | |
| JP2015032984A (en) | Device for driving semiconductor element, and power conversion device using the same | |
| CN113949250A (en) | A semiconductor device and its control method | |
| JP2018011467A (en) | Gate drive circuit for semiconductor switching element | |
| CN216625576U (en) | Semiconductor device with a plurality of transistors | |
| WO2014192327A1 (en) | Power conversion device and control method | |
| CN115085514A (en) | Intelligent power module | |
| JPH0799429A (en) | IGBT surge voltage suppression circuit and overcurrent cutoff circuit | |
| EP3694096A1 (en) | Three-level pulse width modulation technique for reducing semiconductor short circuit conduction loss | |
| CN112534720B (en) | Driving circuit | |
| CN111817597A (en) | an intelligent power module | |
| CN105409101B (en) | Three-level rectifier | |
| JP7537183B2 (en) | Semiconductor Device | |
| CN116169645A (en) | Intelligent power module | |
| CN218276457U (en) | Intelligent power module | |
| JP7373424B2 (en) | power converter | |
| US20220149839A1 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |