CN115083363B - Time sequence signal generating device and method, screen logic board and liquid crystal display device - Google Patents
Time sequence signal generating device and method, screen logic board and liquid crystal display device Download PDFInfo
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 10
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- 238000007781 pre-processing Methods 0.000 claims description 4
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application discloses a time sequence signal generating device and method, a screen logic board and a liquid crystal display device, and relates to the technical field of display. The device of the application comprises: the device comprises a receiving unit, a processing unit and a control unit; the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit; a receiving unit for receiving a first signal transmitted to a screen logic board, the first signal being a level signal containing line display data; the processing unit is used for processing the first signal to obtain a second signal after at least one function application is opened, wherein the second signal is a level signal emitted outwards by the screen logic board; and the control unit is used for controlling and generating a time sequence signal of the liquid crystal display panel according to the second signal.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a timing signal generating device and method, a screen logic board, and a liquid crystal display device.
Background
The screen logic board (Tcon) is also called a screen driving board and a central control board, and one of the most basic functions of Tcon is to make the panel normally light according to the Array substrate row driving (GATE DRIVER ON Array, GOA) design of the liquid crystal display panel. The GOA technology can use the original process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so that the driving circuit can replace an external integrated circuit (INTEGRATED CIRCUIT, IC) to finish the driving of the horizontal scanning line.
For example, the specific implementation process may be that a receiver (Rx) of Tcon is utilized to receive a Low-Voltage differential signal (Low-Voltage DIFFERENTIAL SIGNALING, LVDS) image data input signal (the input signal includes three signals of RGB data signal, clock signal and control signal) sent by a digital board, and after the processing of Tcon, the input signal is converted into an LVDS signal capable of driving a liquid crystal screen, and then the LVDS signal is directly sent to a display Driver IC by a transmitter (Tx) of Tcon, so as to further drive a control panel to normally display a picture.
Currently, in order to meet the design requirements of various products, manufacturers increase functional applications for adjusting the image quality effect, and in the process of testing the liquid crystal display panel, different functional applications are continuously turned on/off to achieve the purpose of optimizing the image display effect.
However, in view of low power consumption of Tcon, each functional application is controlled to be turned on or turned off by its corresponding clock, and under the influence of these different clocks, each display line of the panel may acquire display data in disorder, so that abnormal display of the panel screen may occur.
Disclosure of Invention
The application provides a time sequence signal generating device and method, a screen logic board and a liquid crystal display device, and mainly aims to optimize a time sequence method for setting a panel, and ensure that each display line of the panel can acquire correct display data even if the function with different clocks is applied, so that the normal display of a panel picture is ensured.
In order to achieve the above purpose, the present application mainly provides the following technical solutions:
the first aspect of the present application provides a timing signal generating apparatus, comprising:
The device comprises a receiving unit, a processing unit and a control unit; the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit;
a receiving unit for receiving a first signal transmitted to a screen logic board, the first signal being a level signal containing line display data;
The processing unit is used for processing the first signal to obtain a second signal after at least one function application is opened, wherein the second signal is a level signal emitted outwards by the screen logic board;
and the control unit is used for controlling and generating a time sequence signal of the liquid crystal display panel according to the second signal.
In some variant embodiments of the first aspect of the present application, the processing unit includes:
the triggering module is used for triggering and opening at least one function application;
A first constructing module, configured to increase at least one signal period before a first signal period in the first signal to obtain a third signal;
The processing module is used for processing the line display data carried in the third signal by utilizing a preset data arrangement form to obtain a processed third signal;
And the second construction module is used for constructing a fourth signal obtained by adding at least one signal period after the last signal period in the processed third signal, and taking the fourth signal as the second signal which is emitted outwards by the screen logic board.
In some variations of the first aspect of the present application, the first construction module includes:
a pre-processing sub-module for generating a wavefront signal using a virtual clock, the wavefront signal comprising at least one signal period;
the first construction submodule is used for receiving the first signal according to a rule of first-out of signal period, adding the wavefront signal to the front of the first signal period of the first signal and outputting a first target signal;
a first determination submodule for taking the first target signal as the third signal constructed based on the first signal.
In some variations of the first aspect of the present application, the first construction module further comprises:
The judging submodule is used for judging whether the clock domains corresponding to the wavefront signal and the first signal are the same or not;
and the adjusting sub-module is used for adjusting the duty ratio of the wave front signal when the clock domains corresponding to the wave front signal and the first signal are different, so that the wave front signal and the first signal keep consistent in a signal period.
In some variations of the first aspect of the present application, the second construction module includes:
a line buffering sub-module, configured to buffer the processed third signal;
A post-processing sub-module, configured to generate a post-signal according to a waveform in a signal period in the first signal, where the post-signal includes at least one signal period;
a second construction submodule, configured to add the post-signal to a last signal period of the first signal and output a second target signal;
A second determination submodule for taking the second target signal as the fourth signal constructed based on the first signal.
A second aspect of the present application provides a screen logic board comprising: the timing signal generating device as described above.
A third aspect of the present application provides a liquid crystal display device comprising: a screen logic board as described above.
A fourth aspect of the present application provides a timing signal generation method, applied to the timing signal generation apparatus as described above, comprising:
receiving a first signal transmitted to a screen logic board, wherein the first signal is a level signal containing row display data;
After at least one function application is opened, processing the first signal to obtain a second signal, wherein the second signal is a level signal emitted outwards by the screen logic board;
And controlling and generating a time sequence signal of the liquid crystal display panel according to the second signal.
In some modified embodiments of the fourth aspect of the present application, the processing the first signal to obtain the second signal after opening the at least one function application includes:
Triggering to open at least one function application;
Before a first signal period in the first signal, constructing an increase of at least one signal period to obtain a third signal;
Processing the line display data carried in the third signal by using a preset data arrangement form to obtain a processed third signal;
And after the last signal period in the processed third signals, constructing and adding at least one signal period to obtain fourth signals, and taking the fourth signals as the second signals which are outwards emitted by the screen logic board.
In some modified embodiments of the fourth aspect of the present application, the step of adding at least one signal period to the first signal period before the first signal period in the first signal to obtain a third signal includes:
generating a wavefront signal with a virtual clock, the wavefront signal comprising at least one signal period;
Receiving the first signal according to a rule of first receiving and first outputting of signal periods, and adding the wavefront signal to the first signal period of the first signal to output a first target signal;
the first target signal is taken as the third signal constructed based on the first signal.
In some variant embodiments of the fourth aspect of the present application, before said taking the first target signal as the third signal constructed based on the first signal, the method further comprises:
judging whether the clock domains corresponding to the wavefront signal and the first signal are the same or not;
If not, the duty ratio of the wave front signal is adjusted so that the wave front signal and the first signal keep consistent in waveform in one signal period.
In some modified embodiments of the fourth aspect of the present application, after the last signal period in the processed third signal, the step of adding at least one signal period to obtain a fourth signal includes:
Caching the processed third signal;
generating a wave-back signal according to a waveform in a signal period in the first signal, wherein the wave-back signal comprises at least one signal period;
Adding the wave-back signal into the last signal period of the first signal, and outputting a second target signal;
the second target signal is taken as the fourth signal constructed based on the first signal.
A fifth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a timing signal generation method as described above.
A sixth aspect of the present application provides an electronic device, comprising: the timing signal generation device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the timing signal generation method when executing the computer program.
By means of the technical scheme, the technical scheme provided by the application has at least the following advantages:
the application provides a time sequence signal generating device, a method, a screen logic board and a liquid crystal display device, wherein the device comprises: the device comprises a receiving unit, a processing unit and a control unit, wherein the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit. The receiving unit receives a first signal transmitted to the screen logic board, wherein the first signal is a level signal containing row display data, and after at least one function application is opened, the processing unit processes the first signal to obtain a second signal, and the second signal is a level signal transmitted by the screen logic board outwards, so that the control unit controls and generates a time sequence signal of the liquid crystal display panel according to the second signal.
According to the application, the timing synchronization of the panel timing and the timing synchronization of the Tx-transmitted second signal is realized according to the Tx-transmitted second signal of the Tcon as a reference for setting the panel timing, and for the functional application with different clocks, no matter how many the Tx-transmitted second signal is opened or closed, the number of signal periods delayed between the first signal and the second signal is only changed, so that each display line of the panel is not influenced to acquire correct display data, and the normal display of a panel picture is ensured. Compared with the prior art, the technical problem of abnormal display of the panel picture caused by the fact that the function applications with different clocks are opened or closed is solved.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is an exemplary Rx and Tx workflow diagram within a Tcon;
FIG. 2 is another exemplary Tcon internal Rx and Tx workflow diagram;
FIG. 3 is a schematic diagram of an exemplary Tcon internal Rx receiving a first signal;
FIG. 4 is a schematic diagram illustrating an abnormal display condition of a liquid crystal display panel;
FIG. 5 is a block diagram showing a timing signal generating apparatus according to an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a timing signal generated by a liquid crystal display panel according to a second signal control according to an embodiment of the present application;
FIG. 7 is a flowchart of a timing signal generating method according to an embodiment of the present application;
FIG. 8 is a block diagram showing another timing signal generating apparatus according to an embodiment of the present application;
Fig. 9 is a schematic diagram of a signal processing flow in Tcon provided in an embodiment of the present application;
FIG. 10 is a timing diagram of a plurality of GOAs according to an embodiment of the present application;
FIG. 11 is a signal diagram illustrating two different clock domains according to an embodiment of the present application;
fig. 12 is a flowchart of another timing signal generating method according to an embodiment of the application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
To meet different product design requirements of various manufacturers of liquid crystal display panels, various functional modules, such as digital gamma control (ACC), frame Rate Control (FRC), frame Overdrive (FOD), data Line Overdrive (LOD), etc., are provided in Tcon, and are functional applications for providing a debug image quality effect, and each functional application is controlled to be turned on or off by a respective corresponding clock in view of low power consumption of Tcon.
As the number of functional applications turned on or off varies, the number of signal periods delayed between a signal carrying the line display Data (DE) received by Rx (i.e., simply referred to as a first signal) and a signal carrying the DE transmitted by Tx (i.e., simply referred to as a second signal) varies. Specifically, the following is explained using the Tcon internal Rx and Tx workflow illustrated in FIGS. 1 and 2, respectively:
As in fig. 1, for example, 3 function applications are opened within Tcon: ACC, FRC and FOD. The high level representation of each of the first signal received by the Rx and the second signal transmitted outward by Tx after Tcon processing carries the DE, and an exemplary illustration: based on the 3 functional applications that are on, the first signal and the second signal are delayed by 3 signal periods, i.e. 3 DE.
As in fig. 2, for example, 4 function applications are opened within Tcon: ACC, FRC, FOD and LOD, one more function application is opened compared to fig. 1. The high level representation of each of the first signal received by the Rx and the second signal transmitted outward by Tx after Tcon processing carries the DE, and an exemplary illustration: based on the 4 functional applications that are on, the first signal and the second signal are delayed by 4 signal periods, i.e. 4 DE.
For fig. 1 and 2, it is first necessary to explain the DE carried in the signal, as illustrated in fig. 3, which is a schematic diagram of the signal carrying the DE. The high level in each signal period represents the carried DE, for example, the full high definition resolution of the panel is 1920×1080, and accordingly, in order to enable the whole panel to successfully display data, the data signal to be processed is the line display data containing 1080 lines of display data (i.e. 1080 DE), and each DE is the line display data composed of 1920 display points (for example, specifically 1920 pixel points), and the display parameters contained in each display point are obtained by overlapping red, green and blue color components.
And also it should be noted that, depending on what content services the function application specifically provides, how much Tcon is consumed for each function application, the opening/closing of the function application will affect the delay signal period between the first signal and the second signal for convenience of explanation, so that the exemplary illustration of opening either function application will add one signal period delay. That is, as shown in fig. 1 and 2, since one more function application is turned on, fig. 2 shows that one more signal period is delayed between the first signal and the second signal.
Based on the change of the number of delay signal periods between the first signal and the second signal caused by the change of the number of applications of the on/off function in conjunction with the workflow of Rx and Tx in Tcon shown in fig. 1 and 2, the inventor finds that if the first signal received by Rx according to Tcon is used as a reference for setting the timing of the panel, it will cause that each display line of the panel acquires display data to be disordered, resulting in abnormal display of the panel screen, and specifically, in conjunction with the abnormal display schematic diagram of the liquid crystal display panel illustrated in fig. 4, the explanation is as follows:
For example, if the timing signal of the liquid crystal display panel is generated according to the first signal control, the panel timing is set to be synchronous with the first signal timing. Illustratively, the high level of the first signal period of the set panel GOA timing signal corresponds to the 4 th DE of the first signal, which is fixed before the set panel timing is not changed (as shown in fig. 4).
And in connection with fig. 1 and 2, the explanation is aided, as shown in fig. 1, on the basis of opening 3 functional applications, such that a delay of 3 cycles is made between the first signal and the second signal, i.e. the first DE of the second signal is corresponding to the 4 th DE of the first signal. However, if one more function application is turned on, as shown in fig. 2, the first signal and the second signal are delayed by one more signal period, that is, by 4 signal periods, so that the first DE of the second signal corresponds to the 5 th DE of the first signal.
For the case of opening 4 function applications, as shown in fig. 4, since the correspondence between the high level of the first signal period of the panel GOA timing signal and the 4 th DE of the first signal is fixed, this will make the high level of the first signal period of the panel GOA timing signal unable to correspond to the first DE of the second signal, so that the first DE carried by the second signal cannot be acquired, and accordingly, the first display line of the panel will not correctly acquire the first line display data carried by the second signal, and will cause the display data to be acquired by each subsequent display line on the panel to be disordered, resulting in abnormal panel display. If each display line of the panel is allowed to acquire correct display data again, the setting panel timing must be frequently changed, which undoubtedly increases more panel debugging processing costs, and greatly reduces panel debugging efficiency although the panel screen display effect is corrected.
In order to solve the above problem of abnormal display of the panel screen, an embodiment of the present application provides a timing signal generating device, so as to implement an optimized timing method for setting the panel, where a block diagram of the device is shown in fig. 5, and the device includes: a receiving unit 11, a processing unit 12, and a control unit 13; the processing unit 12 is connected to an output end of the receiving unit 11, and the control unit 13 is connected to an output end of the processing unit 12.
The receiving unit 11 is configured to receive a first signal transmitted to the screen logic board, where the first signal is a high-low level signal including line display data; a processing unit 12, configured to process the first signal to obtain a second signal after at least one function application is opened, where the second signal is a high-low level signal emitted by the screen logic board; and a control unit 13 for controlling generation of a timing signal of the liquid crystal display panel according to the second signal.
In the embodiment of the application, the Rx of the Tcon receives a first signal transmitted from the outside, wherein the first signal is a high-low level signal containing DE, and the high level representation of the signal carries DE. The first signal is processed in the Tcon to obtain a second signal which is also a high-low level signal containing DE, and the first signal and the second signal carry different data contents of the row display data. After the Tcon processing, a second signal is directly transmitted to the outside by using Tx of the Tcon, for example, to a display Driver IC, so as to further drive the control panel to display the picture normally.
In the embodiment of the present application, the timing signals of the lcd panel are generated according to the second signal control, as shown in fig. 6, the embodiment of the present application exemplifies the generation of the timing signals of the lcd panel, and the following explanation is made with reference to the cases of turning on different functional applications shown in fig. 1 and 2:
in the embodiment of the present application, the timing signal of the liquid crystal display panel is generated according to the DE control included in the second signal, as shown in fig. 6, for example, the high level of the first signal period of the timing signal of the setting panel GOA corresponds to the first DE of the second signal transmitted by Tx, the correspondence is fixed before the timing of the setting panel is not changed,
Then, in connection with the case of opening different function applications shown in fig. 1 and 2, the function applications having different clocks should be dealt with, and as the number of open/close function applications is changed, the embodiment of the present application will always ensure that, regardless of the number of signal periods causing delay between the first signal and the second signal is changed: the high level of the first signal period of the panel GOA timing signal corresponds to the first DE of the second signal transmitted by Tx. Therefore, the first display line of the panel can accurately acquire the first DE carried by the second signal, and the second DE, the third DE and the like in the second signal are sequentially acquired one by one until each DE according to the panel time sequence, so that each display line of the panel can acquire correct display data, and normal display of a panel picture is ensured.
In the embodiment of the present application, based on a timing signal generating device shown in fig. 6, a timing method applied to an optimized setting panel executed on a screen logic board side is correspondingly obtained, and as shown in fig. 7, the specific implementation steps of the method include the following steps:
s201, receiving a first signal transmitted to a screen logic board, wherein the first signal is a high-low level signal containing row display data.
S202, after at least one function application is opened, the first signal is processed to obtain a second signal, and the second signal is a high-low level signal emitted outwards by the screen logic board.
S203, generating a time sequence signal of the liquid crystal display panel according to the second signal control.
In the foregoing, the embodiment of the present application provides a timing signal generating device and method, where the device provided by the embodiment of the present application includes: the device comprises a receiving unit, a processing unit and a control unit, wherein the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit. The receiving unit receives a first signal transmitted to the screen logic board, wherein the first signal is a high-low level signal containing row display data, and after at least one function application is opened, the processing unit processes the first signal to obtain a second signal, and the second signal is a high-low level signal transmitted by the screen logic board outwards, so that the control unit controls and generates a time sequence signal of the liquid crystal display panel according to the second signal.
Based on the timing signal generating device provided by the embodiment of the application, the correspondingly provided timing signal generating method comprises the following steps: according to the embodiment of the application, the second signal transmitted by Tx of Tcon is used as a reference for setting the panel time sequence, so that the time sequence synchronization of the panel time sequence and the second signal transmitted by Tx is realized, and for functional application with different clocks, no matter how many the second signal is opened or closed, the number of signal periods delayed between the first signal and the second signal is only changed, each display line of the panel is not influenced to acquire correct display data, and the normal display of a panel picture is ensured. Compared with the prior art, the technical problem of abnormal display of the panel picture caused by the fact that the function applications with different clocks are opened or closed is solved. And the time sequence of the panel is not required to be frequently changed, and the panel debugging efficiency is not influenced, so that the panel debugging accuracy and efficiency are considered.
In some modified embodiments, in order to accommodate the requirements of multiple manufacturers of liquid crystal display panels for different GOA timing, another timing signal generating device is provided according to an embodiment of the present application based on the device shown in fig. 5, and as shown in fig. 8, the following details are explained:
In the embodiment of the present application, the processing unit 12 includes: a trigger module 121, a first construction module 122, a processing module 123, and a second construction module 124;
Wherein, the triggering module 121 is configured to trigger to open at least one function application; a first constructing module 122, configured to increase at least one signal period before a first signal period in the first signal to obtain a third signal; a processing module 123, configured to process the line display data carried in the third signal by using a preset data arrangement form, so as to obtain a processed third signal; and the second construction module 124 is configured to increase at least one signal period after the last signal period in the processed third signals to obtain a fourth signal, and take the fourth signal as a second signal emitted by the screen logic board.
The embodiment of the application provides a plurality of functional modules such as ACC, FRC, FOD, LOD and the like in the Tcon, wherein the functional modules are used for providing functional applications for debugging image quality effects, and each functional application has respective corresponding clocks for controlling on and off due to the consideration of low power consumption of the Tcon. In order to meet the application requirements of various liquid crystal display panel manufacturers, which specific function application is opened and the number of the opened function applications can be preset in the Tcon.
It should be noted that, for Rx of Tcon to receive the first signal, some manufacturers of liquid crystal display panels require that the panel GOA timing is generated before the first signal, but some manufacturers of liquid crystal display panels require that the panel GOA timing is generated after the first signal. Therefore, in order to be compatible with the requirements of multiple liquid crystal display panel manufacturers for setting different GOA time sequences, the processing unit 12 is utilized to perform signal transformation and output the second signal in the process of processing the first signal, so that the embodiment of the application can still consider the requirements of setting different GOA time sequences by taking the second signal output by Tcon as a reference for setting the time sequences of the panels. Exemplary, the following is explained in detail in conjunction with the schematic diagram of the signal processing flow in Tcon shown in fig. 9 and the schematic diagram of the various GOA timing shown in fig. 10:
as shown in fig. 9, the first constructing module 122 may be a forward Line fifo function module (Front Line fifo), the processing module 123 may be a cell map function module (CELL MAPPING), and the second constructing module 124 may be a Line Buffer function module (Line Buffer).
Illustratively, the Rx of Tcon of the embodiment of the present application receives the first signal as a Video signal (Video DE), which carries the effective DE. The embodiment of the application is equivalent to adding at least one signal period (Front DE) to obtain a third signal by using the Front line fifo structure before its first period based on the Video DE.
The third signal is processed by CELL MAPPING in the middle, so as to adjust the display parameters of the display points in each DE to match with the display parameters required by the panel, specifically, adjust the color channels of each display point to match with the color channels displayed by the panel, which is equivalent to adjusting the display parameters contained in each display point at the pixel level.
And constructing and adding at least one signal period (Back DE) after the last period of the processed third signal by using the Line Buffer. Accordingly, after the above three processing of Video DE by Tcon, the resulting fourth signal is actually equivalent to including Front DE, video DE and Back DE.
Moreover, it should be further noted that, for Front DE and Back DE, the row display data represented by their respective high levels are null, i.e. do not carry valid row display data, so that for the fourth signal, although three portions including Video DE are included, the actual valid DE carried is still Video DE, so as to avoid panel display anomalies caused by panel GOA timing acquisition row display data disorder.
As shown in the various GOA timing diagrams of fig. 10, the embodiment of the present application uses the second signal output by Tcon as a reference for setting the panel timing, where the second signal is actually the fourth signal based on the Video DE structure mentioned above, and includes three parts of Front DE, video DE and Back DE. Accordingly, the embodiments of the present application are equivalent to generating the panel GOA timing based on the Front DE portion, the Video DE portion, or the Back DE portion, that is, the requirement that the panel GOA timing can be generated before, after, or both the first signal is satisfied.
And, as a further variant, the need to be able to generate the timing of the panel GOA just before or based on the first signal is met. The embodiment of the application can save the processing cost of constructing waveforms, namely only constructing a wave Front signal (Front DE), so that the second signal transmitted by Tx of Tcon is equivalent to two parts including the Front DE and the Video DE.
The need to be able to generate the panel GOA timing based on or after the first signal is only met. The embodiment of the application can also save the processing cost of some construction waveforms, namely, the method only needs to construct a post-wave signal (Back DE) based on the Video DE, so that the second signal transmitted by Tx of Tcon is equivalent to the two parts including the Video DE and the Back DE.
In the above, for different types of GOA timing setting requirements of each lcd panel manufacturer, different modification embodiments may be selected according to the embodiments of the present application, so as to better consider the GOA timing setting requirements of each lcd panel manufacturer.
In an embodiment of the present application, the first construction module 122 includes: a preprocessing submodule 1221, a first construction submodule 1222 and a first determination submodule 1223;
wherein the preprocessing sub-module 1221 is configured to generate a wavefront signal using the virtual clock, where the wavefront signal includes at least one signal period, and display data represented by a high level in each signal period is null; a first construction submodule 1222 for receiving the first signal according to the rule that the signal period is output first, and adding the wavefront signal to the first signal period of the first signal before outputting the first target signal; the first determining submodule 1223 is configured to take the first target signal as a third signal configured based on the first signal.
For the embodiment of the present application, the Panel GOA timing is generated before the first signal, and the embodiment of the present application is to key in a dummy clock (dummy CLK) before the Panel clock (Panel CLK) and generate a wavefront signal using the dummy clock, where the wavefront signal includes at least one signal period, and the display data represented by the high level is empty in each signal period.
Illustratively, the wavefront signal is "Front DE" shown in fig. 9, and the embodiment of the present application receives the first signal (i.e. Video DE) according to the rule that the signal period is received first and output the first target signal before adding the wavefront signal to the first signal period of the first signal, as "Front DE" + "VideoDE" shown in fig. 9.
In an embodiment of the present application, the first construction module 122 further includes: a decision submodule 1224 and an adjustment submodule 1225;
The judging sub-module 1224 is configured to judge whether clock domains corresponding to the wavefront signal and the first signal are the same; an adjustment submodule 1225 is configured to adjust a duty cycle of the wavefront signal when clock domains corresponding to the wavefront signal and the first signal are different, so that the wavefront signal and the first signal keep the waveform consistent in one signal period.
Further, it is also necessary for the wavefront signal and the first signal to determine whether their respective clock domains are the same, and if they are different, the duty cycle of the wavefront signal needs to be adjusted so that the wavefront signal and the first signal keep the waveform consistent in one signal period.
For example, as illustrated in fig. 11, signals of two different clock domains are explained based on fig. 9, because Video DE is in different local clock domains before and after entering Front line fifo, which results in inconsistent widths of Video DE before and after entering Front line fifo, it is necessary to make an adjustable duty cycle design for Front DE before Video DE to ensure consistency with Video DE after entering Front line fifo.
In an embodiment of the present application, the second construction module 124 includes: a line cache sub-module 1241, a post-processing sub-module 1242, a second construction sub-module 1243 and a second determination sub-module 1244;
The line buffering submodule 1241 is used for buffering the processed third signal; a post-processing sub-module 1242, configured to generate a post-signal according to a waveform in a signal period in the third signal, where the post-signal includes at least one signal period, and display data represented by a high level in each signal period is null; a second construction submodule 1243, configured to output a second target signal after adding the post signal to the last signal period of the first signal; the second determination submodule 1244 is configured to take the second target signal as a fourth signal which is constructed based on the first signal.
For the embodiment of the present application, in response to the requirement that some manufacturers of liquid crystal display panels require that the panel GAO timing is generated after the first signal, the embodiment of the present application generates the post-wave signal according to the waveform of each signal period of the processed third signal (i.e., the third signal processed by CELL MAPPING), where the post-wave signal includes at least one signal period, and the display data represented by the high level is null in each signal period.
Illustratively, the explanation is made in connection with fig. 9, the post signal being the "Back DE" shown in fig. 9, which is constructed in accordance with the waveform of the last signal period of the third signal after CELL MAPPING processing, and more than one signal period may be constructed.
Further, in combination with a timing signal generating apparatus shown in fig. 8, a timing signal generating method is performed by an application on the screen logic board side, and as shown in fig. 12, the method includes the following specific implementation steps:
S301, receiving a first signal transmitted to a screen logic board, wherein the first signal is a high-low level signal containing row display data.
S302, triggering to open at least one function application.
S303, before the first signal period in the first signal, at least one signal period is increased to obtain a third signal.
In an embodiment of the present application, in response to a requirement that some lcd panel manufacturers require that the panel GOA timing is generated before the first signal, at least one signal period needs to be added before the first signal to obtain the third signal, and the specific implementation method includes the following steps:
first, a wavefront signal is generated using a virtual clock, the wavefront signal comprising at least one signal period, the display data representing a high level being empty within each signal period.
And secondly, receiving the first signal according to a first-out rule of signal period first, and outputting a first target signal before adding the wave front signal to the first signal period of the first signal.
The first target signal is used as a third signal constructed based on the first signal.
In addition, it should be noted that it is necessary to determine whether the wavefront signal and the first signal respectively correspond to the same clock domain, and if they are different, the duty ratio of the wavefront signal needs to be adjusted so that the waveforms of the wavefront signal and the first signal are consistent in one signal period.
S304, processing the line display data carried in the third signal by using a preset data arrangement form to obtain a processed third signal.
S305, after the last signal period in the processed third signals, constructing a fourth signal by adding at least one signal period, and taking the fourth signal as a second signal emitted outwards by the screen logic board.
In the embodiment of the present application, in response to the requirement that some manufacturers of liquid crystal display panels require that the panel GAO timing is generated after the first signal, the embodiment of the present application needs to add at least one signal period after the third signal to obtain the fourth signal, and the specific implementation method includes the following steps:
first, the processed third signal is buffered.
And secondly, generating a wave-back signal according to the waveform in the signal period in the first signal, wherein the wave-back signal comprises at least one signal period, and the display data of the high level representation in each signal period is null.
And after adding the wave-back signal to the last signal period of the first signal, outputting a second target signal, and taking the second target signal as a fourth signal constructed based on the first signal.
S306, generating a time sequence signal of the liquid crystal display panel according to the second signal control.
In an embodiment of the present application, the second signal transmitted by Tx of Tcon, illustratively shown in fig. 9, comprises: the three parts of "Front DE" + "VideoDE" + "Back DE" are to be noted, and the "Front DE" and "Back DE" are each equivalent to a constructed signal waveform, but the row display data of the high level representation of the signal is empty, i.e. does not carry valid display data. Accordingly, the actual effective line display data carried by the second signal transmitted by Tx is still Video DE, so as to avoid abnormal panel display caused by the disorder of the line display data acquired by the panel GOA timing.
In summary, the embodiment of the present application provides a timing signal generating device and method, where the device provided by the embodiment of the present application includes: the device comprises a receiving unit, a processing unit and a control unit, wherein the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit. The receiving unit receives a first signal transmitted to the screen logic board, wherein the first signal is a high-low level signal containing row display data, and after at least one function application is opened, the processing unit processes the first signal to obtain a second signal, and the second signal is a high-low level signal transmitted by the screen logic board outwards, so that the control unit can control and generate a time sequence signal of the liquid crystal display panel according to the second signal.
The embodiment of the application takes the second signals output by the screen logic board as references for setting the panel time sequence, no matter which function application is opened/closed or the number of the function application is increased, the panel time sequence corresponds to the second signals transmitted by the screen logic board, even if the number of signal periods delayed between the first signals and the second signals is changed, the condition of disorder of the panel time sequence is avoided, and abnormal picture display is avoided.
In addition, in order to meet the diversity requirement of various liquid crystal display panel manufacturers on the panel GOA timing sequence, the embodiment of the application further performs waveform construction based on the first signal to obtain the second signal transmitted by Tx of Tcon, wherein the second signal is equivalent to the second signal and comprises three parts of a wavefront signal, a video signal and a rear signal, and based on some modified embodiments, the second signal is further enabled to comprise two parts of the wavefront signal and the video signal or is enabled to comprise two parts of the video signal and the rear signal, but only the video signal is still enabled to carry valid row display data, so that the requirement of the diversity of the panel GOA timing sequence is met, the fact that the row display data are acquired by the panel is accurate is ensured, and the panel display is still enabled to be normal is still ensured.
The time sequence signal generating device provided by the embodiment of the application comprises a processor and a memory, wherein the receiving unit, the processing unit, the control unit and the like are all stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can set one or more than one, the kernel parameters are adjusted to take the Tx transmitting signal of Tcon as a reference for setting panel time sequence, no matter which function application or how many are opened, the panel time sequence corresponds to DE contained in the Tx transmitting signal, abnormal picture display can not occur, the panel time sequence is not required to be frequently changed, and further the debugging efficiency is ensured.
The embodiment of the application provides a screen logic board, which comprises: the timing signal generating device as described above.
An embodiment of the present application provides a liquid crystal display device including: a screen logic board as described above.
Embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a timing signal generation method as described above.
The embodiment of the application provides electronic equipment, which comprises: the timing signal generation device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the timing signal generation method when executing the computer program.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, the device includes one or more processors (CPUs), memory, and a bus. The device may also include input/output interfaces, network interfaces, and the like.
The memory may include volatile memory, random Access Memory (RAM), and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (13)
1. A timing signal generating apparatus, the apparatus comprising: the device comprises a receiving unit, a processing unit and a control unit; the processing unit is connected with the output end of the receiving unit, and the control unit is connected with the output end of the processing unit;
a receiving unit for receiving a first signal transmitted to a screen logic board, the first signal being a level signal containing line display data;
The processing unit is used for processing the first signal to obtain a second signal after at least one function application is opened, wherein the second signal is a level signal emitted outwards by the screen logic board;
The processing unit includes: the triggering module is used for triggering and opening at least one function application; a first constructing module, configured to increase at least one signal period before a first signal period in the first signal to obtain a third signal; the processing module is used for processing the line display data carried in the third signal by utilizing a preset data arrangement form to obtain a processed third signal; the second construction module is used for constructing a fourth signal obtained by adding at least one signal period after the last signal period in the processed third signal, and taking the fourth signal as the second signal which is outwards emitted by the screen logic board;
and the control unit is used for controlling and generating a time sequence signal of the liquid crystal display panel according to the second signal.
2. The apparatus of claim 1, wherein the first construction module comprises:
a pre-processing sub-module for generating a wavefront signal using a virtual clock, the wavefront signal comprising at least one signal period;
the first construction submodule is used for receiving the first signal according to a rule of first-out of signal period, adding the wavefront signal to the front of the first signal period of the first signal and outputting a first target signal;
a first determination submodule for taking the first target signal as the third signal constructed based on the first signal.
3. The apparatus of claim 2, wherein the first construction module further comprises:
The judging submodule is used for judging whether the clock domains corresponding to the wavefront signal and the first signal are the same or not;
and the adjusting sub-module is used for adjusting the duty ratio of the wave front signal when the clock domains corresponding to the wave front signal and the first signal are different, so that the wave front signal and the first signal keep consistent in a signal period.
4. The apparatus of claim 1, wherein the second construction module comprises:
a line buffering sub-module, configured to buffer the processed third signal;
A post-processing sub-module, configured to generate a post-signal according to a waveform in a signal period in the first signal, where the post-signal includes at least one signal period;
a second construction submodule, configured to add the post-signal to a last signal period of the first signal and output a second target signal;
A second determination submodule for taking the second target signal as the fourth signal constructed based on the first signal.
5. A screen logic board, comprising: the timing signal generating apparatus according to any one of claims 1 to 4.
6. A liquid crystal display device, comprising: the screen logic of claim 5.
7. A timing signal generating method, characterized by being applied to the timing signal generating apparatus according to any one of claims 1 to 4, the method comprising:
receiving a first signal transmitted to a screen logic board, wherein the first signal is a level signal containing row display data;
After at least one function application is opened, processing the first signal to obtain a second signal, wherein the second signal is a level signal emitted outwards by the screen logic board;
And controlling and generating a time sequence signal of the liquid crystal display panel according to the second signal.
8. The method of claim 7, wherein processing the first signal to obtain a second signal after opening at least one functional application comprises:
Triggering to open at least one function application;
Before a first signal period in the first signal, constructing an increase of at least one signal period to obtain a third signal;
Processing the line display data carried in the third signal by using a preset data arrangement form to obtain a processed third signal;
And after the last signal period in the processed third signals, constructing and adding at least one signal period to obtain fourth signals, and taking the fourth signals as the second signals which are outwards emitted by the screen logic board.
9. The method of claim 8, wherein the constructing an increase of at least one signal period to obtain a third signal before a first signal period in the first signal comprises:
generating a wavefront signal with a virtual clock, the wavefront signal comprising at least one signal period;
Receiving the first signal according to a rule of first receiving and first outputting of signal periods, and adding the wavefront signal to the first signal period of the first signal to output a first target signal;
the first target signal is taken as the third signal constructed based on the first signal.
10. The method of claim 9, wherein prior to said configuring said first target signal as said third signal based on said first signal, said method further comprises:
judging whether the clock domains corresponding to the wavefront signal and the first signal are the same or not;
If not, the duty ratio of the wave front signal is adjusted so that the wave front signal and the first signal keep consistent in waveform in one signal period.
11. The method of claim 8, wherein said constructing a fourth signal by increasing at least one signal period after a last signal period in said processed third signal comprises:
Caching the processed third signal;
generating a wave-back signal according to a waveform in a signal period in the first signal, wherein the wave-back signal comprises at least one signal period;
Adding the wave-back signal into the last signal period of the first signal, and outputting a second target signal;
the second target signal is taken as the fourth signal constructed based on the first signal.
12. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the timing signal generation method according to any of claims 7-11.
13. An electronic device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the timing signal generation method according to any of claims 7-11 when the computer program is executed.
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