CN115050694A - Process method for improving hilly bulge defect - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000008569 process Effects 0.000 title claims abstract description 35
- 230000007547 defect Effects 0.000 title claims abstract description 29
- 229910052802 copper Inorganic materials 0.000 claims abstract description 45
- 239000010949 copper Substances 0.000 claims abstract description 45
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 238000005137 deposition process Methods 0.000 claims abstract description 4
- 238000009832 plasma treatment Methods 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 229910000077 silane Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000001125 extrusion Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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Abstract
Description
技术领域technical field
本发明涉及半导体技术领域，特别是涉及一种改善丘状凸起缺陷的工艺方法。The invention relates to the technical field of semiconductors, in particular to a process method for improving mound-shaped protrusion defects.
背景技术Background technique
随着集成电路制造工艺的发展以及关键尺寸的缩小，很多新的方法被运用到器件制造工艺中，用以改善器件性能，氮化硅因其有着良好的刻蚀选择性、良好的铜粘附性以及良好的阻挡铜在界面间的扩散等性质而被广泛应用。With the development of integrated circuit manufacturing process and the reduction of critical dimensions, many new methods have been applied to the device manufacturing process to improve device performance. Silicon nitride has good etch selectivity, good copper adhesion It is widely used because of its properties and good barrier to the diffusion of copper between interfaces.
目前为止的报道中，研究者们认为只有增加氮化硅对铜表面的粘附性才能更好地压制铜在界面间的扩散，从而大都着眼于铜CMP之后增加预处理步骤用来去掉由于铜裸露造成的氧化铜层，从而减小界面间的接触电阻并且防止铜在界面间的扩散现象，现行的65/55/40/28/22nm等工艺节点中顶层铜CMP之后都会沉积氮化硅薄膜作为刻蚀阻挡层，而在氮化硅薄膜沉积之后不可避免的都会出现大量丘状(hillock)缺陷，本质上，hillock缺陷造成的机理是由于为了满足更低的介电层造成的容抗，而采用了包裹铜的低介电常数的介电层，而低介电常数的介电层往往都有较为疏松的特性，疏松的介电层带来的副作用便是在高温或者其他外部因素下难以压制铜线的溢出而造成了hillock缺陷，随着工艺节点逐渐向下，到40nm节点铜hillock缺陷越发严重达到250000颗以上，而铜hillock缺陷一直存在着角落区比较薄弱的铜渗透现象，而铜渗透现象在工艺节点逐渐向下时由于铜线与铜线的距离变得越来越短，从而所表现出的造成电流击穿的风险会越来越大。In the reports so far, researchers believe that only by increasing the adhesion of silicon nitride to the copper surface can better suppress the diffusion of copper between the interfaces, so most of them focus on adding a pretreatment step after copper CMP to remove the copper The exposed copper oxide layer reduces the contact resistance between the interfaces and prevents the diffusion of copper between the interfaces. In the current process nodes such as 65/55/40/28/22nm, a silicon nitride film will be deposited on the top layer of copper after CMP. As an etching barrier layer, a large number of hillock defects will inevitably appear after the deposition of the silicon nitride film. However, a low-k dielectric layer wrapped with copper is used, and the low-k dielectric layer often has relatively loose characteristics. The side effect of the loose dielectric layer is that under high temperature or other external factors It is difficult to suppress the overflow of the copper wire and cause the hillock defect. As the process node gradually goes down, the copper hillock defect becomes more and more serious at the 40nm node, reaching more than 250,000 pieces. However, the copper hillock defect has always had a relatively weak copper penetration in the corner area. The copper penetration phenomenon presents an increasing risk of current breakdown as the process node goes down as the wire-to-copper distance becomes shorter and shorter.
发明内容SUMMARY OF THE INVENTION
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种改善丘状凸起缺陷的工艺方法，用于解决现有技术中铜CMP后形成的丘状缺陷导致电流击穿的风险增大的问题。In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a process method for improving the mound-shaped protrusion defect, which is used to solve the increased risk of current breakdown caused by the mound-shaped defect formed after copper CMP in the prior art. big problem.
为实现上述目的及其他相关目的，本发明提供一种改善丘状凸起缺陷的工艺方法，至少包括：In order to achieve the above-mentioned purpose and other related purposes, the present invention provides a process method for improving mound-shaped protrusion defects, including at least:
步骤一、提供表面由铜和介电质结构组成的半导体器件平面；Step 1, providing a semiconductor device plane whose surface is composed of copper and dielectric structures;
步骤二、在所述半导体器件平面沉积厚度为50～200埃、350℃工艺的第一氮化硅层作为铜溢出阻挡层；Step 2, depositing a first silicon nitride layer with a thickness of 50-200 angstroms and a 350°C process on the plane of the semiconductor device as a copper overflow blocking layer;
步骤三、对所述半导体器件平面进行退火预处理，增加所述铜溢出阻挡层与所述半导体器件平面中的铜表面的粘附性；Step 3, performing annealing pretreatment on the plane of the semiconductor device to increase the adhesion between the copper overflow barrier layer and the copper surface in the plane of the semiconductor device;
步骤四、在退火后的所述第一氮化硅层表面沉积第二氮化硅层，沉积工艺的温度为400℃。Step 4, depositing a second silicon nitride layer on the surface of the first silicon nitride layer after annealing, and the temperature of the deposition process is 400°C.
优选地，步骤二中的所述沉积所述第一氮化硅层的方法为：在1-5torr的压力下，通入氮气流量为1000～10000sccm，通入硅烷流量100～1000sccm，通入氨气流量100～1000sccm，温度为350℃的环境下进行等离子体处理。Preferably, the method for depositing the first silicon nitride layer in step 2 is as follows: under the pressure of 1-5torr, the flow rate of nitrogen gas is 1000-10000sccm, the flow rate of silane is 100-1000sccm, and ammonia is introduced The plasma treatment was performed in an environment with an air flow rate of 100 to 1000 sccm and a temperature of 350°C.
优选地，步骤二中所述等离子体处理的高频射频为100～1000瓦特。Preferably, the high-frequency radio frequency of the plasma treatment in step 2 is 100-1000 watts.
优选地，步骤二中所述等离子体处理的持续时间为1～20秒。Preferably, the duration of the plasma treatment in step 2 is 1-20 seconds.
优选地，步骤三中进行退火预处理的工艺为炉管工艺，退火温度为350℃。Preferably, the process of performing annealing pretreatment in step 3 is a furnace tube process, and the annealing temperature is 350°C.
优选地，步骤三中进行退火预处理的退火时间为30～60分钟。Preferably, the annealing time for the annealing pretreatment in step 3 is 30-60 minutes.
优选地，步骤三的所述退火预处理的作用是防止步骤四中沉积所述第二氮化硅层后造成丘状凸起的缺陷。Preferably, the function of the annealing pretreatment in step 3 is to prevent the defects of mound-shaped protrusions caused by the deposition of the second silicon nitride layer in step 4.
优选地，该方法应用于65nm、55nm、40nm、28nm以及22nm技术节点的工艺方法中。Preferably, the method is applied to the process methods of 65nm, 55nm, 40nm, 28nm and 22nm technology nodes.
如上所述，本发明的改善丘状凸起缺陷的工艺方法，具有以下有益效果：本发明通过对铜CMP之后增加低温350℃工艺的氮化硅薄膜以及350℃低温炉管工艺的方式大大改善铜表面受400℃氮化硅工艺影响挤压造成的丘状凸起缺陷。As mentioned above, the process method for improving the mound-shaped protrusion defect of the present invention has the following beneficial effects: the present invention greatly improves the silicon nitride film by adding a low temperature 350 ℃ process and a 350 ℃ low temperature furnace tube process after copper CMP. The copper surface is affected by the 400 ℃ silicon nitride process, and the mound-shaped protrusion defect is caused by extrusion.
附图说明Description of drawings
图1显示为本发明改善丘状凸起缺陷的工艺方法流程图。FIG. 1 shows a flow chart of a process method for improving mound-shaped protrusion defects of the present invention.
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。See Figure 1. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.
本发明提供一种改善丘状凸起缺陷的工艺方法，至少包括：The present invention provides a process method for improving mound-shaped protrusion defects, including at least:
步骤一、提供表面由铜和介电质结构组成的半导体器件平面；Step 1, providing a semiconductor device plane whose surface is composed of copper and dielectric structures;
步骤二、在所述半导体器件平面沉积厚度为50～200埃、350℃工艺的第一氮化硅层作为铜溢出阻挡层；Step 2, depositing a first silicon nitride layer with a thickness of 50-200 angstroms and a 350°C process on the plane of the semiconductor device as a copper overflow blocking layer;
本发明进一步地，本实施例的步骤二中的所述沉积所述第一氮化硅层的方法为：在1-5torr的压力下，通入氮气流量为1000～10000sccm，通入硅烷流量100～1000sccm，通入氨气流量100～1000sccm，温度为350℃的环境下进行等离子体处理。Further, the method for depositing the first silicon nitride layer in step 2 of this embodiment is: under the pressure of 1-5torr, the flow rate of nitrogen gas is 1000-10000sccm, and the flow rate of silane is 100 ～1000sccm, the flow rate of ammonia gas is 100～1000sccm, and the plasma treatment is performed in an environment with a temperature of 350 ℃.
本发明进一步地，本实施例的步骤二中所述等离子体处理的高频射频为100～1000瓦特。Further, in the present invention, the high-frequency radio frequency of the plasma treatment in step 2 of this embodiment is 100-1000 watts.
本发明进一步地，本实施例的步骤二中所述等离子体处理的持续时间为1～20秒。Further, in the present invention, the duration of the plasma treatment in step 2 of this embodiment is 1-20 seconds.
步骤二中在此铜与介电质结构的平面沉积厚度为50～200埃的350摄氏度工艺的氮化硅作为铜溢出阻挡层，其制作工艺细节包含但不限定为：在1-5torr(托，真空压强单位)的压力下，通入氮气流量约为1000～10000sccm(standard cubic centimeter perminute，每分钟立方厘米)，通入硅烷流量100～1000sccm，通入氨气流量100～1000sccm，温度约为350℃的环境下进行等离子体处理，其高频射频约为100～1000瓦特，持续时间约为1～20秒(以满足实际所需厚度设定时间)。In step 2, silicon nitride with a thickness of 50-200 angstroms is deposited on the plane of the copper and dielectric structures at a temperature of 350 degrees Celsius as a copper overflow blocking layer. Under the pressure of vacuum pressure unit), the flow rate of nitrogen gas is about 1000～10000sccm (standard cubic centimeter perminute, cubic centimeter per minute), the flow rate of silane is 100～1000sccm, the flow rate of ammonia gas is 100～1000sccm, and the temperature is about Plasma treatment is performed in an environment of 350°C, and the high-frequency radio frequency is about 100-1000 watts, and the duration is about 1-20 seconds (to meet the actual required thickness setting time).
步骤三、对所述半导体器件平面进行退火预处理，增加所述铜溢出阻挡层与所述半导体器件平面中的铜表面的粘附性；在铜溢出阻挡层后做350摄氏度炉管工艺30～60分钟用来使铜溢出阻挡层的氮化硅与铜表面具有更好地粘附性起到铜表面稳定作用。Step 3: Perform annealing pretreatment on the plane of the semiconductor device to increase the adhesion between the copper overflow barrier layer and the copper surface in the plane of the semiconductor device; after the copper overflow barrier layer is subjected to a furnace tube process of 350 degrees Celsius for 30- The 60 minutes were used to make the silicon nitride of the copper overflow barrier have better adhesion to the copper surface to stabilize the copper surface.
本发明进一步地，本实施例的步骤三中进行退火预处理的工艺为炉管工艺，退火温度为350℃。Further, in the third step of the present invention, the annealing pretreatment process is a furnace tube process, and the annealing temperature is 350°C.
本发明进一步地，本实施例的步骤三中进行退火预处理的退火时间为30～60分钟。Further, in the present invention, the annealing time for the annealing pretreatment in step 3 of this embodiment is 30-60 minutes.
本发明进一步地，本实施例的步骤三的所述退火预处理的作用是防止步骤四中沉积所述第二氮化硅层后造成丘状凸起的缺陷。In the present invention, further, the annealing pretreatment in step 3 of this embodiment is to prevent the defects of mound-shaped protrusions caused by the deposition of the second silicon nitride layer in step 4.
步骤四、在退火后的所述第一氮化硅层表面沉积第二氮化硅层，沉积工艺的温度为400℃。Step 4, depositing a second silicon nitride layer on the surface of the first silicon nitride layer after annealing, and the temperature of the deposition process is 400°C.
本发明进一步地，本实施例的该方法应用于65nm、55nm、40nm、28nm以及22nm技术节点的工艺方法中。Further, the method of this embodiment is applied to the process methods of 65nm, 55nm, 40nm, 28nm and 22nm technology nodes.
本发明是在氮化硅沉积前增加了几种前处理步骤，经过预沉积350摄氏度工艺氮化硅薄膜后将铜Hillock缺陷从基础水准250000颗以上降低到1001颗，再经过350摄氏度退火预处理后可将hillock defect降至0颗，效果明显。In the present invention, several pretreatment steps are added before the deposition of silicon nitride. After pre-depositing a silicon nitride film at a temperature of 350 degrees Celsius, the copper Hillock defects are reduced from more than 250,000 pieces to 1,001 pieces from the basic level, and then annealed at 350 degrees Celsius for pretreatment. Afterwards, the hillock defect can be reduced to 0, and the effect is obvious.
综上所述，本发明通过对铜CMP之后增加低温350℃工艺的氮化硅薄膜以及350℃低温炉管工艺的方式大大改善铜表面受400℃氮化硅工艺影响挤压造成的丘状凸起缺陷。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, the present invention greatly improves the mound-shaped protrusions on the copper surface caused by the extrusion of the copper surface affected by the 400°C silicon nitride process by adding a silicon nitride film with a low temperature 350°C process and a 350°C low temperature furnace tube process after copper CMP. defect. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.
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