CN115050663B - Gate-to-gate lateral short detection structure in FinFET process - Google Patents
Gate-to-gate lateral short detection structure in FinFET process Download PDFInfo
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Abstract
本申请涉及鳍式场效晶体管工艺的栅极间侧向短接检测结构。包括：鳍式有源区和浅沟槽隔离区沿第一方向交替排布；鳍式有源区的中部和鳍式有源区在第一方向上的两侧边缘分别设有一栅极结构，栅极结构沿第二方向延伸；浅沟槽隔离区的中部和浅沟槽隔离区在第一方向上的两侧边缘处分别设有一栅极结构，栅极结构沿第二方向延伸；第二方向与第一方向垂直；检测引线包括第一检测引线、第二检测引线、第三检测引线和第四检测引线；第一检测引线引出位于浅沟槽隔离区中部的栅极结构，第二检测引线引出位于浅沟槽隔离区两侧边缘的栅极结构，第三检测引线引出位于鳍式有源区两侧边缘的栅极结构，第四检测引线引出位于鳍式有源区中部的栅极结构。
The present application relates to a gate-to-gate lateral short detection structure of a fin field effect transistor process. The structure comprises: a fin active region and a shallow trench isolation region are alternately arranged along a first direction; a gate structure is respectively provided at the middle of the fin active region and at the two side edges of the fin active region in the first direction, and the gate structure extends along a second direction; a gate structure is respectively provided at the middle of the shallow trench isolation region and at the two side edges of the shallow trench isolation region in the first direction, and the gate structure extends along a second direction; the second direction is perpendicular to the first direction; the detection lead comprises a first detection lead, a second detection lead, a third detection lead and a fourth detection lead; the first detection lead leads to a gate structure located in the middle of the shallow trench isolation region, the second detection lead leads to a gate structure located at the two side edges of the shallow trench isolation region, the third detection lead leads to a gate structure located at the two side edges of the fin active region, and the fourth detection lead leads to a gate structure located in the middle of the fin active region.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit detection, in particular to a lateral short circuit detection structure between grids of a fin field effect transistor process.
Background
In fin field effect transistor (FinFET) semiconductor technology, defect management is critical to the improvement of semiconductor device yield. However, due to the extremely small size (less than a nanometer) and the complex structure of three-dimensional space, detection and analysis of defects are often very difficult.
In the related art, a test-key (test-key) similar to a real circuit is usually placed on a wafer to monitor defects in the real circuit in the manufacturing process, but the spare area outside the real circuit is precious and limited, so that how to improve the utilization rate of the test-key and the efficiency of capturing problems is a challenge to a design method. In addition, the lateral short circuit problem between the grids of the FinFET process relates to a plurality of modules such as grid (Gate), fin active region (Fin), source drain Epitaxy (EPI) and the like, and models of defect generation are quite different. The current related test-key designs are not optimized enough and a single structure cannot effectively detect and resolve various failure modes. Often, the possibility of a problem can be mined by means of mutual introduction of multiple groups of test-keys, so that the area is wasted and the time is wasted.
Disclosure of Invention
The application provides a detection structure for lateral short circuit between grids of a fin field effect transistor process, which can solve the problems that the related art structure for lateral short circuit between grids wastes the area of an integrated circuit and wastes the detection time.
In order to solve the technical problems in the background technology, the application provides a lateral short circuit detection structure between grids of a fin field effect transistor process, which comprises a shallow trench isolation region, a grid structure, a fin active region and a detection lead;
The fin-shaped active areas and the shallow trench isolation areas are alternately arranged along a first direction;
the middle part of the fin type active region and the two side edges of the fin type active region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the middle part of the shallow trench isolation region and the two side edges of the shallow trench isolation region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the second direction is perpendicular to the first direction;
the detection leads comprise a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;
the first detection lead leads out the grid structure positioned in the middle of the shallow trench isolation region, the second detection lead out the grid structure positioned at the edges of two sides of the shallow trench isolation region, the third detection lead out the grid structure positioned at the edges of two sides of the fin-type active region, and the fourth detection lead out the grid structure positioned in the middle of the fin-type active region.
Optionally, the first, second, third and fourth sense leads each extend along the first direction.
Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged at intervals in the second direction.
Optionally, a first contact hole is formed at the junction of the gate structure positioned in the middle of the shallow trench isolation region and the first detection lead, and the gate structure positioned in the middle of the shallow trench isolation region is interconnected with the first detection lead through the first contact hole;
The grid structures are positioned at the two side edges of the shallow trench isolation region and are intersected with the second detection lead to form a second contact hole; the grid structures positioned at the two side edges of the shallow trench isolation region are interconnected with the second detection lead through the second contact hole;
the gate structures are positioned at the two side edges of the fin-type active region and are intersected with the third detection lead to form a third contact hole; the gate structures located at the two side edges of the fin-shaped active region are interconnected with the third detection lead through the third contact hole;
A fourth contact hole is formed at the junction of the grid structure positioned in the middle of the fin-type active region and the fourth detection lead; and the grid structure positioned in the middle of the fin type active region is interconnected with the fourth detection lead through the fourth contact hole.
Optionally, the fin active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin active region in the first direction.
Optionally, each column of the fin active regions includes a plurality of rows spaced apart from each other in the second direction, and each row of fin active regions in each column of fin active regions is formed in a row alignment.
In order to solve the technical problems in the background art, the application also provides a lateral short circuit detection structure between grids of a fin field effect transistor process, which comprises a shallow trench isolation region, a grid structure, a fin active region and a detection lead;
The fin-shaped active areas and the shallow trench isolation areas are alternately arranged along a first direction;
The middle part of the fin type active region is provided with a plurality of grid structures, two side edges of the fin type active region in the first direction are respectively provided with a grid structure, and the grid structures extend along the second direction;
the middle part of the shallow trench isolation region and the two side edges of the shallow trench isolation region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the second direction is perpendicular to the first direction;
the detection leads comprise a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;
the first detection lead is led out of a grid structure positioned in the middle of the shallow trench isolation region, the second detection lead is led out of grid structures positioned at two side edges of the shallow trench isolation region, the third detection lead is led out of grid structures positioned at two side edges of the fin type active region and at least one grid structure positioned in the middle of the fin type active region, and the fourth detection lead is led out of the grid structures positioned in the middle of the fin type active region and the rest grid structures positioned in the middle of the fin type active region except the grid structures led out by the third detection lead.
Optionally, the first, second, third and fourth sense leads each extend along the first direction.
Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged at intervals in the second direction.
Optionally, a first contact hole is formed at the junction of the gate structure positioned in the middle of the shallow trench isolation region and the first detection lead, and the gate structure positioned in the middle of the shallow trench isolation region is interconnected with the first detection lead through the first contact hole;
The grid structures are positioned at the two side edges of the shallow trench isolation region and are intersected with the second detection lead to form a second contact hole; the grid structures positioned at the two side edges of the shallow trench isolation region are interconnected with the second detection lead through the second contact hole;
The intersection of the gate structures positioned at the two side edges of the fin-type active region and the third detection lead, and the intersection of at least one gate structure positioned in the middle of the fin-type active region and the third detection lead form a third contact hole; the gate structures are positioned at the edges of two sides of the fin type active region, and at least one gate structure positioned in the middle of the fin type active region is interconnected with the third detection lead through the third contact hole;
A fourth contact hole is formed at the intersection of the gate structure positioned in the middle of the fin-type active region and the fourth detection lead and at the intersection of the remaining gate structures positioned in the middle of the fin-type active region except the gate structure led out by the third detection and the fourth detection lead; and the gate structure positioned in the middle of the fin type active region, the rest gate structures positioned in the middle of the fin type active region except the gate structure led out by the third detection lead wire are interconnected with the fourth detection lead wire through the fourth contact hole.
Optionally, any two gate structures led out from the third detection lead are not adjacent to each other, and any two gate structures led out from the fourth detection lead are not adjacent to each other.
Optionally, the fin active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin active region in the first direction.
Optionally, each column of the fin active regions includes a plurality of rows spaced apart from each other in the second direction, and each row of fin active regions in each column of fin active regions is formed in a row alignment.
The technical scheme at least has the advantages that the lateral short circuit problem among various grids can be detected by arranging the shallow trench isolation region, the grid structure, the fin active region and the structure of the detection lead on a limited area, so that the detection area is greatly saved, and the time for analyzing the problem is saved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic top view of a lateral short detection structure between gates in a finfet process according to another embodiment of the present application;
fig. 2 is a schematic top view of a lateral short detection structure between gates in a finfet process according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intermediate medium, and in communication with each other between two elements, and wirelessly connected, or wired. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Fig. 1 is a schematic top view of a lateral short detection structure between gates in a fin field effect transistor process according to an embodiment of the present application, and it should be explained that the lateral short detection structure of the contact hole of the active area is composed of a plurality of basic units, the number of the basic units can be set according to the requirement, and the structure of each basic unit is shown in fig. 1.
As can be seen in fig. 1, the inter-gate lateral short detection structure of the finfet process includes a shallow trench isolation region 110, a gate structure 130, a fin active region 120, and a detection lead.
The fin active regions 120 and the shallow trench isolation regions 110 are alternately arranged along a first direction. The first direction in this embodiment is the lateral direction shown in fig. 1, and the fin-type active region 120 in this embodiment has two rows, i.e., a left-side row of fin-type active regions 120 and a right-side row of fin-type active regions 120, and the shallow trench isolation regions 110 are spaced between the two rows of fin-type active regions 120.
The middle portion of the fin active region 120 and two side edges of the fin active region 120 in the first direction are respectively provided with a gate structure 130, and the gate structure 130 extends along the second direction.
The middle part of the shallow trench isolation region 110 and the two side edges of the shallow trench isolation region 110 in the first direction are respectively provided with a gate structure 130, and the gate structure 130 extends along the second direction. The second direction in this embodiment is the longitudinal direction shown in fig. 1, and the first direction and the second direction are perpendicular.
The detection leads include a first detection lead Pin1 for leading out the gate structure 130 located in the middle of the shallow trench isolation region 110, a second detection lead Pin2 for leading out the gate structure 130 located at two sides of the shallow trench isolation region 110, a third detection lead Pin3 for leading out the gate structure 130 located at two sides of the fin-type active region 120, and a fourth detection lead Pin4 for leading out the gate structure 130 located in the middle of the fin-type active region 120.
The first, second, third and fourth sensing leads Pin1, pin2, pin3 and Pin4 each extend along the first direction shown in fig. 1. And the first, second, third and fourth sensing leads Pin1, pin2, pin3 and Pin4 are arranged to be spaced apart from each other in the second direction shown in fig. 2.
As can be seen from fig. 1, the left-side column fin active region 120 and the right-side column fin active region 120 each include three rows of fin active regions, a first row of fin active regions, a second row of fin active regions, and a third row of fin active regions in this order from top to bottom in the second direction. The fin active regions of the same row of the same column are arranged at intervals in the second direction, and the fin active regions of the same row of different columns are aligned in the first direction.
The first detection lead Pin1 is located above the first row of fin-type active regions, and a first contact hole 141 is formed at the intersection with the gate structure 130 located in the middle of the shallow trench isolation region 110. The first detecting lead Pin1 is interconnected with the gate structure 130 located in the middle of the shallow trench isolation region 110 through the first contact hole 141.
The second detecting lead Pin2 is located between the first row of fin-type active regions and the second row of fin-type active regions, and a second contact hole 142 is formed at the junction of the second detecting lead Pin2 and the gate structure 130 located at the two side edges of the shallow trench isolation region 110. The second detecting lead Pin2 is interconnected with the gate structures 130 located at two side edges of the shallow trench isolation region 110 through the second contact hole 142.
The third detecting lead Pin2 is located between the second row of fin-type active regions and the third row of fin-type active regions, and a third contact hole 143 is formed at the junction of the third detecting lead Pin2 and the gate structures 130 located at the two side edges of the fin-type active region 120. The third detecting lead Pin2 is interconnected with the gate structures 130 located at both side edges of the fin active region 120 through the third contact hole 143.
The fourth detection lead Pin4 is located under the fourth row of fin-type active regions 120, and a fourth contact hole 144 is formed at the intersection of the fourth detection lead Pin4 and the gate structure 130 located in the middle of the fin-type active regions 120. The fourth detecting lead Pin4 is interconnected with the gate structure 130 located in the middle of the fin active region 120 through the fourth contact hole 144.
Fig. 2 is a schematic top view of a lateral short detection structure between gates in a fin field effect transistor process according to another embodiment of the present application, and it should be explained that the lateral short detection structure of the contact hole of the active area is composed of a plurality of basic units, the number of the basic units can be set according to the requirement, and the structure of each basic unit is shown in fig. 2.
As can be seen in fig. 2, the inter-gate lateral short detection structure of the finfet process includes a shallow trench isolation region 110, a gate structure 130, a fin active region 120, and a detection lead.
The fin active regions 120 and the shallow trench isolation regions 110 are alternately arranged along a first direction. The first direction in this embodiment is the lateral direction shown in fig. 1, and the fin-type active region 120 in this embodiment has two rows, i.e., a left-side row of fin-type active regions 120 and a right-side row of fin-type active regions 120, and the shallow trench isolation regions 110 are spaced between the two rows of fin-type active regions 120.
A gate structure is disposed at two side edges of the fin active region 120. As shown in fig. 2, the gate structures located at the left and right edges of the fin active region 120 are the third gate structures 133.
A plurality of gate structures are also provided in the middle between the two side edges of the fin active region 120. As can be seen from fig. 2, in the present embodiment, the middle portion of the left-side column fin active region 120 and the middle portion of the right-side column fin active region 120 are provided with three gate structures, which are respectively a first gate structure 131 located in the middle, and a second gate structure 132 located between the first gate structure 131 and the left and right third gate structures 133.
It is understood that the first gate structure 131 and the left and right third gate structures 133 are separated by a second gate structure 132. The first gate structure 131 and the second gate structure 132 are both gate structures located in the middle of the fin active region 120.
The gate structures 130 are respectively disposed at two side edges of the shallow trench isolation region 110 and between two side edges of the shallow trench isolation region 110, and all the gate structures 130 extend along the second direction. The second direction in this embodiment is the longitudinal direction shown in fig. 2, and the first direction and the second direction are perpendicular.
The detection leads comprise a first detection lead Pin1, a second detection lead Pin2, a third detection lead Pin3 and a fourth detection lead Pin4.
The first detection lead Pin1 leads out the gate structure 130 positioned in the middle of the shallow trench isolation region 110, the second detection lead Pin2 leads out the gate structure 130 positioned at two side edges of the shallow trench isolation region 110, the third detection lead Pin3 leads out the gate structure 130 positioned at two side edges of the fin-type active region 120 and at least one gate structure 130 positioned in the middle of the fin-type active region 120, and the fourth detection lead Pin4 leads out the gate structure 130 positioned in the middle of the fin-type active region 120 and the rest gate structure 130 positioned in the middle of the fin-type active region 120 except the gate structure 130 led out by the third detection lead Pin 3.
As can be seen from fig. 2, the left-side column fin active region 120 and the right-side column fin active region 120 each include three rows of fin active regions 120, a first row of fin active regions, a second row of fin active regions, and a third row of fin active regions in this order from top to bottom in the second direction. The fin active regions 120 of the same row are arranged at intervals in the second direction, and the fin active regions 120 of the same row of different columns are aligned in the first direction.
The first detection lead Pin1 is located above the first row of fin-type active regions 120, and a first contact hole 141 is formed at the junction of the gate structure 130 located in the middle of the shallow trench isolation region 110, and the first detection lead Pin1 is interconnected with the gate structure 130 located in the middle of the shallow trench isolation region 110 through the first contact hole 141.
A second detection lead Pin2 is located between the first row of fin-type active regions 120 and the second row of fin-type active regions 120, and a second contact hole 142 is formed at the junction of the gate structures 130 located at the edges of the two sides of the shallow trench isolation region 110, and the second detection lead Pin2 is interconnected with the gate structures 130 located at the edges of the two sides of the shallow trench isolation region 110 through the second contact hole 142.
The third detection lead Pin3 is located between the second row of fin active regions 120 and the third row of fin active regions 120, and a third contact hole 143 is formed at the intersection with the third gate structure 133 and the intersection with the first gate structure 131, the third detection lead Pin3 and the third gate structure 133 are interconnected through the third contact hole 143, and the third detection lead Pin3 and the first gate structure 131 are interconnected through the third contact hole 143.
As can also be seen from fig. 2, any two gate structures led out from the third detecting lead Pin3 are not adjacent to each other, and a gate structure led out from another detecting lead is spaced between any two gate structures led out from the third detecting lead Pin3, that is, a second gate structure 132 is spaced between a third gate structure 133 led out from the third detecting lead Pin3 and the first gate structure 131, and the second gate structure 132 is led out from the fourth detecting lead Pin 4.
Similarly, any two gate structures led out from the fourth detection lead Pin4 are not adjacent to each other. The first gate structure 131 is spaced between the two second gate structures 132 led out from the fourth detection lead Pin 4.
The following different failure modes of the inter-gate lateral shorting problem can be detected by using the inter-gate lateral shorting detection structure of the finfet process shown in fig. 1 or 2 by:
The shorting test may be performed by applying a relatively high voltage to any one of the first and second sensing leads Pin1 and Pin2 and applying a relatively low voltage to the other sensing lead, and if the shorting test result shows a short, it is determined that an abnormality occurs at the top of the gate structure 130 located in the shallow trench isolation region 110.
A shorting test may be performed by applying a relatively high voltage to any one of the third and fourth sensing leads Pin3 and Pin4 and applying a relatively low voltage to the other sensing lead, and if the shorting test result shows a short, it is determined that an abnormality occurs in the bottom of the gate structure 130 located in the fin active region 120.
The shorting test may be performed by applying a relatively high voltage to any one of the second and third sensing leads Pin2 and Pin3 and applying a relatively low voltage to the other sensing lead, and if the shorting test result shows that shorting occurs, it is determined that an abnormality occurs at the edge of the fin active region 120.
The embodiment shown in fig. 1 and 2 can realize the detection of lateral short-circuit problems among various gates by arranging the structures of the shallow trench isolation region, the gate structure, the fin active region and the detection lead on a limited area, thereby greatly saving the detection area and the time for analyzing the problems.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (13)
1. The inter-gate lateral short circuit detection structure of the fin field effect transistor process is characterized by comprising a shallow trench isolation region, a gate structure, a fin active region and a detection lead;
The fin-shaped active areas and the shallow trench isolation areas are alternately arranged along a first direction;
the middle part of the fin type active region and the two side edges of the fin type active region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the middle part of the shallow trench isolation region and the two side edges of the shallow trench isolation region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the second direction is perpendicular to the first direction;
the detection leads comprise a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;
the first detection lead leads out the grid structure positioned in the middle of the shallow trench isolation region, the second detection lead out the grid structure positioned at the edges of two sides of the shallow trench isolation region, the third detection lead out the grid structure positioned at the edges of two sides of the fin-type active region, and the fourth detection lead out the grid structure positioned in the middle of the fin-type active region.
2. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 1, wherein the first, second, third, and fourth detection leads each extend along the first direction.
3. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 1, wherein the first, second, third, and fourth detection leads are spaced apart from each other in the second direction.
4. The fin field effect transistor process inter-gate lateral short detection structure of claim 1, wherein a first contact hole is formed at an intersection of a gate structure located in the middle of the shallow trench isolation region and the first detection lead;
The grid structures are positioned at the two side edges of the shallow trench isolation region and are intersected with the second detection lead to form a second contact hole; the grid structures positioned at the two side edges of the shallow trench isolation region are interconnected with the second detection lead through the second contact hole;
the gate structures are positioned at the two side edges of the fin-type active region and are intersected with the third detection lead to form a third contact hole; the gate structures located at the two side edges of the fin-shaped active region are interconnected with the third detection lead through the third contact hole;
A fourth contact hole is formed at the junction of the grid structure positioned in the middle of the fin-type active region and the fourth detection lead; and the grid structure positioned in the middle of the fin type active region is interconnected with the fourth detection lead through the fourth contact hole.
5. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 1, wherein the fin active region comprises at least two columns, the shallow trench isolation region being spaced between two adjacent columns of the fin active region in the first direction.
6. The fin field effect transistor process of claim 5, wherein each column of fin active regions includes a plurality of rows spaced apart from each other in the second direction, and rows of fin active regions in each column of fin active regions are aligned.
7. The inter-gate lateral short circuit detection structure of the fin field effect transistor process is characterized by comprising a shallow trench isolation region, a gate structure, a fin active region and a detection lead;
The fin-shaped active areas and the shallow trench isolation areas are alternately arranged along a first direction;
The middle part of the fin type active region is provided with a plurality of grid structures, two side edges of the fin type active region in the first direction are respectively provided with a grid structure, and the grid structures extend along the second direction;
the middle part of the shallow trench isolation region and the two side edges of the shallow trench isolation region in the first direction are respectively provided with a grid structure, and the grid structure extends along the second direction;
the second direction is perpendicular to the first direction;
the detection leads comprise a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;
The first detection lead is led out of a grid structure positioned in the middle of the shallow trench isolation region, the second detection lead is led out of grid structures positioned at two side edges of the shallow trench isolation region, the third detection lead is led out of grid structures positioned at two side edges of the fin type active region and at least one grid structure positioned in the middle of the fin type active region, and the fourth detection lead is led out of the grid structures positioned in the middle of the fin type active region and the rest grid structures positioned in the middle of the fin type active region except the grid structures led out by the third detection lead.
8. The fin-fet process inter-gate lateral shorting detection structure of claim 7, wherein the first, second, third, and fourth detection leads each extend along the first direction.
9. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 7, wherein the first, second, third, and fourth detection leads are spaced apart from each other in the second direction.
10. The fin field effect transistor process of claim 7, wherein the inter-gate lateral shorting detection structure,
The junction of the grid structure positioned in the middle of the shallow trench isolation region and the first detection lead forms a first contact hole; the grid structure positioned in the middle of the shallow trench isolation region is interconnected with the first detection lead through the first contact hole;
The grid structures are positioned at the two side edges of the shallow trench isolation region and are intersected with the second detection lead to form a second contact hole; the grid structures positioned at the two side edges of the shallow trench isolation region are interconnected with the second detection lead through the second contact hole;
The intersection of the gate structures positioned at the two side edges of the fin-type active region and the third detection lead, and the intersection of at least one gate structure positioned in the middle of the fin-type active region and the third detection lead form a third contact hole; the gate structures are positioned at the edges of two sides of the fin type active region, and at least one gate structure positioned in the middle of the fin type active region is interconnected with the third detection lead through the third contact hole;
A fourth contact hole is formed at the intersection of the gate structure positioned in the middle of the fin-type active region and the fourth detection lead and at the intersection of the remaining gate structures positioned in the middle of the fin-type active region except the gate structure led out by the third detection and the fourth detection lead; and the gate structure positioned in the middle of the fin type active region and the rest gate structure positioned in the middle of the fin type active region except the gate structure led out by the third detection lead are interconnected with the fourth detection lead through the fourth contact hole.
11. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 7, wherein any two gate structures from the third detection lead are not adjacent to each other and any two gate structures from the fourth detection lead are not adjacent to each other.
12. The fin field effect transistor process inter-gate lateral shorting detection structure of claim 7, wherein the fin active region comprises at least two columns, the shallow trench isolation region being spaced between two adjacent columns of the fin active region in the first direction.
13. The fin-fet process inter-gate lateral shorting detection structure of claim 12, wherein each column of the fin active regions comprises a plurality of rows spaced apart from each other in the second direction, and wherein rows of fin active regions in each column of fin active regions are aligned.
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| CN108831925A (en) * | 2018-05-30 | 2018-11-16 | 上海华力集成电路制造有限公司 | Defect Detection Structure and Detection Method of Fin Field Effect Transistor |
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| CN108831925A (en) * | 2018-05-30 | 2018-11-16 | 上海华力集成电路制造有限公司 | Defect Detection Structure and Detection Method of Fin Field Effect Transistor |
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