CN115050405A - Read-write control circuit, control method, chip and electronic equipment - Google Patents

Abstract

The application provides a read-write control circuit, a control method, a chip and electronic equipment, and belongs to the technical field of electronics. The read-write control circuit comprises a cache module; the read-write control circuitry is configured to: when continuous read-write operation exists, executing the read operation, and storing data corresponding to the write operation in the cache module; and writing the data corresponding to the write operation into a memory from the cache module. By the method and the device, system access efficiency can be improved.

Description

A read-write control circuit, control method, chip and electronic device

technical field

The present application relates to the field of electronic technology, and in particular, to a read-write control circuit, a control method, a chip and an electronic device.

Background technique

AHB (Advanced High Performance Bus, Advanced High Performance Bus) can trigger access to SRAM (Static Random-Access Memory, Static Random Access Memory) by initiating a read operation or a write operation.

When the AHB bus accesses the SRAM, if the write operation is followed by the read operation, the read operation will wait due to the time required for the SRAM write operation, and the system access efficiency will be affected.

SUMMARY OF THE INVENTION

In order to solve the problems in the prior art, the embodiments of the present application provide a read-write control circuit, a control method, a chip and an electronic device, which can improve system access efficiency. The technical solution is as follows:

According to an aspect of the present application, a read-write control circuit is provided, and the read-write control circuit includes a cache module;

The read-write control circuit is configured to:

When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module;

Data corresponding to the write operation is written into the memory from the cache module.

Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

The read-write control circuit is configured to:

When there is a write operation, the data corresponding to the write operation is stored in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, the read-write control circuit is configured as:

Receive a first operation instruction, and determine that the first operation instruction is a write operation, execute the first operation instruction and store the data corresponding to the first operation instruction in the first-level write cache unit;

Receive a second operation instruction, and determine that the second operation instruction is a read operation, if the first operation instruction is in the execution state, suspend the first operation instruction, and execute the second operation instruction to obtain the Describe the data required by the second operation instruction and write it back;

After the execution of the second operation instruction is completed, if there is currently no read operation to be executed, the pending first operation instruction is executed, and the data currently stored in the first-level write cache unit is written. the operation of the second level write cache unit.

Optionally, the read-write control circuit is configured as:

Receive a third operation instruction, and determine that the third operation instruction is a read operation, execute the third operation instruction to obtain the data required by the third operation instruction and write it back;

After receiving the fourth operation instruction, and determining that the fourth operation instruction is a write operation, after the execution of the third operation instruction is completed, the fourth operation instruction is executed and the data corresponding to the fourth operation instruction is stored in the in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, the read-write control circuit is further configured as:

Receive a fifth operation instruction, and determine that the fifth operation instruction is a write operation, execute the fifth operation instruction and store the data corresponding to the fifth operation instruction in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, the read-write control circuit is further configured as:

When performing the operation of writing the data currently stored in the first-level write-cache unit into the second-level write-cache unit, the data currently stored in the first-level write-cache unit is taken as the first data, if the The second-level write cache unit currently stores the second data, then it is determined whether the write address corresponding to the first data and the write address corresponding to the second data satisfy an adjacent condition, and the adjacent condition refers to the Storage locations in memory are adjacent;

If the adjacent condition is satisfied, writing the first data and the second data into the memory;

If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit.

Optionally, the read-write control circuit is further configured as:

When the bus is idle, the data currently stored in the cache module is written into the memory.

Optionally, the read-write control circuit is configured as:

When the data required for the read operation exists in the cache module, obtain the required data from the cache module;

When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

The read-write control circuit is configured to:

For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write-cache unit; Obtain the data of the current read operation; if it is not the same, enter the judgment on the second-level write cache unit as follows;

For the second level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second level write cache unit, if they are the same, then from the second level write cache unit Get the data of the current read operation.

Optionally, the cache module further includes a read cache unit;

The read-write control circuit is also configured to:

After judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, enter the following judgment on the read cache unit;

For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit, if they are the same, then obtain the data of the current read operation from the read cache unit; if not the same , the required data is read from the memory.

Optionally, the cache module further includes a read cache unit;

The read-write control circuit is also configured to:

Based on the read address corresponding to the current read operation, read the data of the read address and its adjacent storage locations from the memory;

The data of the read address is written back as the data required for the current read operation, and the data of the adjacent storage location is written into the read cache unit.

Optionally, the cache module includes a first-level write cache unit, a second-level write cache unit, and a read cache unit, and the read-write control circuit further includes a first data selector, a second data selector, and a third data selector. a selector, a fourth data selector and a write data selection control circuit;

The input end of the first-level write buffer unit is connected to the bus, and the output end is respectively connected to the input end of the first data selector and the input end of the second data selector;

The input end of the second-level write buffer unit is connected to the output end of the first data selector, and the output end is respectively connected to the input end of the write data selection control circuit and the input end of the third data selector;

The input end of the read buffer unit is connected to the memory, and the output end is connected to the input end of the fourth data selector;

The input end of the first data selector is also connected to the bus, and the output end is also connected to the write data selection control circuit;

The input end of the second data selector is also connected to the output end of the third data selector, and the output end is connected to the bus;

The input end of the third data selector is also connected with the output end of the fourth data selector;

The input end of the fourth data selector is also connected with the memory;

The output end of the write data selection control circuit is also connected to the memory.

According to another aspect of the present application, a control method for a read-write control circuit is provided, the read-write control circuit includes a cache module;

The method includes:

When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module;

Data corresponding to the write operation is written into the memory from the cache module.

According to another aspect of the present application, a chip is provided, including the above-mentioned read-write control circuit.

According to another aspect of the present application, an electronic device is provided, including the above-mentioned read-write control circuit.

In this application, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read preferentially, and then the data of the write operation is written into the memory, eliminating the need for the write operation to occur in the first place. The waiting time of the read operation improves the system access efficiency.

Description of drawings

Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

1 shows a schematic diagram of a read-write control circuit provided according to an exemplary embodiment of the present application;

FIG. 2 shows a schematic diagram of a cache module provided according to an exemplary embodiment of the present application;

FIG. 3 shows a schematic diagram of a cache module provided according to an exemplary embodiment of the present application;

FIG. 4 shows a schematic diagram of a cache module provided according to an exemplary embodiment of the present application;

FIG. 5 shows a schematic diagram of a read-write control circuit provided according to an exemplary embodiment of the present application;

Fig. 6 shows the system sequence diagram when the read-write control circuit provided by the present application is not used;

Fig. 7 shows the system sequence diagram after adopting the read-write control circuit provided by the present application;

Fig. 8 shows the system sequence diagram when the read-write control circuit provided by the present application is not used;

Fig. 9 shows the system sequence diagram after adopting the read-write control circuit provided by the present application;

FIG. 10 shows a flowchart of a control method of a read-write control circuit provided according to an exemplary embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for the purpose of A more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of the present application are only used for exemplary purposes, and are not used to limit the protection scope of the present application.

As used herein, the term "including" and variations thereof are open-ended inclusions, ie, "including but not limited to". The term "based on" is "based at least in part on." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or interdependence.

It should be noted that the modifications of "a" and "a plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, they should be understood as "one or a plurality of". multiple".

The names of messages or information exchanged between multiple devices in the embodiments of the present application are only used for illustrative purposes, and are not used to limit the scope of these messages or information.

The embodiments of the present application provide a read-write control circuit, and the read-write control circuit may be integrated in a chip or provided in an electronic device.

Referring to the schematic diagram of the read-write control circuit shown in FIG. 1 , the read-write control circuit may include a cache module.

The read-write control circuit can be configured as:

When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module;

Write the data corresponding to the write operation into the memory from the cache module.

In a possible implementation, a read-write control circuit may be provided between the bus and the memory, and data is transferred between the two. Specifically, the above-mentioned bus may refer to the AHB bus, and the memory may refer to the SRAM. As an example, the read-write control circuit can be applied to the design of a 32-bit MCU (Microcontroller Unit, micro-control unit), and each address of the SRAM stores 64 bits of data.

When the bus sends out continuous read and write operations, through configuration, the read-write control circuit can first perform the read operation, read the data required for the read operation, and then perform the write operation, and store the data corresponding to the write operation in the cache module. And write the data of the write operation to the memory.

When there are continuous read and write operations, especially continuous write + read operations, the waiting time of the read operation when the write operation is preceded is eliminated, and the system access efficiency is improved.

The configuration related to the write operation of the read/write control circuit will be introduced below.

Referring to the schematic diagram of the cache module shown in FIG. 2 , the cache module may include a first-level write cache unit and a second-level write cache unit. As an example, the data stored in the first-level write cache unit and the second-level write cache unit may be 32 bits.

On this basis, the read-write control circuit can be configured as:

When there is a write operation, the data corresponding to the write operation is stored in the first-level write cache unit;

If there is currently no read operation to be performed, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

In a possible implementation, whenever a write operation is issued by the bus, the data corresponding to the write operation is first stored in the first-level write buffer unit, and the next non-read address phase of the bus (that is, there is no pending execution) read operation), write the data of the first-level write cache unit into the second-level write cache unit. That is to say, if the next clock cycle of the write address phase in the bus is the read address phase (that is, the read operation is triggered), the write operation is temporarily suspended, the SRAM is read first, and when there is no read address phase on the bus, the write operation is suspended. The write operation from the beginning of the write operation is executed, that is, the second-level write cache unit is written. As an example, referring to FIG. 6 , when HWRITE is high and HADDR has an address phase, it means that the AHB bus issues a write operation, and the address phase at this time is the write address phase; when HWRITE is low and HADDR has an address phase, it means AHB The bus issues a read operation, and the address phase at this time is the read address phase.

Optionally, after the data of the first-level write cache unit is written into the second-level write cache unit, the first-level write cache unit may be cleared.

Each situation of the trigger operation will be introduced separately below.

Case 1: Trigger continuous write + read operations, that is, the write operation comes first, and the read operation comes after.

In this case, the read-write control circuit can be configured as:

Receive the first operation instruction, and determine that the first operation instruction is a write operation, then execute the first operation instruction and store the data corresponding to the first operation instruction in the first-level write cache unit;

Receive the second operation instruction, and determine that the second operation instruction is a read operation. If the first operation instruction is in the execution state, the first operation instruction is suspended, and the second operation instruction is executed to obtain the data required by the second operation instruction and write back;

After the second operation instruction is executed, if there is currently no read operation to be executed, the pending first operation instruction is executed, and the data currently stored in the first-level write cache unit is written into the second-level write cache unit. operation.

In a possible implementation, in the first clock cycle, the first operation instruction corresponding to the write operation is triggered in the bus, the first operation instruction can be received and the type of the instruction can be determined as a write operation, and then the read and write control circuit The write operation may be performed to store the data corresponding to the write operation into the first-level write cache unit. In the next second clock cycle, the second operation instruction corresponding to the read operation is triggered in the bus, the second operation instruction can be received and the instruction type can be determined as a write operation, and then the read-write control circuit can suspend the above write operation. , perform the read operation, obtain the data required by the read operation, and write it back as the result of the second operation instruction. In the next third clock cycle, if another write operation is triggered on the bus or no operation is triggered, and there is no read address phase in the bus at this time, the read-write control circuit can execute the pending write operation, that is, execute The operation of writing the data currently stored in the first-level write-cache unit into the second-level write-cache unit.

In addition, in the above third clock cycle, if another read operation is triggered in the bus, the read operation and the pending write operation still have a conflict of accessing the memory (that is, there is a waiting time for the read operation when the write operation is ahead), and the read operation still has a conflict with the pending write operation. Consistent with the above situation. At this time, the write operation may continue to be suspended until there is no read operation to be performed on the bus, and then the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Case 2: Trigger continuous read + write operations, that is, read operations come first and write operations follow.

In this case, the read-write control circuit can be configured as:

Receive the third operation instruction, and determine that the third operation instruction is a read operation, execute the third operation instruction to obtain the data required by the third operation instruction and write it back;

Receive the fourth operation instruction, and determine that the fourth operation instruction is a write operation, then after the execution of the third operation instruction is completed, execute the fourth operation instruction and store the data corresponding to the fourth operation instruction in the first-level write cache unit;

If there is currently no read operation to be performed, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

In a possible implementation, in the first clock cycle, the third operation instruction corresponding to the read operation is triggered in the bus, the third operation instruction can be received and the instruction type can be determined as a read operation, and then the read and write control circuit can be read and written. The read operation can be performed, and the data required for the read operation is obtained and written back as a result of the third operation instruction. In the next second clock cycle, the fourth operation instruction corresponding to the write operation is triggered in the bus, the fourth operation instruction can be received, the instruction type can be determined as a write operation, and it is determined whether the above-mentioned read operation is completed. After the above-mentioned read operation is completed, the read-write control circuit may execute the write operation corresponding to the fourth operation instruction, and store the data corresponding to the write operation into the first-level write cache unit. In the next third clock cycle, if another write operation is triggered in the bus or no operation is triggered, and there is no read address phase in the bus at this time, the read-write control circuit can execute the data currently stored in the first-level write cache unit. An operation that writes to a second-level write cache unit.

Similarly, in the above third clock cycle, if another read operation is triggered in the bus, the read operation and the write operation corresponding to the fourth operation instruction have a conflict of accessing the memory (that is, there is a waiting time for the read operation when the write operation is preceding) , which is consistent with the above situation. At this time, the write operation can be suspended until there is no read operation to be performed on the bus, and then the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Case 3: Trigger continuous write + write operation or separate write operation.

In this case, the read-write control circuit can be configured as:

Receive the fifth operation instruction, and determine that the fifth operation instruction is a write operation, then execute the fifth operation instruction and store the data corresponding to the fifth operation instruction in the first-level write cache unit;

If there is currently no read operation to be performed, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

In a possible implementation, in the first clock cycle, the fifth operation instruction corresponding to the write operation is triggered in the bus, the fifth operation instruction can be received and the instruction type can be determined as a write operation, and then the read and write control circuit The write operation may be performed, and the data corresponding to the write operation is stored in the first-level write cache unit. In the next second clock cycle, the sixth operation instruction corresponding to another write operation is triggered in the bus or no operation is triggered (that is, there is no read operation to be performed), then the read-write control circuit can execute the first-level write operation. The operation of writing the data currently stored in the cache unit to the second-level write cache unit. Thereafter, in response to receiving the sixth operation instruction, the read-write control circuit may also clear the first-level write cache unit, and store the data corresponding to the write operation of the sixth operation instruction into the first-level write cache unit.

Optionally, the specific processing of the above-mentioned operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit may be as follows:

Using the data currently stored in the first-level write cache unit as the first data, determine whether the second-level write cache unit stores the second data;

If the second-level write cache unit currently stores the second data, it is determined whether the write address corresponding to the first data and the write address corresponding to the second data satisfy the adjacent condition. The adjacent condition means that the storage locations in the memory are adjacent to each other. ; If the adjacent conditions are met, the first data and the second data are written into the memory; if the adjacent conditions are not met, the second data is written into the memory, and the first data is written into the second-level write cache unit;

If the second level write cache unit does not currently store the second data, the data currently stored in the first level write cache unit is written into the second level write cache unit. At this time, the data stored in the second-level write cache unit can be used as the second data when the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed next time.

As an example, the addresses of the read and write operations initiated by the AHB bus may be such as 0xXXXX_XXX0, 0xXXXX_XXX4, 0xXXXX_XXX8 and 0xXXXX_XXXC, and each address corresponds to 32 bits of data, where 0xXXXX_XXX0 and 0xXXXX_XXX4 are adjacent, and 0xXXXX_XXX8 and 0xXXXX_XXXC are adjacent. Two adjacent addresses can be addressed to the same physical address in the SRAM (bit width is 64 bits), and the data of a total of 64 bits corresponding to the two adjacent addresses is stored in the same physical address addressed, that is, it satisfies Adjacent conditions.

Whenever data needs to be written into the second-level write cache unit, it can be judged whether the second-level write cache unit is full by relying on the full flag of the cache. If the cache is full, it cannot be written. At this time, it can be judged whether the address of the current data to be written (ie the first data) and the address of the data already cached in the second-level write cache unit (ie the second data) satisfy the aforementioned adjacent conditions.

If it is satisfied, it means that the corresponding position can be accessed by addressing once in the SRAM, and 64bit data is written into the SRAM.

If it is not satisfied, write the 32-bit data that has been cached in the second-level write cache unit into the SRAM, write the 32-bit data currently to be written into the second-level write cache unit, and wait for another 32-bit data adjacent to it. Data is written to SRAM all at once.

Through the above configuration, the second-level write cache unit can be used to cache the data waiting for adjacent addresses. When the data of two adjacent addresses are written twice in a row, the data of the two addresses can be written into the memory at the same time. , reducing the number of memory accesses, thereby reducing system power consumption.

After that, the data can be written into the memory when the bus is idle, and on this basis, the read-write control circuit can also be configured to write the data currently stored in the cache module into the memory when the bus is idle. Optionally, after the data is written into the memory, the corresponding data in the cache module may be deleted, that is, the cache module may be cleared.

Through the above configuration, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written into the memory, eliminating the need for the write operation to be in the first place. The waiting time of the read operation improves the system access efficiency.

The configuration related to the read operation of the read/write control circuit will be introduced below.

For read operations, the read/write control circuit can be configured as:

When the data required for the read operation exists in the cache module, obtain the required data from the cache module;

When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

In a possible implementation manner, whether the data is required for the read operation may be determined based on the address of the read operation and the address of the data already cached in the cache module. If the data at the same address as the read operation exists in the cache module, indicating that the data is required for the read operation, the data can be obtained from the cache module as the result of the read operation and written back. If not present, the memory can be accessed, the data needed for the read operation is read and written back.

Through the above configuration, the number of times of accessing the memory can also be reduced, and the power consumption of the system can be reduced.

Optionally, when the cache module includes a first-level write cache unit and a second-level write cache unit, the read-write control circuit may be configured as:

For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write-cache unit, if they are the same, obtain the data of the current read operation from the first-level write-cache unit ; If they are not the same, enter the following judgment for the second-level write cache unit;

For the second-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit, if they are the same, obtain the data of the current read operation from the second-level write cache unit .

That is to say, whether the first-level write cache unit and the second-level write cache unit store data required for the read operation can be sequentially determined, and if so, the read operation data comes from the corresponding write cache unit.

If the required data is still not found in the second-level write cache unit, the required data can be read from the memory, or the technical solution provided below is used to continue the search.

In order to further reduce the power consumption of the system, similar to the technical solution of writing the data of two adjacent addresses at the same time, the data of the two adjacent addresses can be read out through the cache module at the same time, and the data of the two adjacent addresses can be read out by the cache module. After the required data is taken away, the data in the adjacent storage location is written into the cache module. When judging whether the data required for the read operation exists in the cache module, it can also be judged whether the data required for the current read operation is read out by judging whether the data required for the current read operation is read out in the previous read operation.

On this basis, as an optional solution, referring to the schematic diagram of the cache module shown in FIG. 3 , the cache module may further include a read cache unit, and the read cache unit may be used to store the data of the above-mentioned adjacent storage locations. As an example, the data stored in the read cache unit may be 32 bits.

When the read cache unit is combined with the first level write cache unit and the second level write cache unit, as shown in FIG. 4 . On this basis, the read-write control circuit can also be configured as:

After judging whether the read address corresponding to the current read operation and the address corresponding to the data of the second-level write cache unit are the same, if they are not the same, enter the following judgment on the read cache unit;

For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit. If they are the same, obtain the data of the current read operation from the read cache unit; if they are not the same, read from the memory. Fetch the required data.

That is to say, whether the first-level write cache unit, the second-level write cache unit and the read cache unit store the data required for the read operation can be judged in turn, and if so, the data of the read operation comes from the corresponding cache unit.

Among them, the process of judging whether the read address corresponding to the current read operation and the address corresponding to the data of the read cache unit are the same, or whether the read address corresponding to the current read operation and the read address corresponding to the previous read operation satisfy the above-mentioned adjacent If the condition is fulfilled, it indicates that the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit.

After that, if the desired data is still not found, the desired data can be read from the memory.

When data needs to be read from memory, the read-write control circuit can be configured as:

Based on the read address corresponding to the current read operation, read the data of the read address and its adjacent storage locations from the memory;

After the data of the read address is written back as the data required by the current read operation, the data of the adjacent storage location is written into the read cache unit.

As a specific example, referring to the schematic diagram of the read-write control circuit shown in FIG. 5 , the read-write control circuit may specifically consist of a first-level write cache unit, a second-level write cache unit, a read cache unit, and a first data selector. , a second data selector, a third data selector, a fourth data selector and a write data selection control circuit, wherein the first level write cache unit, the second level write cache unit and the read cache unit may correspond to the above cache Module, the configuration of the read-write control circuit can be realized through the first data selector, the second data selector, the third data selector, the fourth data selector and the write data selection control circuit.

The input end of the first-level write buffer unit can be connected to the AHB bus, and the output end is respectively connected to the first data selector and the second data selector.

The input end of the second-level write buffer unit can be connected to the first data selector, and the output end is respectively connected to the write data selection control circuit and the third data selector.

The input end of the read buffer unit can be connected to the SRAM, and the output end is connected to the fourth data selector.

The input end of the first data selector can be connected to the AHB bus and the first-level write buffer unit respectively, and the output end is respectively connected to the second-level write buffer unit and the write data selection control circuit.

The input end of the second data selector can be connected to the first-level write buffer unit and the third data selector respectively, and the output end is connected to the AHB bus.

The input end of the third data selector can be connected to the second-level write buffer unit and the fourth data selector respectively, and the output end is connected to the second data selector.

The input end of the fourth data selector can be connected to the SRAM and the read buffer unit respectively, and the output end is connected to the third data selector.

The input end of the write data selection control circuit can be respectively connected to the first data selector and the second level write buffer unit, and the output end is connected to the SRAM.

The embodiments of the present application can achieve the following beneficial effects:

(1) When there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written into the memory, eliminating the need for the read operation when the write operation is preceded. The waiting time of the operation improves the system access efficiency.

Figure 6 shows the system timing diagram when the read-write control circuit provided by the present application is not used, wherein, when HWRITE is high and HADDR has an address phase, it means that the AHB bus issues a write operation, HWRITE is low and HADDR has an address When in phase, it means that the AHB bus sends out a read operation. In Figure 6, the write operation and the read operation are continuous, and the write operation comes first. It can be seen from the timing diagram that SRAM first triggers the write operation WR, and then triggers the read operation RD. However, because SRAM requires time to write, HREADYOUT is low when the read operation RD is triggered, indicating that the data is not ready to be read (in HRDATA The shaded part of ) indicates that the read operation is delayed by one beat and then reads out data (RDATA in HRDATA indicates that RDATA is not read out in the next beat of RD).

Figure 7 shows the system timing diagram after using the read-write control circuit provided by the present application, wherein, SRAM first triggers the read operation RD, and then triggers the write operation WR, and RDATA can be read out in the next shot of RD, eliminating the need for waiting for writing Time to operate WR write.

(2) When the data of two adjacent addresses are written twice in a row, the data of the two addresses can be written into the memory at the same time, and/or the data of the two adjacent addresses can be read out at the same time , when the data of two adjacent addresses are read for two consecutive times, the data can be obtained from the cache module, which reduces the number of times of accessing the memory, thereby reducing the power consumption of the system.

Figure 8 shows a system timing diagram when the read-write control circuit provided by the present application is not used, wherein addr0 and addr1 are two adjacent write addresses, and addr2 and addr3 are two adjacent read addresses. It can be seen that Every AHB bus read and write will trigger SRAM read and write (each WR corresponds to a write address, each RD corresponds to a read address), and the system power consumption is high.

Fig. 9 shows the system timing diagram after using the read-write control circuit provided by the present application, in which it can be seen that the two read/write operations of the AHB bus only trigger one read/write operation of the SRAM (addr0 and addr1 triggers a WR, addr2 and addr3 trigger a RD), which reduces system power consumption.

The embodiment of the present application also provides a control method for a read-write control circuit, which can be used to control the above-mentioned read-write control circuit, and the read-write control circuit includes a cache module. Referring to the flow chart of the control method of the read-write control circuit shown in FIG. 10, the method may include the following steps 1001-1002:

Step 1001, when there are continuous read and write operations, perform a read operation, and store the data corresponding to the write operation in the cache module;

Step 1002: Write the data corresponding to the write operation into the memory from the cache module.

Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

The storing of the data corresponding to the write operation in the cache module includes:

When there is a write operation, the data corresponding to the write operation is stored in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, when there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module, including:

Receive a first operation instruction, and determine that the first operation instruction is a write operation, execute the first operation instruction and store the data corresponding to the first operation instruction in the first-level write cache unit;

Receive a second operation instruction, and determine that the second operation instruction is a read operation, if the first operation instruction is in the execution state, suspend the first operation instruction, and execute the second operation instruction to obtain the Describe the data required by the second operation instruction and write it back;

After the execution of the second operation instruction is completed, if there is currently no read operation to be executed, the pending first operation instruction is executed, and the data currently stored in the first-level write cache unit is written. the operation of the second level write cache unit.

Optionally, when there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module, including:

Receive a third operation instruction, and determine that the third operation instruction is a read operation, execute the third operation instruction to obtain the data required by the third operation instruction and write it back;

After receiving the fourth operation instruction, and determining that the fourth operation instruction is a write operation, after the execution of the third operation instruction is completed, the fourth operation instruction is executed and the data corresponding to the fourth operation instruction is stored in the in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, the method further includes:

Receive a fifth operation instruction, and determine that the fifth operation instruction is a write operation, execute the fifth operation instruction and store the data corresponding to the fifth operation instruction in the first-level write cache unit;

If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

Optionally, the performing the operation of writing data currently stored in the first-level write-cache unit into the second-level write-cache unit includes:

The data currently stored in the first-level write cache unit is used as the first data, and if the second-level write cache unit currently stores the second data, it is determined that the write address corresponding to the first data is the same as the second data. Whether the write address corresponding to the data satisfies the adjacent condition, the adjacent condition means that the storage locations in the memory are adjacent;

If the adjacent condition is satisfied, writing the first data and the second data into the memory;

If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit.

Optionally, the method further includes:

When the bus is idle, the data currently stored in the cache module is written into the memory.

Optionally, the performing a read operation includes:

When the data required for the read operation exists in the cache module, obtain the required data from the cache module;

When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

When the data required for the read operation exists in the cache module, acquiring the required data from the cache module includes:

For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write-cache unit; Obtain the data of the current read operation; if it is not the same, enter the judgment on the second-level write cache unit as follows;

For the second level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second level write cache unit, if they are the same, then from the second level write cache unit Get the data of the current read operation.

Optionally, the cache module further includes a read cache unit;

The method also includes:

After judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, enter the following judgment on the read cache unit;

For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit, if they are the same, then obtain the data of the current read operation from the read cache unit; if not the same , the required data is read from the memory.

Optionally, the method further includes:

Based on the read address corresponding to the current read operation, read the data of the read address and its adjacent storage locations from the memory;

The data of the read address is written back as the data required for the current read operation, and the data of the adjacent storage location is written into the read cache unit.

In the embodiment of the present application, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written into the memory, which eliminates the need for the write operation in the memory. The waiting time of the previous read operation improves the system access efficiency.

The embodiments of the present application further provide a chip, including the read-write control circuit provided by the embodiments of the present application. The chip may be, but is not limited to, a SOC (System on Chip, system-on-chip) chip, or a SIP (system in package, system-in-package) chip. By configuring the above-mentioned read-write control circuit, the chip improves the system access efficiency.

An embodiment of the present application further provides an electronic device, the electronic device includes a device body and the above-mentioned chip provided in the device subject. Electronic devices can be but are not limited to weight scales, body fat scales, nutrition scales, infrared electronic thermometers, pulse oximeters, body composition analyzers, power banks, wireless chargers, fast chargers, car chargers, adapters, monitors , USB (Universal Serial Bus, Universal Serial Bus) docking station, stylus, true wireless headset, car central control screen, automobile, smart wearable device, mobile terminal, smart home equipment. Smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical spine massagers. Mobile terminals include, but are not limited to, smart phones, notebook computers, tablet computers, and POS (point of sales terminal, point of sale terminal) machines. Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights. By configuring the above-mentioned read-write control circuit in the electronic device, the access efficiency of the electronic device system is improved.

The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Without departing from the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or modifications to equivalent examples of equivalent changes, provided that it does not depart from the content of the technical solution of the present application, according to the technical essence of the present application. Any brief modifications, equivalent changes and modifications made in the above embodiments still fall within the scope of the technical solutions of the present application.

Claims (15)

1. a read-write control circuit, is characterized in that, described read-write control circuit comprises a cache module; The read-write control circuit is configured to: When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module; Data corresponding to the write operation is written into the memory from the cache module. 2. The read-write control circuit according to claim 1, wherein the cache module comprises a first-level write cache unit and a second-level write cache unit; The read-write control circuit is configured to: When there is a write operation, the data corresponding to the write operation is stored in the first-level write cache unit; If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed. 3. The read-write control circuit according to claim 2, wherein the read-write control circuit is configured as: Receive a first operation instruction, and determine that the first operation instruction is a write operation, execute the first operation instruction and store the data corresponding to the first operation instruction in the first-level write cache unit; Receive a second operation instruction, and determine that the second operation instruction is a read operation, if the first operation instruction is in the execution state, suspend the first operation instruction, and execute the second operation instruction to obtain the Describe the data required by the second operation instruction and write it back; After the execution of the second operation instruction is completed, if there is currently no read operation to be executed, the pending first operation instruction is executed, and the data currently stored in the first-level write cache unit is written. the operation of the second level write cache unit. 4. The read-write control circuit according to claim 2, wherein the read-write control circuit is configured as: Receive a third operation instruction, and determine that the third operation instruction is a read operation, execute the third operation instruction to obtain the data required by the third operation instruction and write it back; After receiving the fourth operation instruction, and determining that the fourth operation instruction is a write operation, after the execution of the third operation instruction is completed, the fourth operation instruction is executed and the data corresponding to the fourth operation instruction is stored in the in the first-level write cache unit; If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed. 5. The read-write control circuit according to claim 2, wherein the read-write control circuit is further configured as: Receive a fifth operation instruction, and determine that the fifth operation instruction is a write operation, execute the fifth operation instruction and store the data corresponding to the fifth operation instruction in the first-level write cache unit; If there is no read operation to be performed currently, the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed. 6. The read-write control circuit according to any one of claims 2-5, wherein the read-write control circuit is further configured as: When performing the operation of writing the data currently stored in the first-level write-cache unit into the second-level write-cache unit, the data currently stored in the first-level write-cache unit is taken as the first data, if the The second-level write cache unit currently stores the second data, then it is determined whether the write address corresponding to the first data and the write address corresponding to the second data satisfy an adjacent condition, and the adjacent condition refers to the Storage locations in memory are adjacent; If the adjacent condition is satisfied, writing the first data and the second data into the memory; If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit. 7. The read-write control circuit according to claim 1, wherein the read-write control circuit is further configured as: When the bus is idle, the data currently stored in the cache module is written into the memory. 8. The read-write control circuit according to claim 1, wherein the read-write control circuit is configured as: When the data required for the read operation exists in the cache module, obtain the required data from the cache module; When the data required for the read operation does not exist in the cache module, the required data is read from the memory. 9. The read-write control circuit according to claim 8, wherein the cache module comprises a first-level write cache unit and a second-level write cache unit; The read-write control circuit is configured to: For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write-cache unit; Obtain the data of the current read operation; if it is not the same, enter the judgment on the second-level write cache unit as follows; For the second level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second level write cache unit, if they are the same, then from the second level write cache unit Get the data of the current read operation. 10. The read-write control circuit according to claim 9, wherein the cache module further comprises a read cache unit; The read-write control circuit is also configured to: After judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, enter the following judgment on the read cache unit; For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit, if they are the same, then obtain the data of the current read operation from the read cache unit; if not the same , the required data is read from the memory. 11. The read-write control circuit according to claim 8, wherein the cache module further comprises a read cache unit; The read-write control circuit is also configured to: Based on the read address corresponding to the current read operation, read the data of the read address and its adjacent storage locations from the memory; The data of the read address is written back as the data required for the current read operation, and the data of the adjacent storage location is written into the read cache unit. 12 . The read-write control circuit according to claim 1 , wherein the cache module comprises a first-level write cache unit, a second-level write cache unit and a read cache unit, and the read-write control circuit further includes a first-level write cache unit. 13 . a data selector, a second data selector, a third data selector, a fourth data selector and a write data selection control circuit; The input end of the first-level write buffer unit is connected to the bus, and the output end is respectively connected to the input end of the first data selector and the input end of the second data selector; The input end of the second-level write buffer unit is connected to the output end of the first data selector, and the output end is respectively connected to the input end of the write data selection control circuit and the input end of the third data selector; The input end of the read buffer unit is connected to the memory, and the output end is connected to the input end of the fourth data selector; The input end of the first data selector is also connected to the bus, and the output end is also connected to the write data selection control circuit; The input end of the second data selector is also connected to the output end of the third data selector, and the output end is connected to the bus; The input end of the third data selector is also connected with the output end of the fourth data selector; The input end of the fourth data selector is also connected with the memory; The output end of the write data selection control circuit is also connected to the memory. 13. A control method for a read-write control circuit, wherein the read-write control circuit comprises a cache module; The method includes: When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module; The data corresponding to the write operation is written into the memory from the cache module. 14. A chip, characterized by comprising the read-write control circuit according to at least one of claims 1-12. 15. An electronic device, characterized by comprising the read-write control circuit according to at least one of claims 1-12.

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