CN115035929A - A circuit, method and electronic device for efficiently realizing pseudo DDR signal crossing clock domain - Google Patents

Abstract

The invention discloses a circuit, method and electronic device for efficiently realizing pseudo DDR signal crossing clock domain, and relates to the technical field of circuit design. A cross-clock domain module, and a host-side low-frequency clock domain module connected to multiple cross-clock domain modules; each cross-clock module includes a low-frequency to high-frequency transmission sub-module and a high-frequency to low-frequency transmission sub-module, and low-frequency to high-frequency transmission sub-modules One end of the sub-module is connected to the chip-side high-frequency clock domain module, the other end is connected to the host-side low-frequency clock domain module, one end of the high-frequency to low-frequency transmission sub-module is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low frequency clock domain module The clock domain module is connected; it can simultaneously handle scenarios with high timing requirements such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals, avoiding multi-domain propagation of metastable states, and improving the stability and reliability of the circuit.

Description

A circuit, method and electronic device for efficiently realizing pseudo DDR signal crossing clock domain

technical field

The present invention relates to the technical field of circuit design, and in particular, to a circuit, method and electronic device for efficiently realizing a pseudo DDR signal crossing a clock domain.

Background technique

Simple digital integrated circuits are synchronous logic circuits driven by a single clock. The flip-flops in this circuit are reversed under the control of a unified clock, the timing constraints are relatively simple, and the clock system design is relatively easy. However, a single clock constraint is no longer suitable for the rapidly growing integrated circuit scale at this stage. Multiple clock domains usually exist in the design of large-scale digital circuits with complex functions. How to solve the propagation of signals across clock domains (Clock Domain Crossing, CDC), realize the output driving and input sampling of signals, and reduce or avoid the generation of metastability has become a key issue that determines the success or failure of digital integrated circuit design.

The most common way to solve the problem of crossing the clock domain at this stage is to use a synchronizer to sample the asynchronous input signal, so that the generated output signal meets the requirements of the synchronous system for setup time and hold time, thereby suppressing metastability adverse effects on the circuit. There are two commonly used synchronization methods: two-level flip-flop method and locking method.

The essence of the two-stage flip-flop method is to reduce the probability of occurrence of metastable states. By cascading two-stage flip-flops, when the signal from the previous clock domain reaches the first flip-flop of the next clock domain, it is likely to appear unsatisfactory. The setup/hold time condition causes the output of this stage to be metastable for a long time. If the state of the second stage lasts for less than one cycle, the metastable state can be eliminated by adding a first-stage flip-flop, so that the output of the second-stage flip-flop meets the requirements of the synchronization signal, but as long as one stage of D flip-flop is added Will increase the 1-order delay of the input signal. This method is usually used for circuit synchronization with low timing requirements. It is suitable for the synchronization of a small number of signals from slow clocks to fast clocks, but cannot achieve bidirectional synchronization of a large number of signals between fast and slow clock domains with high timing requirements.

The locking method mainly solves the problem that the slow clock may not be able to sample the fast clock in time if the signal changes too fast when the signal transitions from the fast clock to the slow clock during the synchronization of the two-stage transmitter. As a supplement to the two-stage flip-flop method, the lock-in synchronizer still cannot meet the high timing requirements of synchronous cross-domain propagation of a large number of control signals and data signals between fast and slow clock domains, resulting in metastable multi-domain propagation and reducing the system. stability and reliability.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a circuit, method and electronic device for efficiently realizing the cross-clock domain of a pseudo DDR signal, so as to solve the problem that the existing method for solving the cross-clock domain cannot satisfy the synchronous cross-domain propagation of a large number of control signals and data signals between fast and slow clock domains The high timing requirements of the system lead to the occurrence of metastable multi-domain propagation, which reduces the stability and reliability of the system.

In a first aspect, the present invention provides a circuit for efficiently implementing pseudo-DDR signals across clock domains, the circuit comprising:

a chip-side high-frequency clock domain module, a plurality of cross-clock domain modules disposed on the chip-side high-frequency clock domain module, and a host-side low-frequency clock domain module connected to the plurality of the cross-clock domain modules;

Each of the cross-clock domain modules includes a low-frequency to high-frequency transmission sub-module and a high-frequency to low-frequency transmission sub-module. One end of the low-frequency to high-frequency transmission sub-module is connected to the chip-side high-frequency clock domain module, and the other end is connected to the chip-side high-frequency clock domain module. is connected to the host-side low-frequency clock domain module, one end of the high-frequency to low-frequency transmission sub-module is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module;

The low frequency to high frequency transmission sub-module is used for, in the case of receiving the write control signal and the write data signal corresponding to the write operation command issued by the low frequency clock domain module of the host side, to transfer the write control signal and the write data signal. The data signals are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write sending data signals to the chip-side high-frequency clock domain module;

The high frequency to low frequency transmission sub-module is configured to, in the case of receiving a read data signal corresponding to a read operation command issued by the host-side low frequency clock domain module, complete reading of corresponding data based on the read data signal.

In the case of adopting the above technical solution, the embodiment of the present invention provides a circuit for efficiently implementing pseudo-DDR signals across the clock domain. In the case of the write control signal and the write data signal corresponding to the operation command, adjust the write control signal and the write data signal from the low frequency clock domain to the high frequency clock domain, respectively, and adjust the adjusted write control signal and the write data signal. The write data signal is synchronously aligned, and the synchronously aligned write control signal and the write data signal are sent to the chip-side high-frequency clock domain module; the high-frequency to low-frequency transmission sub-module is used for , in the case of receiving the read data signal corresponding to the read operation command issued by the host-side low-frequency clock domain module, the reading of the corresponding data is completed based on the read data signal, and the data between single-cycle and multi-cycle signals can be processed at the same time. Scenarios with high timing requirements, such as synchronous cross-clock domain propagation, have a wide range of application scenarios and can be applied to bidirectional cross-clock domain propagation of a large number of signals from low-frequency domain to high-frequency domain or the opposite direction, avoiding metastable multi-domain propagation. The stability and reliability of the circuit are improved.

In a possible implementation manner, the low frequency to high frequency transmission sub-module includes an asynchronous FIFO control signal transmission unit and a data signal transmission unit, one end of the asynchronous FIFO control signal transmission unit and the chip end The high-frequency clock domain module is connected, the other end is connected to the host-side low-frequency clock domain module, one end of the data signal transmission unit is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module connection;

The low frequency to high frequency transmission sub-module is used for, in the case of receiving the write control signal and the write data signal corresponding to the write operation command issued by the low frequency clock domain module of the host side, to transfer the write control signal and the write data signal. The data signals are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write The data signal is sent to the chip-side high-frequency clock domain module, including:

The asynchronous FIFO control signal transmission unit is configured to adjust the write control signal from the low frequency clock domain in the case of receiving the write control signal corresponding to the write operation command issued by the host-side low frequency clock domain module to the high frequency clock domain;

The data signal transmission unit is configured to adjust the write data signal from the low frequency clock domain to the high frequency clock in the case of receiving the write data signal corresponding to the write operation command issued by the host-side low frequency clock domain module area;

The asynchronous FIFO control signal transmission unit and the data signal transmission unit are further configured to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and align the synchronously aligned write The control signal and the write data signal are sent to the chip-side high-frequency clock domain module.

In a possible implementation manner, the circuit further includes a plurality of memory modules, the memory modules are arranged on the chip-side high-frequency clock domain module, and the plurality of the memory modules respectively correspond to each of the cross-clocks Domain modules are connected one by one.

In a possible implementation manner, the asynchronous FIFO control signal transmission unit is configured to, in the case of receiving a write control signal corresponding to the write operation command sent by the host-side low-frequency clock domain module, transmit the The write control signal is adjusted from the low frequency clock domain to the high frequency clock domain, including:

The asynchronous FIFO control signal transmission unit is configured to, in the case of receiving the write control signal corresponding to the write operation command sent by the host-side low-frequency clock domain module, according to a preset first transmission depth value, when it is detected that the asynchronous FIFO control signal transmission unit is in a preset normal state, write the write control signal into the asynchronous FIFO control signal transmission unit;

The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state.

In a possible implementation manner, the data signal transmission unit is configured to, when receiving a write data signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, transmit the write data signal Adjustment from the low frequency clock domain to the high frequency clock domain, including:

The data signal transmission unit is configured to, in the case of receiving the write data signal sent by the host-side low-frequency clock domain module, determine the write data transmission corresponding to each transmission according to a preset second transmission depth value signal, store the write data transmission signal in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and store all the write data transmission signals from the data in the order of storage and writing The transfer units are sequentially read out.

In a second aspect, the present invention also provides a method for efficiently implementing a pseudo DDR signal crossing a clock domain, which is applied to any of the circuits for efficiently implementing a pseudo DDR signal crossing a clock domain in the first aspect, and the method includes:

When the low-frequency to high-frequency transmission sub-module receives the write control signal and the write data signal corresponding to the write operation command issued by the host-side low-frequency clock domain module, the write control signal and the write data signal are respectively transferred from the low-frequency clock domain to the write control signal and the write data signal. Adjust to the high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the synchronously aligned write control signal and the write data signal to the chip-side high frequency clock domain module;

The high frequency to low frequency transmission sub-module completes reading of the corresponding data based on the read data signal in the case of receiving the read data signal corresponding to the read operation command issued by the host-side low frequency clock domain module.

In a possible implementation manner, the low-frequency to high-frequency transmission sub-module includes an asynchronous FIFO control signal transmission unit and a data signal transmission unit, and the low-frequency to high-frequency transmission sub-module receives the host-side low frequency When the clock domain module sends the write control signal and the write data signal corresponding to the write operation command, the write control signal and the write data signal are respectively adjusted from the low-frequency clock domain to the high-frequency clock domain, and all the adjusted signals are adjusted. The write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write data signal are sent to the chip-side high-frequency clock domain module, including:

The asynchronous FIFO control signal transmission unit adjusts the write control signal from the low frequency clock domain to the high frequency when receiving the write control signal corresponding to the write operation command issued by the host-side low frequency clock domain module clock domain;

The data signal transmission unit adjusts the write data signal from the low frequency clock domain to the high frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the host-side low frequency clock domain module;

The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and synchronously align the write control signal and all the write data signals. The write data signal is sent to the chip-side high-frequency clock domain module.

In a possible implementation manner, the asynchronous FIFO control signal transmission unit sends the write control signal to the The signal is adjusted from the low frequency clock domain to the high frequency clock domain, including:

In the case that the asynchronous FIFO control signal transmission unit receives the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, according to the preset first transmission depth value, When detecting that the asynchronous FIFO control signal transmission unit is in a preset normal state, write the write control signal into the asynchronous FIFO control signal transmission unit;

The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state.

In a possible implementation manner, the data signal transmission unit transmits the write data signal from the low-frequency clock to the write data signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module. domain adjusted to the high frequency clock domain, including:

In the case of receiving the write data signal sent by the low-frequency clock domain module of the host side, the data signal transmission unit determines the corresponding write data transmission signal for each transmission according to the preset second transmission depth value, The write data transmission signal is stored in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and all the write data transmission signals are stored and written in sequence from the data transmission unit. read out.

The beneficial effect of the method for efficiently implementing the pseudo DDR signal crossing the clock domain provided by the second aspect is the same as the beneficial effect of the circuit for efficiently implementing the pseudo DDR signal crossing the clock domain described in the first aspect or any possible implementation manner of the first aspect. No further elaboration here.

In a third aspect, the present invention also provides an electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon, when executed by the one or more processors , so that the apparatus executes the method for efficiently implementing the pseudo DDR signal crossing the clock domain described in any possible implementation manner of the second aspect.

The beneficial effects of the electronic device provided in the third aspect are the same as those of the method for efficiently implementing the pseudo DDR signal crossing the clock domain described in the second aspect or any possible implementation manner of the second aspect, and will not be repeated here.

Description of drawings

The accompanying drawings described herein are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

FIG. 1 shows a schematic structural diagram of a circuit for efficiently implementing a pseudo DDR signal across clock domains provided by an embodiment of the present application;

FIG. 2 shows an operation timing diagram of a write operation signal provided by an embodiment of the present application;

FIG. 3 shows an operation timing diagram of a read operation signal provided by an embodiment of the present application;

4 shows a schematic diagram of waveforms before and after a host-side low-frequency clock domain module to a chip-side high-frequency clock domain module crosses the clock domain according to an embodiment of the present application;

5 shows a schematic diagram of waveforms before and after a chip-side high-frequency clock domain module to a host-side low-frequency clock domain module crosses a clock domain according to an embodiment of the present application;

FIG. 6 shows a schematic flowchart of a method for efficiently implementing a pseudo DDR signal crossing a clock domain provided by an embodiment of the present application;

7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a chip provided by an embodiment of the present invention.

Detailed ways

In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and the sequence of the first threshold is not limited. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like are not necessarily different.

It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

In the present invention, "at least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. The character "/" generally indicates that the associated objects are an "or" relationship. "At least one item(s) below" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (a) of a, b or c may represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a combination of a, b and c Combination, where a, b, c can be single or multiple.

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a common type of memory used as RAM in most modern processors. In order to match the actual application requirements, the pseudo DDR signal simplifies the double-edge transmission characteristics of the standard DDR and simplifies the unnecessary DDR regulations according to the application scenario, such as fixing the burst length, canceling the uncommon DDR signal and so on. However, considering that pseudo DDR still has bidirectional cross-domain propagation signals, and there is a synchronous cross-domain propagation problem between specific read/write (Read/Write) commands and the data transmitted therewith. Therefore, the above-mentioned key cross-clock domain propagation problems can be efficiently solved, and the propagation of metastable states between different clock domains can be avoided on the basis of realizing the basic functions of the system, and the system level disturbance can be reduced, so as to improve the system stability and reliability. The invention has a wide range of application prospects in the era of VLSI with increasingly complex functions in the future.

FIG. 1 shows a schematic structural diagram of a circuit for efficiently implementing a pseudo DDR signal crossing a clock domain provided by an embodiment of the present application. As shown in FIG. 1 , the circuit for efficiently implementing a pseudo DDR signal crossing a clock domain includes:

A chip-side high-frequency clock domain module 101 , a plurality of cross-clock domain modules 102 disposed on the chip-side high-frequency clock domain module 101 , and a host-side low-frequency clock domain module connected to the plurality of the cross-clock domain modules 102 103;

Each of the cross-clock domain modules 102 includes a low-frequency to high-frequency transmission sub-module 1021 and a high-frequency to low-frequency transmission sub-module 1022, one end of the low-frequency to high-frequency transmission sub-module 1021 and the chip-side high-frequency clock domain module 101 is connected, the other end is connected to the host-side low-frequency clock domain module 103, one end of the high-frequency to low-frequency transmission sub-module 1022 is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the host-side low frequency clock domain module 101. The clock domain module 103 is connected.

The low frequency to high frequency transmission sub-module is used for, in the case of receiving the write control signal and the write data signal corresponding to the write operation command issued by the low frequency clock domain module of the host side, to transfer the write control signal and the write data signal. The data signals are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write sending data signals to the chip-side high-frequency clock domain module;

The high frequency to low frequency transmission sub-module is configured to, in the case of receiving a read data signal corresponding to a read operation command issued by the host-side low frequency clock domain module, complete reading of corresponding data based on the read data signal.

In this application, the high frequency to low frequency transmission sub-module 1022 includes a first-in, first-out queue (QUEUE) 1022A.

In the circuit for efficiently realizing the pseudo-DDR signal crossing the clock domain provided by the embodiment of the present invention, the low-frequency to high-frequency transmission sub-module is used to receive a write control signal corresponding to a write operation command issued by the host-side low-frequency clock domain module and In the case of writing a data signal, the write control signal and the write data signal are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned. processing, sending the write control signal and the write data signal after synchronization and alignment processing to the chip-side high-frequency clock domain module; the high-frequency to low-frequency transmission sub-module is used to receive the host-side When the low-frequency clock domain module issues a read data signal corresponding to a read operation command, the reading of the corresponding data is completed based on the read data signal, and the synchronization between single-cycle and multi-cycle signals can be processed simultaneously across the clock domain. The required scenarios have a wide range of application scenarios and can be applied to the bidirectional cross-clock domain propagation of a large number of signals from the low frequency domain to the high frequency domain or the opposite direction, avoiding the multi-domain propagation of metastable stability and improving the stability and reliability of the circuit. sex.

Optionally, referring to FIG. 1, the circuit further includes a plurality of memory modules 104, the memory modules 104 are arranged on the chip-side high-frequency clock domain module 101, and the plurality of the memory modules 104 are respectively connected to each of the memory modules 104. The cross-clock domain modules 102 are connected in one-to-one correspondence.

Optionally, referring to FIG. 1 , the low frequency to high frequency transmission sub-module 1021 includes an asynchronous FIFO control signal transmission unit 1021A and a data signal transmission unit 1021B, one end of the asynchronous FIFO control signal transmission unit 1021A and all The chip-side high-frequency clock domain module 101 is connected, the other end is connected to the host-side low-frequency clock domain module 103, one end of the data signal transmission unit 1021B is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the chip-side high-frequency clock domain module 101. It is connected to the host-side low-frequency clock domain module 103 .

The asynchronous FIFO control signal transmission unit is configured to adjust the write control signal from the low frequency clock domain in the case of receiving the write control signal corresponding to the write operation command issued by the host-side low frequency clock domain module to the high frequency clock domain;

The data signal transmission unit is configured to adjust the write data signal from the low frequency clock domain to the high frequency clock in the case of receiving the write data signal corresponding to the write operation command issued by the host-side low frequency clock domain module area;

The asynchronous FIFO control signal transmission unit and the data signal transmission unit are further configured to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and align the synchronously aligned write The control signal and the write data signal are sent to the chip-side high-frequency clock domain module.

The host-side low-frequency clock domain module may be HOST, where HOST is a 100-MHz low-frequency clock, and the chip-side high-frequency clock domain module may be DEVICE, where DEVICE is a 400-MHz high-frequency clock.

When the host-side low-frequency clock domain module performs a write (WRITE) operation, the HOST side will send a control (WRITE) signal, a synchronous data (DATA) signal, and a non-read non-write (NOP) signal to the DEVICE side. READ) operation, the DEVICE terminal will only send a data signal to the HOST terminal.

Optionally, FIG. 2 shows an operation timing diagram of a write operation signal provided by an embodiment of the present application. As shown in FIG. 2 , the CTRL signal lasts for one clock cycle, followed by several cycles of NOP operations. During the write operation, the HOST terminal sends a WRITE signal, and 8 cycles of DATA data will be sent to the DEVICE terminal synchronously when the WRITE command is sent, and no other commands other than the NOP command will be sent until the DATA data is sent, and the signal odt =1 indicates that DATA is written to DEVICE by HOST.

Optionally, FIG. 3 shows an operation timing diagram of a read operation signal provided by an embodiment of the present application. As shown in FIG. 3 , there is only 8 consecutive cycles of DATA signal transmission from DEVICE to HOST, and there is no such direction. CTRL signal transmission, read valid signal rdvalid=1 indicates that DATA is read to HOST by DEVICE.

It should be noted that the basic requirements for cross-time domain can include: the signal period before and after CDC remains unchanged, the WRITE instruction and the transmitted DATA signal are kept aligned before and after CDC, and the DATA data in the WRITE and READ processes are determined by the odt and rdvalid signals respectively. control.

Signals from HOST to DEVICE across the clock domain may include: ddr4_cke, ddr4_cs_n, ddr4_act_n, ddr4_adr[16:0], ddr4_bg[2:0], ddr4_c[2:0], ddr4_ba[1:0], ddr4_odt, ddr4_dq[ 7:0], ddr4_dm_n, and ddr4_dqs.

The signals from DEVICE to HOST across the clock domain may include: ddr4_dq[7:0], ddr4_dm_n, ddr4_dqs and rd_valid.

Optionally, the asynchronous first-in-first-out control signal transmission unit in this application is also an asynchronous FIFO (first-in-first-out queue, First Input First Output). Asynchronous FIFO is a first-in, first-out circuit that can store buffered and then synchronize data in two different clock domains. Asynchronous FIFO is two completely independent clock domains, write clock domain and read clock domain. The clock signal of the write clock domain is wclk , the asynchronous reset signal is reset_n. The winc signal is an enable signal that controls whether to write wdata to the FIFO.

When the FIFO is full, the wfull signal will be pulled up to be active high until the data in the FIFO is read from the read clock domain to make the FIFO not empty, then wfull will be pulled low again. The signal definitions for the read clock domain are similar to the write clock domain. If the empty signal is pulled high, it means that the data in the FIFO has been completely read at this time, until the write clock domain re-writes the data into the FIFO, then the empty will be pulled low again. The awfull and arempty signals in the asynchronous FIFO are used to indicate that only one size verse in the FIFO will be filled or read empty at this time, and the awfull and arempty signals are also high-effective outputs.

When the HOST issues a write operation (ddr4adr=10000), see Figure 2, the HOST end will send a cycle of write control signals to the DEVICE end, and 8 cycles of write data signals will be sent synchronously with it. The control signal and the write data signal are processed across the clock domain from the low frequency domain to the high frequency domain respectively, and then the two are synchronized and aligned.

Optionally, the asynchronous FIFO control signal transmission unit is configured to, in the case of receiving the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, according to a preset For the first transmission depth value, when it is detected that the asynchronous FIFO control signal transmission unit is in a preset normal state, the write control signal is written into the asynchronous FIFO control signal transmission unit;

The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state.

Specifically, the CTRL (control) signal has a certain duration, not burst transmission like the DATA signal. Therefore, by setting an appropriate FIFO depth, when it is detected that the FIFO is not full and is not in the NOP state, the winc signal is set to Set to 1 to allow wdata to be written to the FIFO from the write clock domain. The rinc signal is set to 1 as long as it detects that the FIFO is not empty, and the rinc signal can only be kept valid for one cycle, so that the real-time processing of the CTRL signal across the clock domain can be realized. That is, as long as a cycle non-NOP instruction is written in the FIFO, the instruction in the FIFO is read out, and the read instruction is also valid for one cycle. Since the clock frequency changes before and after the clock domain, in order to ensure that the rinc Only one cycle is valid. On the basis of setting rinc to 1 when detecting that the FIFO is not empty, a level pulse conversion (rising edge detection) circuit can also be added to control only one cycle of rinc being active high.

Optionally, the data signal transmission unit is configured to, in the case of receiving the write data signal sent by the host-side low-frequency clock domain module, determine the corresponding value of each transmission according to a preset second transmission depth value. store the write data transmission signal in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and store all the write data transmission signals in the order of storage and writing Sequentially read from the data transfer unit.

In this application, the data transmission unit may be a QUEUE.

Specifically, when odt=1, DATA is transmitted from HOST to DEVICE. The characteristic of the DATA signal is that it is bursty. Only when the HOST terminal sends a specific WRITE command will data be transmitted, and the length of each burst transmission is fixed as 8. To use the FIFO as a QUEUE, first set the depth of the FIFO to the burst length, which can be a definite value of 8, that is, the second transmission depth value can be 8, and store 8 units of DATA for each burst transmission in the FIFO for stability. After 8 units of data are all entered into the QUEUE, the QUEUE is marked as full (wfull=1), and then the DATA is read out from the QUEUE in the order in which it was written from the write clock domain.

After completing the CDC transmission of the CTRL signal and the DATA signal respectively, align the WRITE command of a specific cycle with the DATA signal of 8 cycles to complete the coordinated transmission of the CTRL signal and the DATA signal. Since the DATA signal is temporarily in the QUEUE Storage will cause a certain delay, so it has a certain delay characteristic. Therefore, the DATA signal cannot be advanced to the same cycle as each WRITE command to start transmission. Based on this, the WRITE command can be delayed until the same cycle as the DATA command. to transmit. Since the readout of the DATA signal is conditional on rinc=1, rinc=1 can be used as the readout condition of the CTRL signal to synchronize the CTRL and DATA signals to complete the cross-clock domain processing from HOST to DEVICE.

The high frequency to low frequency transmission sub-module is configured to, in the case of receiving a read data signal corresponding to a read operation command issued by the host-side low frequency clock domain module, complete reading of corresponding data based on the read data signal.

In this application, the high frequency to low frequency transmission sub-module may include QUEUE. When a read operation occurs, it is a cross-clock domain processing from the DEVICE high frequency domain to the HOST low frequency domain. The data transmission from the DEVICE end to the HOST end has a certain Burst, when DEVICE continuously transmits 8 cycles of DATA data to HOST, FIFO is used as the function of QUEUE, all data is temporarily stored in QUEUE, and then the data in QUEUE is sequentially read from DEVICE. Because the clock frequency of the DEVICE side is higher than that of the HOST side, the speed at which the QUEUE is full is the same as the reading speed. Therefore, it is necessary to write the next DATA data after all the data in the last QUEUE has been read out, two bursts. The interval between the 8 units of data in the read operation cannot be too small, which can avoid data loss due to the fact that the last data has not been read out and the next written data has arrived, and the cross-clock domain from the DEVICE end to the HOST end is completed. deal with.

The circuit for efficiently realizing pseudo-DDR signals across clock domains of the present application has good configurability, and can simultaneously handle scenarios with high timing requirements such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals, and has a wide range of application scenarios. It is applied to the bidirectional cross-clock domain propagation of a large number of signals from the low frequency domain to the high frequency domain or the opposite direction, avoiding the multi-domain propagation of the metastable state, and improving the stability and reliability of the system.

4 shows a schematic diagram of waveforms before and after a host-side low-frequency clock domain module to a chip-side high-frequency clock domain module crosses the clock domain according to an embodiment of the present application. In the HOST to DEVICE cross-clock domain mode, the CTRL signal and the After the CDC transmission of the DATA signal, align the WRITE command of a specific cycle with the DATA signal of 8 cycles to complete the coordinated transmission of the CTRL signal and the DATA signal. Because the DATA signal is temporarily stored in the QUEUE, it will cause a certain delay. Therefore, it has a certain delay characteristic. Therefore, the DATA signal cannot be transmitted in advance to the same cycle as each WRITE command. Based on this, the WRITE command can be delayed until the same cycle as the DATA command before transmission. Since the readout of the DATA signal is conditional on rinc=1, rinc=1 can be used as the readout condition of the CTRL signal to synchronize the CTRL and DATA signals to complete the cross-clock domain processing from HOST to DEVICE.

5 shows a schematic diagram of waveforms before and after a chip-side high-frequency clock domain module to a host-side low-frequency clock domain module crosses the clock domain provided by an embodiment of the present application. In the DEVICE to HOST cross-clock domain mode, when a read operation occurs , is the cross-clock domain processing from the high-frequency domain of DEVICE to the low-frequency domain of HOST. The data transmission from the DEVICE end to the HOST end has a certain burstiness. When DEVICE continuously bursts 8 cycles of DATA data to the HOST, the FIFO Used as the function of QUEUE, all data is temporarily stored in QUEUE, and then the data in QUEUE is sequentially read from the DEVICE side. Because the clock frequency of the DEVICE side is higher than that of the HOST side, the speed at which the QUEUE is full is the same as the reading speed. Therefore, it is necessary to write the next DATA data after all the data in the last QUEUE has been read out, two bursts. The interval between the 8 units of data in the read operation cannot be too small, that is, before the arrival of the next written data, it is ensured that the currently written data has been read. Restrictions, you can make specific adjustments according to the actual application scenario, you can avoid the data loss that occurs when the last data has not been read, and the next written data has arrived, and complete the cross-clock domain processing from the DEVICE side to the HOST side.

In the circuit for efficiently realizing the pseudo-DDR signal crossing the clock domain provided by the embodiment of the present invention, the low-frequency to high-frequency transmission sub-module is used to receive a write control signal corresponding to a write operation command issued by the host-side low-frequency clock domain module and In the case of writing a data signal, the write control signal and the write data signal are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned. processing, sending the write control signal and the write data signal after synchronization and alignment processing to the chip-side high-frequency clock domain module; the high-frequency to low-frequency transmission sub-module is used to receive the host-side When the low-frequency clock domain module issues a read data signal corresponding to a read operation command, the reading of the corresponding data is completed based on the read data signal, and the synchronization between single-cycle and multi-cycle signals can be processed simultaneously across the clock domain. The required scenarios have a wide range of application scenarios and can be applied to the bidirectional cross-clock domain propagation of a large number of signals from the low frequency domain to the high frequency domain or the opposite direction, avoiding the multi-domain propagation of metastable stability and improving the stability and reliability of the circuit. sex.

FIG. 6 shows a schematic flowchart of a method for efficiently implementing a pseudo DDR signal crossing a clock domain provided by an embodiment of the present application, which is applied to the circuit for efficiently implementing a pseudo DDR signal crossing a clock domain shown in FIG. 1 , as shown in FIG. 6 . As shown in the figure, the method for efficiently realizing the pseudo DDR signal crossing the clock domain includes:

Step 201: In the case where the low-frequency to high-frequency transmission sub-module receives the write control signal and the write data signal corresponding to the write operation command issued by the host-side low-frequency clock domain module, the write control signal and the write data signal are respectively sent from the host side to the write control signal and the write data signal. The low-frequency clock domain is adjusted to the high-frequency clock domain, the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write data signal are sent to the Chip-side high-frequency clock domain module.

Optionally, the specific implementation of step 201 may include the following sub-steps:

Sub-step S1: the asynchronous FIFO control signal transmission unit transmits the write control signal from the low-frequency clock domain to the low-frequency clock domain when receiving the write control signal corresponding to the write operation command issued by the host-side low-frequency clock domain module. Adjusted to the high frequency clock domain;

Optionally, when the asynchronous FIFO control signal transmission unit receives the write control signal corresponding to the write operation command sent by the host-side low-frequency clock domain module, the transmission a depth value, when it is detected that the asynchronous FIFO control signal transmission unit is in a preset normal state, write the write control signal into the asynchronous FIFO control signal transmission unit;

The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state.

Sub-step S2: the data signal transmission unit adjusts the write data signal from the low frequency clock domain to the high frequency when receiving the write data signal corresponding to the write operation command issued by the host-side low frequency clock domain module clock domain;

In the case of receiving the write data signal sent by the low-frequency clock domain module of the host side, the data signal transmission unit determines the corresponding write data transmission signal for each transmission according to the preset second transmission depth value, The write data transmission signal is stored in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and all the write data transmission signals are stored and written in sequence from the data transmission unit. read out.

Sub-step S3: the asynchronous FIFO control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and synchronously align the write The control signal and the write data signal are sent to the chip-side high-frequency clock domain module.

Step 202 : the high frequency to low frequency transmission sub-module completes the reading of the corresponding data based on the read data signal in the case of receiving the read data signal corresponding to the read operation command issued by the host-side low frequency clock domain module.

The embodiment of the present invention provides a method for efficiently implementing a pseudo-DDR signal across a clock domain, wherein the low-frequency to high-frequency transmission sub-module receives a write control signal and a write data signal corresponding to a write operation command issued by the host-side low-frequency clock domain module In the case of , the write control signal and the write data signal are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned. The write control signal and the write data signal after synchronous alignment processing are sent to the chip-side high-frequency clock domain module; the high-frequency to low-frequency transmission sub-module receives a read from the host-side low-frequency clock domain module In the case of the read data signal corresponding to the operation command, the reading of the corresponding data is completed based on the read data signal, and the scenarios with high timing requirements such as synchronization between single-cycle and multi-cycle signals can be simultaneously processed across clock domains, and its application It has a wide range of scenarios and can be applied to the bidirectional cross-clock domain propagation of a large number of signals from the low frequency domain to the high frequency domain or the opposite direction, avoiding the multi-domain propagation of metastable stability and improving the stability and reliability of the circuit.

The method for efficiently realizing the pseudo DDR signal crossing the clock domain provided by the present invention is applied to the circuit for efficiently realizing the pseudo DDR signal crossing the clock domain as shown in FIG.

The electronic device in this embodiment of the present invention may be an apparatus, or may be a component, an integrated circuit, or a chip in a terminal. The apparatus may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant). , PDA), etc., the non-mobile electronic device may be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc. The embodiment of the present invention There is no specific limitation.

The electronic device in the embodiment of the present invention may be a device having an operating system. The operating system may be an Android (Android) operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present invention.

FIG. 7 shows a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present invention. As shown in FIG. 7 , the electronic device 300 includes a processor 310 .

As shown in FIG. 7 , the above-mentioned processor 310 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more for controlling the The integrated circuit in which the program of the invention scheme is executed.

As shown in FIG. 7 , the above-mentioned electronic device 300 may further include a communication line 340 . Communication line 340 may include a path to communicate information between the aforementioned components.

Optionally, as shown in FIG. 7 , the above electronic device may further include a communication interface 320 . The communication interface 320 may be one or more. Communication interface 320 may use any transceiver-like device for communicating with other devices or communication networks.

Optionally, as shown in FIG. 7 , the electronic device may further include a memory 330 . The memory 330 is used to store computer-executable instructions for implementing the solutions of the present invention, and the execution is controlled by the processor. The processor is configured to execute the computer-executed instructions stored in the memory, thereby implementing the method provided by the embodiments of the present invention.

As shown in FIG. 7, the memory 330 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or a random access memory (RAM) that can store Other types of dynamic storage devices for information and instructions, which can also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM), or other Optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or capable of carrying or storing desired programs in the form of instructions or data structures code and any other medium that can be accessed by a computer, without limitation. The memory 330 may exist independently and be connected to the processor 310 through a communication line 340 . The memory 330 may also be integrated with the processor 310 .

Optionally, the computer-executed instructions in this embodiment of the present invention may also be referred to as application code, which is not specifically limited in this embodiment of the present invention.

In a specific implementation, as an embodiment, as shown in FIG. 7 , the processor 310 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 7 .

In a specific implementation, as an embodiment, as shown in FIG. 7 , the terminal device may include multiple processors, such as the first processor 3101 and the second processor 3102 in FIG. 7 . Each of these processors can be a single-core processor or a multi-core processor.

FIG. 8 is a schematic structural diagram of a chip provided by an embodiment of the present invention. As shown in FIG. 8 , the chip 400 includes one or more than two (including two) processors 310 .

Optionally, as shown in FIG. 8 , the chip further includes a communication interface 320 and a memory 330. The memory 330 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 8, the memory 330 stores the following elements, execution modules or data structures, or a subset thereof, or an extended set thereof.

In this embodiment of the present invention, as shown in FIG. 8 , corresponding operations are performed by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system).

As shown in FIG. 8 , the processor 310 controls the processing operation of any one of the terminal devices, and the processor 310 may also be referred to as a central processing unit (central processing unit, CPU).

As shown in FIG. 8, memory 330 may include read only memory and random access memory, and provide instructions and data to the processor. A portion of memory 330 may also include NVRAM. For example, in an application, the memory, the communication interface, and the memory are coupled together through a bus system, where the bus system may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. However, for clarity of illustration, the various buses are labeled as bus system 450 in FIG. 8 .

As shown in FIG. 8 , the methods disclosed in the above embodiments of the present invention may be applied to a processor, or implemented by a processor. A processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above-mentioned method can be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software. The above-mentioned processor may be a general-purpose processor, a digital signal processing (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Various methods, steps, and logical block diagrams disclosed in the embodiments of the present invention can be implemented or executed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present invention may be directly embodied as executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.

In one aspect, a computer-readable storage medium is provided, where instructions are stored in the computer-readable storage medium, and when the instructions are executed, the functions performed by the terminal device in the foregoing embodiments are implemented.

On the one hand, a chip is provided, the chip is applied in a terminal device, the chip includes at least one processor and a communication interface, the communication interface is coupled with the at least one processor, and the processor is used for running instructions, so as to realize the high-efficiency implementation in the above-mentioned embodiment. Pseudo DDR signaling functions performed by circuits that span clock domains.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are performed. The computer may be a general purpose computer, special purpose computer, computer network, terminal, user equipment, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be downloaded from a website site, computer, A server or data center transmits by wire or wireless to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, data center, or the like that integrates one or more available media. The usable media may be magnetic media, such as floppy disks, hard disks, magnetic tapes; optical media, such as digital video discs (DVD); and semiconductor media, such as solid state drives (solid state drives). , SSD).

Although the invention is described herein in connection with various embodiments, in practicing the claimed invention, those skilled in the art can understand and implement the disclosure by reviewing the drawings, the disclosure, and the appended claims Other variations of the embodiment. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

Although the invention has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims, and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. a circuit for efficiently realizing pseudo DDR signal crossing clock domain, it is characterized in that, described circuit comprises: a chip-side high-frequency clock domain module, a plurality of cross-clock domain modules disposed on the chip-side high-frequency clock domain module, and a host-side low-frequency clock domain module connected to the plurality of the cross-clock domain modules; Each of the cross-clock domain modules includes a low-frequency to high-frequency transmission sub-module and a high-frequency to low-frequency transmission sub-module. One end of the low-frequency to high-frequency transmission sub-module is connected to the chip-side high-frequency clock domain module, and the other end is connected to the chip-side high-frequency clock domain module. is connected to the host-side low-frequency clock domain module, one end of the high-frequency to low-frequency transmission sub-module is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; The low frequency to high frequency transmission sub-module is used for, in the case of receiving the write control signal and the write data signal corresponding to the write operation command issued by the low frequency clock domain module of the host side, to transfer the write control signal and the write data signal. The data signals are respectively adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write sending data signals to the chip-side high-frequency clock domain module; The high frequency to low frequency transmission sub-module is configured to, in the case of receiving a read data signal corresponding to a read operation command issued by the host-side low frequency clock domain module, complete reading of corresponding data based on the read data signal. 2 . The circuit for efficiently implementing pseudo-DDR signals across clock domains according to claim 1 , wherein the low-frequency to high-frequency transmission sub-module comprises an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit, 2 . One end of the asynchronous FIFO control signal transmission unit is connected to the chip-side high-frequency clock domain module, the other end is connected to the host-side low-frequency clock domain module, and one end of the data signal transmission unit is connected to the chip-side high-frequency clock domain module. The clock domain module is connected, and the other end is connected with the low-frequency clock domain module on the host side; The low frequency to high frequency transmission sub-module is used for, in the case of receiving the write control signal and the write data signal corresponding to the write operation command issued by the low frequency clock domain module of the host side, to transfer the write control signal and the write data signal. The data signal is adjusted from the low frequency clock domain to the high frequency clock domain, and the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write The data signal is sent to the chip-side high-frequency clock domain module, including: The asynchronous FIFO control signal transmission unit is configured to adjust the write control signal from the low frequency clock domain in the case of receiving the write control signal corresponding to the write operation command issued by the host-side low frequency clock domain module to the high frequency clock domain; The data signal transmission unit is configured to adjust the write data signal from the low frequency clock domain to the high frequency clock in the case of receiving the write data signal corresponding to the write operation command issued by the host-side low frequency clock domain module area; The asynchronous FIFO control signal transmission unit and the data signal transmission unit are further configured to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and align the synchronously aligned write The control signal and the write data signal are sent to the chip-side high-frequency clock domain module. 3 . The circuit for efficiently implementing pseudo-DDR signals across clock domains according to claim 2 , wherein the circuit further comprises a plurality of memory modules, and the memory modules are arranged on the chip-side high-frequency clock domain module. 4 . , and a plurality of the memory modules are respectively connected to each of the clock domain-crossing modules in a one-to-one correspondence. 4 . The circuit for efficiently implementing pseudo-DDR signals across clock domains according to claim 3 , wherein the asynchronous FIFO control signal transmission unit is used to transmit the signal sent by the host-side low-frequency clock domain module after receiving the signal. 5 . In the case of the write control signal corresponding to the write operation instruction, adjusting the write control signal from the low-frequency clock domain to the high-frequency clock domain, including: The asynchronous FIFO control signal transmission unit is configured to, in the case of receiving the write control signal corresponding to the write operation command sent by the host-side low-frequency clock domain module, according to a preset first transmission depth value, when it is detected that the asynchronous FIFO control signal transmission unit is in a preset normal state, write the write control signal into the asynchronous FIFO control signal transmission unit; The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state. 5 . The circuit for efficiently implementing pseudo-DDR signals across clock domains according to claim 4 , wherein the data signal transmission unit is configured to issue the write operation instruction after receiving the host-side low-frequency clock domain module. 6 . In the case of the corresponding write data signal, adjusting the write data signal from the low frequency clock domain to the high frequency clock domain, including: The data signal transmission unit is configured to, in the case of receiving the write data signal sent by the host-side low-frequency clock domain module, determine the write data transmission corresponding to each transmission according to a preset second transmission depth value signal, store the write data transmission signal in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and store all the write data transmission signals from the data in the order of storage and writing The transfer units are read out sequentially. 6. A method for efficiently realizing a pseudo DDR signal crossing a clock domain, characterized in that, applied to the circuit for efficiently realizing a pseudo DDR signal crossing a clock domain according to any one of claims 1 to 5, the method comprising: When the low-frequency to high-frequency transmission sub-module receives the write control signal and the write data signal corresponding to the write operation command issued by the host-side low-frequency clock domain module, the write control signal and the write data signal are respectively transferred from the low-frequency clock domain to the write control signal and the write data signal. Adjust to the high-frequency clock domain, perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the synchronously aligned write control signal and the write data signal to the chip-side high frequency clock domain module; The high frequency to low frequency transmission sub-module completes reading of the corresponding data based on the read data signal in the case of receiving the read data signal corresponding to the read operation command issued by the host-side low frequency clock domain module. 7 . The method for efficiently implementing pseudo-DDR signals across clock domains according to claim 6 , wherein the low-frequency to high-frequency transmission sub-module comprises an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit. 8 . When the low frequency to high frequency transmission sub-module receives the write control signal and the write data signal corresponding to the write operation command issued by the host-side low frequency clock domain module, the write control signal and the write data signal are respectively changed from the low frequency to the low frequency. The clock domain is adjusted to the high-frequency clock domain, the adjusted write control signal and the write data signal are synchronously aligned, and the synchronously aligned write control signal and the write data signal are sent to the The chip-side high-frequency clock domain module includes: The asynchronous FIFO control signal transmission unit adjusts the write control signal from the low frequency clock domain to the high frequency when receiving the write control signal corresponding to the write operation command issued by the host-side low frequency clock domain module clock domain; The data signal transmission unit adjusts the write data signal from the low frequency clock domain to the high frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the host-side low frequency clock domain module; The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and synchronously align the write control signal and all the write data signals. The write data signal is sent to the chip-side high-frequency clock domain module. 8 . The method for efficiently implementing pseudo-DDR signals across clock domains according to claim 7 , wherein the asynchronous FIFO control signal transmission unit sends the write operation after receiving the host-side low-frequency clock domain module. 9 . In the case of the write control signal corresponding to the instruction, adjusting the write control signal from the low-frequency clock domain to the high-frequency clock domain, including: In the case that the asynchronous FIFO control signal transmission unit receives the write control signal corresponding to the write operation instruction sent by the host-side low-frequency clock domain module, according to the preset first transmission depth value, When detecting that the asynchronous FIFO control signal transmission unit is in a preset normal state, write the write control signal into the asynchronous FIFO control signal transmission unit; The preset normal state refers to that the asynchronous FIFO control signal transmission unit is not full and not in a non-reading and non-writing state. 9 . The method for efficiently implementing pseudo-DDR signals across clock domains according to claim 8 , wherein the data signal transmission unit sends a write corresponding to the write operation instruction after receiving the host-side low-frequency clock domain module. 10 . In the case of a data signal, adjusting the write data signal from the low-frequency clock domain to the high-frequency clock domain includes: In the case of receiving the write data signal sent by the low-frequency clock domain module of the host side, the data signal transmission unit determines the corresponding write data transmission signal for each transmission according to the preset second transmission depth value, The write data transmission signal is stored in the corresponding memory module until the number of times of transmission reaches the second transmission depth value, and all the write data transmission signals are stored and written in sequence from the data transmission unit. read out. 10. An electronic device, comprising: one or more processors; and one or more machine-readable media having instructions stored thereon that, when executed by the one or more processors, cause The method for efficiently realizing the pseudo DDR signal crossing the clock domain according to any one of claims 6-9 is executed.

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