CN115020205B - A low interface thermal resistance diamond-based wafer and low temperature bonding method thereof - Google Patents
A low interface thermal resistance diamond-based wafer and low temperature bonding method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 44
- 239000010432 diamond Substances 0.000 title claims abstract description 44
- 235000012431 wafers Nutrition 0.000 claims abstract description 107
- 238000000151 deposition Methods 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 230000007704 transition Effects 0.000 claims abstract description 18
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 230000004913 activation Effects 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 claims description 36
- 238000004140 cleaning Methods 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
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- 239000007789 gas Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 230000001105 regulatory effect Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
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- 239000002105 nanoparticle Substances 0.000 claims description 2
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- 238000005137 deposition process Methods 0.000 claims 1
- 229910002601 GaN Inorganic materials 0.000 abstract description 19
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 62
- 239000000758 substrate Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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Abstract
The invention provides a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof, which belong to the technical field of bonding of diamond and gallium nitride, and the method comprises the steps of S1, respectively carrying out surface activation on the diamond and a semiconductor wafer through plasma etching treatment, S2, respectively depositing nanometer-sized gradient layers, S3, inverting one wafer obtained in the step S2 to enable the gradient layers on the two wafers to be in contact with each other, and S4, and then bonding under a bonding condition, wherein the gradient layers sequentially comprise an initial layer, a transition layer and an end layer, the initial layer is at least one of Ti, ta, cr, ni, W, mo nm, the end layer is Ag, the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the end layer is not more than 15nm. The invention has lower interface thermal resistance, high bonding strength and lower bonding environment requirement.
Description
Technical Field
The invention relates to the technical field of bonding of diamond and gallium nitride, in particular to a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof.
Background
Due to the self-heating effect of the GaN-based power device and the low thermal conductivity of the original substrate, the power output capacity is reduced, the stability and the reliability of the device are affected, and the performance of the device is seriously degraded. Diamond, however, has an ultra-high thermal conductivity and a very small coefficient of thermal expansion, and therefore diamond is the preferred substrate material. However, the large lattice mismatch and the difference in thermal expansion coefficient between materials make high quality integration of GaN with diamond quite difficult. The bonding of diamond and GaN is a feasible method, and the principle is that two or more materials are combined into a whole through Van der Waals force, molecular force and even atomic force, so that the integration level of a wafer is improved, and the bonding method is an indispensable important link in the field of semiconductor manufacturing. The bonding of GaN and diamond is a parallel process, a GaN layer and a diamond substrate can be respectively prepared, the low-temperature bonding technology can avoid the difference of lattice mismatch and thermal expansion coefficient generated by growing GaN at high temperature, and simultaneously, the problem of low thermal conductivity of a nucleation layer is avoided. Metal bonding is a promising technique by depositing nanocrystalline metal films on two wafers to be bonded, then bringing the wafer surfaces into contact with each other, and applying a certain temperature and pressure to promote the diffusion of metal atoms and the growth of grains, thereby forming metal bonds between the metal atoms at the bonding interface. The metal bonding can ensure high bonding strength of the bonding interface, and the metal material has high heat conductivity, thereby being beneficial to the reduction of interface thermal resistance. The metal bonding can realize low-temperature bonding, and damage to the device under the high-temperature condition is avoided.
Generally, diamond and GaN are bonded through a metal interlayer, and the requirements of high bonding strength, low interface thermal resistance, low bonding temperature and the like need to be met. For example, the heterogeneous integration method of the diamond-based gallium nitride transistor with high electron mobility, which is reported in the patent CN 109860049A, adopts W and Au as an intermediate layer, has higher bonding strength and good heat dissipation effect, has simple process and does not need harsh conditions such as ultrahigh vacuum, high flatness, high-temperature annealing and the like, and is successfully applied to the preparation of the diamond-based GaN HEMT.
However, in the conventional metal bonding method, the bonding intermediate layer is of a multi-layer structure, so that more interface thermal resistance is possibly generated, and in addition, the bonding strength is difficult to ensure by adopting normal-temperature Au bonding, so that the wafer bonding power is obviously influenced by the processing state of the substrate. Therefore, a bonding system which reduces bonding interfaces as much as possible and has low requirements on bonding environment is developed, and has important significance for the semiconductor material integration process applicable to a heat dissipation system.
Disclosure of Invention
The invention aims to provide a diamond-based wafer with low interface thermal resistance and a low-temperature bonding method thereof, which have the advantages of low interface thermal resistance, high bonding strength and low bonding environment requirements. The method is particularly suitable for the application requirements of the semiconductor material integration field on some temperature sensitive devices. The bonding temperature is low, and the thermal conductivity of the bonding interface is high, so that the method is suitable for integrating semiconductor materials with large difference of thermal expansion coefficients.
In order to solve the technical problems, the invention provides the following technical scheme:
in a first aspect, a low interface thermal resistance diamond-based wafer low temperature bonding method is provided, comprising the steps of:
S1, performing surface activation on diamond and a semiconductor wafer through plasma etching treatment respectively;
s2, respectively depositing nano-sized gradient layers on the surfaces of the diamond activated in the step S1 and the semiconductor wafer;
s3, inverting one wafer obtained in the step S2 to enable the gradient layers on the two wafers to be in contact with each other;
And S4, bonding under the bonding condition.
The diamond is a material with ultrahigh heat conductivity, and the diamond is used as a heat dissipation substrate of a GaN and other power devices, so that the heat dissipation capacity of the near junction region of the devices can be effectively improved, the peak temperature is reduced, and the maximum output power and the reliability of the devices are greatly improved.
Wherein, preferably, the thickness of the diamond is 400-600 μm, and the thickness of the semiconductor wafer is 1-3 μm. This preferred solution is more advantageous for adapting to a specific gradient layer.
The semiconductor wafer may or may not include a substrate, and may be, for example, a semiconductor wafer or a silicon-based semiconductor wafer.
The gradient layer sequentially comprises an initial layer, a transition layer and an end layer, wherein the initial layer is at least one selected from Ti, ta, cr, ni, W, mo, and the end layer is Ag. It is understood that the transition layer is a layer in which the composition of the initial layer element and the end layer Ag is graded.
The thickness of the gradient layer is below 30 nm.
Preferably, the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the end layer is not more than 15nm. With the adoption of the preferable scheme, the influence of the intermediate layer on the performance of the bonded semiconductor material can be reduced to the greatest extent.
Wherein, preferably, the diamond and the semiconductor wafer in the step S1 meet the conditions that the surface flatness is less than 3 mu m and the roughness Rq is less than or equal to 2nm. Under the preferred scheme, the semiconductor substrate material is more suitable for the deposition of the specific gradient layer, so that the interface bonding strength is more improved.
Preferably, the semiconductor wafer is selected from one or more semiconductor materials of GaN, si, ge, gaAs, inP, gaO, siC, alN.
The plasma etching treatment in step S1 may be ICP, RIE or other low-temperature plasma treatment methods. Preferably, the plasma etching process in step S1 is specifically performed by bombarding the surface of the bonded wafer with ICP Ar plasma.
Wherein, the surface activation condition in the step S1 preferably comprises that the RF power is 40-60W under the vacuum degree of 3X 10 -3 Pa, the treatment atmosphere is a protective atmosphere without oxygen, and the treatment time is 40-80S. According to the preferred scheme, the adsorbed gas and the natural oxide layer are more favorably removed, the oxygen atom adsorption of the bonding surface is removed, meanwhile, the surface roughness of the bonding surface is not obviously changed, the bonding strength and bonding power are increased, the surface of the wafer is cleaned, the activation energy is increased, meanwhile, the surface of the wafer has proper flatness and roughness, and the bonding of a specific gradient layer is facilitated. The plasma treatment time should not be too long, and the energy should not be too high, otherwise the surface roughness would be increased.
The protective atmosphere containing no oxygen may be, for example, a non-O-type atmosphere such as Ar, N 2, and H 2.
The low-temperature bonding method preferably further comprises the step of cleaning the surface of the wafer before the step S1, wherein the step of cleaning the surface of the wafer with acetone or isopropanol for 10-30min, the step of cleaning the surface of the wafer with absolute ethyl alcohol for 10-20min, the step of cleaning the surface of the wafer with deionized water for 10-20min, and the step of taking out the wafer after cleaning is finished and drying the wafer with protective gas.
The shielding gas includes, but is not limited to, nitrogen, inert gases, and the like.
In some specific embodiments, the cleaning step specifically comprises the steps of firstly ultrasonically cleaning with acetone or isopropanol for 15 minutes, then ultrasonically cleaning with absolute ethyl alcohol for 10 minutes, finally ultrasonically cleaning with deionized water for 10 minutes, taking out after cleaning, and drying with nitrogen for later use.
The deposition in step S2 may be sputtering or evaporation. Preferably, the deposition in step S2 is a physical vapor deposition method.
The deposition preferably prepares the gradient layer by multi-target reactive magnetron sputtering.
The gradient layer containing the transition layer is arranged, so that the transition layer has no obvious interface, the stress is gradually released, the binding force can be obviously improved, and the stress mismatch between the film layer and the substrate is reduced.
The conditions of low temperature, low power and short time are satisfied during the deposition so as to ensure that the deposited gradient layer is in a proper nano size. Wherein, preferably, the depositing in step S2 includes:
Pre-sputtering under vacuum degree of 5×10 -4 Pa, sputtering power of 90-110W, ar gas flow of 40-60sccm, and pre-sputtering for 10-20min;
Then starting to deposit an initial layer, regulating the flow of argon to 20-30sccm, regulating the sputtering power to 90-110W, regulating the cavity pressure to 0.2-0.4Pa, and regulating the deposition time to 30-50s, thereby completing the initial layer plating process;
Then opening the Ag target to start co-sputtering, gradually increasing the power of the Ag target from 9-12W to 90-110W, gradually reducing the power of the initial layer target from 90-110W to 0W, and completing the deposition of the transition layer, wherein the co-sputtering time is 50-70 s;
And after the co-sputtering is finished, depositing an end layer Ag, keeping the cavity pressure and the argon flow unchanged, and continuing sputtering for 80-200s under the condition of 90-110W to finish the deposition of the end layer. Under the preferred scheme, each layer is more favorable for being uniformly deposited on the whole wafer surface, and a deposition layer with proper grain size and proper thickness can be obtained, so that low-temperature bonding is more favorable.
In the deposition method, the grain size of the deposited nano Ag layer is smaller than 10nm, which is more beneficial to low-temperature bonding.
The step S3 of the invention is used for lamination, and the specific operation can be that one side of the wafer plated with the metal layer is bonded together face to face, the wafer is put into a template with the corresponding wafer size, the template is put into bonding equipment for fixing, and the upper wafer and the lower wafer are aligned by using the template.
Wherein, the bonding condition in the step S4 preferably comprises the following steps of gradually applying pressure to a wafer at the top to enable the pressure to reach 0.1-0.3MPa within 30S under the condition that the ambient vacuum degree is less than 1X 10 -3 Pa, and then simultaneously heating the upper wafer and the lower wafer at the temperature of 200-250 ℃ for 10-20min.
After the bonding is completed, the interface of the intermediate layer is reduced, gradient transition is formed, and the concentration of the element is higher as the element is closer to the initial layer of the wafer, and the concentration of the element is higher as the element is closer to the intermediate Ag.
The specific operation of bonding can be that after the wafer is placed into bonding equipment, parameters such as pressure, temperature, time and the like are designed according to the thickness of the gradient layer. And when pressure is applied to the top of the wafer, bonding, the interior of the device is kept in a vacuum state, the temperature of the upper wafer and the lower wafer is raised, the sample is naturally cooled along with the device after bonding, and the bonding is completed after the sample is taken out, so that the low-temperature metal bonding of the semiconductor material is formed.
Wherein, preferably, the low-temperature bonding method further comprises the step of pre-bonding before the bonding in the step S4:
And under the condition of room temperature and atmosphere, applying 0.1-0.2MPa pressure to a wafer at the top, keeping for 8-12min, gradually reducing the pressure to 0, and completing pre-bonding.
The method of the invention can be popularized to bonding of various semiconductor materials, such as Si/Si bonding, si/diamond bonding, si/GaN bonding and the like, and the condition is optimized according to the specific materials. The period and thickness of the gradient layer can be adjusted according to the stress and the lattice mismatch degree, so that the gradient layer forms a gradient transition of the structure and the stress.
In a second aspect, a low interfacial thermal resistance diamond-based wafer made by the low temperature bonding method of the first aspect is provided.
The bonding strength of the diamond-based wafer is above 5MPa, and the interface bonding rate is more than 95%.
The technical scheme of the invention has the following beneficial effects:
1. The gradient layer with the specific thickness is used as an intermediate layer, has good heat conductivity, can play a role of a heat conducting layer, has high heat conductivity (429W/m.K) of Ag in metal, and can realize the integration process of Si/diamond, gaN/diamond and the like which are suitable for a heat dissipation system.
2. The gradient layer with proper thickness and containing the transition layer is used as transition between the surface layer and the bottom metal, so that multiple interface introduction is reduced, interface scattering in phonon/electron coupling transmission process is prevented, meanwhile, stress gradient change is realized, and bonding strength and interface heat conduction are remarkably improved.
3. The gradient layer for bonding contains nano Ag, the melting point of the deposited nano Ag with proper thickness is very low, and the bonding at the low temperature of normal temperature to 250 ℃ can be realized. The low-temperature bonding method can furthest reduce the mismatch of thermal expansion coefficients among different materials, and avoid the problems of wafer warpage and the like caused by defect generation and stress increase caused by a high-temperature process.
4. The process is simple, the conditions are easy to obtain, and the subsequent high-temperature annealing or ultra-high vacuum environment is not needed. The requirement on the surface roughness of the bonding wafer is low, and the surface does not need complex treatment.
5. Compared with Au-Au bonding, the method has lower cost and higher interface thermal conductivity.
Drawings
FIG. 1 illustrates a raw semiconductor substrate material with a smooth surface;
FIG. 2 shows Ti plating on a smooth raw substrate surface;
FIG. 3 shows plating of a gradient layer on a Ti surface;
fig. 4 shows Ag plating on the gradient layer surface;
Fig. 5 shows the semiconductor material after bonding is completed.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
Example 1
1) Silicon-based gallium nitride and single crystal diamond are used as original substrate wafers, the original substrate is 5mm by 5mm in size, the diamond thickness is 500 mu m, the surface flatness is <3 mu m, the surface roughness Rq=0.4 nm, the silicon-based gallium nitride is prepared on the silicon substrate by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) technology, wherein the gallium nitride layer is 2 mu m in thickness, the surface flatness is <3 mu m, and the surface roughness Rq=0.8 nm. Firstly, cleaning the surface of a wafer, ultrasonically cleaning the surface of the wafer for 15min by adopting isopropanol, then ultrasonically cleaning the surface of the wafer for 10min by transferring the surface of the wafer into absolute ethyl alcohol, finally, transferring the mixture into deionized water, ultrasonically cleaning the mixture for 10 minutes, and drying the mixture for standby by using nitrogen, as shown in figure 1;
2) And (5) ICP argon plasma treatment. Placing the cleaned wafer into ICP equipment, vacuumizing the equipment to a pressure below 3×10 -3 Pa, wherein the RF power is 50W, the treatment atmosphere is argon, and the treatment time is 50s;
3) Ti (5 nm), ti/Ag (10 nm) and Ag (10 nm) films are respectively deposited on the surfaces of the diamond and the GaN by a magnetron sputtering method. Placing two wafers into equipment for sputtering, vacuumizing the equipment to below 5X 10 -4 Pa, pre-sputtering a target material, setting the sputtering power to be 100W, the Ar gas flow to be 50sccm, pre-sputtering for 15min, firstly depositing Ti, adjusting the Ar gas flow to be 23.5sccm, the sputtering power to be 100W, the cavity pressure to be 0.3Pa, and the deposition time to be 40s, completing a Ti plating process, as shown in figure 2, opening an Ag target at the moment, starting co-sputtering, gradually increasing the Ag target power from 10W to 100W, gradually reducing the Ti target power from 100W to 0W, and the co-sputtering time to be 60s, completing transitional film deposition, as shown in figure 3, depositing Ag after co-sputtering, sputtering for 100s under 100W, and completing Ag film deposition, as shown in figure 4;
4) Pre-bonding, namely bonding one sides of a wafer deposited film together face to face, placing the diamond under the GaN on the upper side, placing the wafer into bonding equipment, fixing the wafer through a die, aligning the upper wafer and the lower wafer, and fixing the die into the equipment, wherein the pressure of 0.1MPa is applied to the dome part of the wafer under the condition of room temperature and atmosphere, the pressure is kept for 10 minutes, gradually reduced to 0, and the pre-bonding is completed;
5) And (5) bonding. After the pre-bonding is finished, vacuumizing the equipment to below 1X 10 -3 Pa, gradually applying pressure to the top wafer to reach 0.15MPa within 30 seconds, heating the upper wafer and the lower wafer at the same time, and keeping the temperature at 250 ℃ for 15 minutes under the conditions of the temperature and the pressure;
6) After bonding, heating was stopped, the pressure was gradually reduced, the sample was cooled to 80 ℃ with the apparatus and then removed, and the intermediate layer formed a gradient transition, as shown in fig. 5.
The bonding strength of the obtained diamond-based semiconductor wafer was 6MPa, and the bonding rate was 97%.
Example 2
1) Silicon and polycrystalline diamond are used as an original substrate wafer, the original substrate has the size of 10 multiplied by 10mm, the diamond thickness is 500 mu m, the surface flatness is less than 3 mu m, the surface roughness Rq=0.8 nm, the silicon wafer has the thickness of 625 mu m, the surface flatness is less than 3 mu m, and the surface roughness Rq=0.9 nm. Firstly, cleaning the surface of a wafer, ultrasonically cleaning the surface of the wafer for 15min by adopting isopropanol, then ultrasonically cleaning the surface of the wafer for 10min by transferring the surface of the wafer into absolute ethyl alcohol, finally ultrasonically cleaning the surface of the wafer for 10min by transferring the surface of the wafer into deionized water, and drying the surface of the wafer for later use by using nitrogen;
2) And (5) ICP argon plasma treatment. Placing the cleaned wafer into ICP equipment, vacuumizing the equipment to a pressure below 3×10 -3 Pa, wherein the RF power is 50W, the treatment atmosphere is argon, and the treatment time is 50s;
3) Ti (5 nm), ti/Ag (10 nm) and Ag (15 nm) films are respectively deposited on the surfaces of the diamond and the silicon wafer by adopting a magnetron sputtering method. Placing two wafers into equipment for sputtering, vacuumizing the equipment to below 5X 10 -4 Pa, pre-sputtering a target material, setting the sputtering power to be 100W, the Ar gas flow to be 50sccm, pre-sputtering for 15min, firstly depositing Ti, adjusting the Ar gas flow to be 23.5sccm, the sputtering power to be 100W, the cavity pressure to be 0.3Pa, and the deposition time to be 40s, completing the Ti plating process, opening an Ag target at the moment, starting co-sputtering, gradually adjusting the Ag target power from 10W to 100W, gradually reducing the Ti target power from 100W to 0W, and the co-sputtering time to be 60s, completing transitional film deposition, depositing Ag after the co-sputtering, keeping the parameters unchanged, sputtering for 140s at 100W, and completing the deposition of an Ag film;
4) Pre-bonding, namely bonding one sides of the wafer deposited film face to face, putting the bonded film into bonding equipment, fixing the wafers through a die, aligning the upper wafer and the lower wafer, and fixing the die in the equipment, wherein the pressure of 0.15MPa is applied to the dome part of the wafer under the condition of room temperature and atmosphere, the wafer is kept for 10 minutes, the pressure is gradually reduced to 0, and the pre-bonding is completed;
5) And (5) bonding. After the pre-bonding is finished, vacuumizing the equipment to below 1X 10 -3 Pa, gradually applying pressure to the top wafer to reach 0.2MPa within 30 seconds, heating the upper wafer and the lower wafer at the same time, and keeping the temperature at 250 ℃ for 15 minutes under the conditions of the temperature and the pressure;
6) After bonding, heating is stopped, the pressure is gradually reduced, the sample is taken out after being cooled to 80 ℃ along with equipment, and the intermediate layer forms gradient transition.
The bonding strength of the obtained composite wafer is 5.2MPa, and the bonding rate is 97%.
Comparative example 1
The procedure is as in example 1, except that the deposition conditions are adjusted so that Ti/Ag (50 nm) is deposited and the other layers are unchanged, wherein the co-deposition conditions are such that the Ag target power is gradually increased from 10W to 100W, the Ti target power is gradually decreased from 100W to 0W, and the co-sputtering time is 540s.
The bonding strength of the obtained composite wafer is 4.7MPa, and the bonding rate is 93%.
Comparative example 2
The procedure of example 1 was followed, except that Ni was used as the initial layer and the thickness was 5nm, the transition layer was Ni/Ag (50 nm), and the other layers were unchanged, and the deposition conditions were the same as in comparative example 1.
The bonding strength of the obtained composite wafer is 2.8MPa, and the bonding rate is 88%.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (8)
1. The low-temperature bonding method of the diamond-based wafer with low interface thermal resistance is characterized by comprising the following steps of:
S1, performing surface activation on diamond and a semiconductor wafer through plasma etching treatment respectively;
The surface activation condition in the step S1 comprises that under the vacuum degree of 3X 10 -3 Pa or below, the RF power is 40-60W, the treatment atmosphere is a protective atmosphere without oxygen, and the treatment time is 40-80S;
s2, respectively depositing nano-sized gradient layers on the surfaces of the diamond activated in the step S1 and the semiconductor wafer;
the deposition process in step S2 includes:
Pre-sputtering under vacuum degree of 5×10 -4 Pa, sputtering power of 90-110W, ar gas flow of 40-60sccm, and pre-sputtering for 10-20min;
Then starting to deposit an initial layer, regulating the flow of argon to 20-30sccm, regulating the sputtering power to 90-110W, regulating the cavity pressure to 0.2-0.4Pa, and regulating the deposition time to 30-50s, thereby completing the initial layer plating process;
Then opening the Ag target to start co-sputtering, gradually increasing the power of the Ag target from 9-12W to 90-110W, gradually reducing the power of the initial layer target from 90-110W to 0W, and completing the deposition of the transition layer, wherein the co-sputtering time is 50-70 s;
After the co-sputtering is finished, depositing an ending layer Ag, keeping the cavity pressure and the argon flow unchanged, and continuing sputtering for 80-200s under 90-110W to finish the deposition of the ending layer;
s3, inverting one wafer obtained in the step S2 to enable the gradient layers on the two wafers to be in contact with each other;
s4, bonding is carried out under the bonding condition;
The gradient layer sequentially comprises an initial layer, a transition layer and an ending layer, wherein the initial layer is at least one selected from Ti, ta, cr, ni, W, mo, the ending layer is Ag, the thickness of the initial layer is not more than 5nm, the thickness of the transition layer is not more than 10nm, and the thickness of the ending layer is not more than 15nm;
The bonding condition in the step S4 comprises the steps of gradually applying pressure to a wafer at the top under the condition that the ambient vacuum degree is less than 1X 10 -3 Pa so as to reach 0.1-0.3MPa within 30S, and then simultaneously heating the upper wafer and the lower wafer at the temperature of 200-250 ℃ for 10-20min.
2. The method of claim 1, wherein the diamond and the semiconductor wafer in step S1 each have a surface flatness of <3 μm and a roughness Rq.ltoreq.2 nm.
3. The method of low temperature bonding according to claim 1, wherein,
The plasma etching process in step S1 is specifically performed by bombarding the surface of the bonded wafer with ICPAr plasma.
4. The low temperature bonding method according to claim 1, further comprising a wafer surface cleaning step before performing step S1:
Firstly, using acetone or isopropanol to carry out ultrasonic cleaning for 10-30min, then using absolute ethyl alcohol to carry out ultrasonic cleaning for 10-20min, finally using deionized water to carry out ultrasonic cleaning for 10-20min, taking out after the cleaning is finished, and drying by using protective gas.
5. The low temperature bonding method of claim 1, wherein the semiconductor wafer is selected from one or more semiconductor materials in GaN, si, ge, gaAs, inP, gaO, siC, alN.
6. The low temperature bonding method according to claim 1, further comprising, prior to the bonding in step S4, further performing pre-bonding:
And under the condition of room temperature and atmosphere, applying 0.1-0.2MPa pressure to a wafer at the top, keeping for 8-12min, gradually reducing the pressure to 0, and completing pre-bonding.
7. A low interfacial thermal resistance diamond-based wafer made by the low temperature bonding method of any one of claims 1-6.
8. The diamond based wafer of claim 7, wherein the diamond based wafer has a bond strength of 5MPa or greater and an interfacial bonding rate of greater than 95%.
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