CN115017852B - A layout method for heterogeneous FPGA - Google Patents
A layout method for heterogeneous FPGA Download PDFInfo
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Abstract
本申请公开了一种异构型FPGA的布局方法，涉及FPGA技术领域，该方法将用户输入网表转换为等效网表，等效网表中任意两个作用有牵引关系的功能模块的模块尺寸差异均不超过差异阈值，然后在等效网表的等效模块的位置约束信息的约束下，按照等效网表利用模块尺寸相近的功能模块进行求解布局，并还原得到原始可布模块的合法布局位置从而完成布局。本申请将异构型FPGA的不同模块尺寸的功能模块混合布局的问题转换为同等规格模块尺寸的功能模块的布局问题，从而提高功能模块之间牵引加力的准确性，继而提高布局质量。
The present application discloses a layout method for heterogeneous FPGAs, and relates to the field of FPGA technology. The method converts a user input netlist into an equivalent netlist, and the module size difference between any two functional modules with a traction relationship in the equivalent netlist does not exceed the difference threshold. Then, under the constraints of the position constraint information of the equivalent modules in the equivalent netlist, the layout is solved using functional modules with similar module sizes according to the equivalent netlist, and the legal layout position of the original routable module is restored to complete the layout. The present application converts the problem of mixed layout of functional modules of different module sizes in heterogeneous FPGAs into the layout problem of functional modules of the same specification module size, thereby improving the accuracy of traction and force addition between functional modules, and then improving the layout quality.
Description
Technical Field
The invention relates to the technical field of FPGA, in particular to a layout method of heterogeneous FPGA.
Background
A Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) is a chip that is widely used in household appliances, large machines, and even aerospace. The use of FPGA chips is not separated from electronic design automation (Electronic Design Automation, EDA) tools. The layout is an important ring in the EDA tool, which has a great influence on the operation speed of the EDA tool itself and the final quality of the processed circuit. In recent years, the circuit scale of FPGA chips has been rapidly increased to make them more powerful, but at the same time, it has also presented challenges to the corresponding EDA tools.
The main function of the layout is to map the examples in the user netlist to the layout positions of the FPGA chip with actual physical coordinates one by one under the optimization target, and the characteristic that the analytic layout algorithm can rapidly obtain the global optimal solution by using a mathematical method becomes one of the main flow directions of the present layout algorithm.
However, in the layout process, the analytic layout algorithm establishes the movable modules to be laid out as nodes and establishes the signal connection relationship between the nodes as a point-to-point edge relationship, so that a force-oriented layout algorithm model is established to carry out iterative solution to complete the layout. However, in reality, each module has a certain size, and in heterogeneous FPGAs, the sizes of different modules are different, so that the fact that the modules are abstracted into one node to be represented is actually inaccurate, and in particular, the stress application of the signal connection relation in the force-guiding layout algorithm model is inaccurate, so that the layout quality is poor.
Disclosure of Invention
Aiming at the problem that the layout quality is affected by inaccuracy of stress application caused by directly abstracting each functional module into one node by a conventional force-oriented layout algorithm model, the application provides a layout method of a heterogeneous FPGA, and the technical scheme of the application is as follows:
A layout method of an heterogeneous FPGA, the method comprising:
Obtaining a user input netlist corresponding to an FPGA chip, wherein the user input netlist comprises a plurality of original distributable modules which do not have legal layout positions yet, and the difference of the module sizes of at least two original distributable modules exceeds a difference threshold;
Converting the user input netlist into an equivalent netlist, wherein the module size difference of any two functional modules with traction relation in the equivalent netlist does not exceed the difference threshold, and the equivalent netlist only comprises equivalent modules or comprises equivalent modules and original spreadable modules; each equivalent module is obtained by equivalent of one or more original routable modules in the user input netlist, and the traction relation between the functional modules in the equivalent netlist is consistent with the traction relation between the original routable modules in the user input netlist;
determining position constraint information of each equivalent module in the equivalent netlist;
Under the constraint of the position constraint information of the equivalent module, solving and laying out the FPGA chip by utilizing a force-directed layout algorithm model based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout position of each functional module in the equivalent netlist;
and obtaining legal layout positions of the corresponding original routable modules according to the legal layout positions of the equivalent modules, obtaining the legal layout positions of all the original routable modules in the user input netlist, and completing the layout of the FPGA chip.
The method comprises the further technical scheme that the equivalent netlist comprises a plurality of virtual small modules which are obtained by equivalent splitting of a large-size distributable module and are not overlapped and are used for traction relation with other functional modules, each virtual small module is formed into an equivalent module, the position constraint information of each virtual small module is the legal layout position of the virtual small module on an FPGA chip, and the large-size distributable module is an original distributable module of which the module size exceeds a first preset size threshold value in the user input netlist.
The further technical scheme is that the method for determining the virtual small modules and the position constraint information thereof in the equivalent netlist comprises the following steps:
Based on traction action among the original spreadable modules, a force-directed layout algorithm model is utilized, an initial layout result is obtained by solving and laying out the FPGA chip according to a user input netlist, legal processing is carried out on the large-size spreadable modules to be equivalently split based on the initial layout result, and legal layout positions of the large-size spreadable modules on the FPGA chip are determined;
And equivalently splitting each large-size distributable module into a plurality of misaligned virtual small modules according to a preset splitting rule, and obtaining the legal layout positions of each virtual small module on the FPGA chip according to the legal layout positions of the large-size distributable modules and the relative relation between each virtual small module and the large-size distributable module.
The further technical scheme is that for a group of traction relations between each large-size distributable module and one other functional module, the traction relations act on virtual small modules which are obtained by equivalently splitting the large-size distributable modules and are positioned at stress application points of the traction relations on the large-size distributable modules;
On the basis that each virtual small module is fixed at the legal layout position, solving and layout are carried out on the FPGA chip according to the equivalent netlist by utilizing the force-directed layout algorithm model based on the traction action of each virtual small module.
The method comprises the further technical scheme that the equivalent netlist comprises a virtual large module obtained by equivalent combination of a plurality of small-size distributable modules, the virtual large module covers all small-size distributable modules, the virtual large module is formed into an equivalent module, the position constraint information of each virtual large module is the relative layout position relation of a plurality of original distributable modules contained in the virtual large module, and the small-size distributable modules are original distributable modules of which the module sizes in the user-input netlist do not exceed a second preset size threshold.
The method comprises the further technical scheme that for a group of traction relations between each small-size distributable module and one other functional module, the traction relations act on a virtual large module obtained by combining the small-size distributable modules, and stress application points of the traction relations on the virtual large module are positioned at physical positions of the small-size distributable modules in the virtual large module;
on the basis of unchanged relative layout position relation of each small-size distributable module in the virtual large module, solving and laying out the FPGA chip according to the equivalent netlist by utilizing a force-guiding layout algorithm model based on the traction action of each functional module.
The method comprises the further technical scheme that the module sizes of all virtual small modules in an equivalent netlist are equal, or the module sizes of at least two virtual small modules are unequal, and the two virtual small modules with unequal module sizes are obtained by equally splitting the same large-size distributable module, or are obtained by equally splitting different two large-size distributable modules.
The further technical scheme is that the sum of the module areas of all equivalent modules obtained by splitting each large-size distributable module is equal to or smaller than the module area of the large-size distributable module.
The further technical scheme is that a large-size distributable module is equivalently split to obtain at least one empty small module without any traction relation, and each empty small module is formed into an equivalent module.
The method comprises the further technical scheme that the module size difference between each empty small module and any other functional module in the equivalent netlist does not exceed a difference threshold, or the module size difference between each empty small module and at least one other functional module in the equivalent netlist exceeds a difference threshold.
The further technical scheme is that each small-size distributable module combined to obtain one virtual large module is respectively acted on at least one group of traction relations with other functional modules, or at least one small-size distributable module is not acted on any traction relation.
The method further comprises the steps of designating a plurality of preset function modules in the user input netlist to be placed at respective legal layout positions, wherein all the function modules except the preset function modules in the user input netlist are original distributable modules;
under the constraint that the preset functional modules are fixed at the legal layout positions of the functional modules and the position constraint information of the equivalent modules, solving and laying out the FPGA chip by utilizing a force-guided layout algorithm model based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout positions of each functional module in the equivalent netlist.
The further technical scheme is that the module size difference between any one preset functional module and any one functional module in the equivalent netlist does not exceed a difference threshold.
The beneficial effects of the application are as follows:
The application provides a layout method of heterogeneous FPGA, which aims at the problem caused by the mixed layout of functional modules with different module sizes in heterogeneous FPGA, the original spreadable modules are equivalently processed into equivalent modules to obtain an equivalent netlist, the equivalent netlist is used for solving and layout by utilizing the functional modules with similar module sizes, and then the legal layout positions of the original spreadable modules are reduced to obtain the legal layout positions of the original spreadable modules to finish the layout, so that the problem of the mixed layout of the functional modules with different module sizes is converted into the layout problem of the functional modules with the same specification of module sizes, thereby improving the accuracy of traction and stress among the functional modules and further improving the layout quality.
When the original distributable module is subjected to equivalent treatment, the large-size distributable module can be subjected to equivalent splitting and/or the small-size distributable module can be subjected to equivalent merging, and the equivalent modes are various, so that the layout requirements of different scenes and different functional modules can be met.
Drawings
FIG. 1 is a method flow diagram of a layout method of a heterogeneous FPGA of one embodiment.
Fig. 2 is a schematic diagram of the arrangement of functional modules with different module sizes inside a heterogeneous FPGA.
FIG. 3 is a method flow diagram of a layout method of a heterogeneous FPGA of another embodiment.
Fig. 4 is a flow chart of a method for equivalent splitting of large-size spreadable modules to obtain a plurality of equivalent modules.
Fig. 5 is an equivalent split schematic of a large-size spreadable module in one example.
Fig. 6 is an equivalent split schematic of a large-size spreadable module in another example.
Fig. 7 is an equivalent split schematic of a large-size spreadable module in another example.
Fig. 8 is an equivalent split schematic of a large-size spreadable module in another example.
FIG. 9 is a flow chart of a method for equivalent merging of multiple small-sized spreadable modules into one equivalent module.
Fig. 10 is an equivalent split schematic of a small-sized spreadable module in one example.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses a layout method of heterogeneous FPGA (field programmable gate array), referring to a flow chart shown in FIG. 1, the method comprises the following steps:
Step 100, obtaining a user input netlist corresponding to the FPGA chip.
The user input netlist comprises a plurality of original spreadable modules, wherein the original spreadable modules are functional modules to be laid out, which have no legal layout positions in the user input netlist. The module size difference of at least two original spreadable modules in the user input netlist exceeds a difference threshold, so that the heterogeneous FPGA can be obtained by completing design on an FPGA chip according to the user input netlist. The difference threshold can be set in a self-defined manner, and a module size difference exceeding the difference threshold indicates that the size difference between the two original spreadable modules is large, and if the two original spreadable modules are laid out according to the traditional method, the stress application between the two original spreadable modules is inaccurate due to the large size difference.
When comparing the module sizes of the two functional modules, the module size difference can be determined according to the module area difference and/or the size specification difference of the two functional modules, wherein the module area difference reflects the difference condition of the module areas of the two functional modules, and the absolute area difference and/or the relative area difference can be used as the module area difference according to the module areas. The size specification difference reflects the difference condition of the size specifications of the two functional modules, and the absolute side length difference and/or the relative side length difference can be obtained as the size difference by comparing the width and the height of the two functional modules.
Please refer to a schematic structure of an internal functional module of a common FPGA chip shown in fig. 2, wherein the FPGA chip includes several functional modules, and the sizes of the functional modules may be the same or different. Typically, the module size of the IOB module and/or CLB module is small, while the module size of the DSP module, BRAM module, CARRYCHAIN module, GTH module, etc. is large, e.g., the module size difference between the IOB module and the DSP module may exceed the difference threshold.
In one embodiment, where no legal layout positions are specified for any functional modules prior to performing step 200, then all of the functional modules in the user input netlist are originally routable modules. In another embodiment, a plurality of predetermined function modules in the user-input netlist are designated and placed at respective legal layout positions, that is, before step 200 is performed, legal layout positions are designated for some of the function modules first, and referring to fig. 3, all of the function modules in the user-input netlist are original routable modules except for the predetermined function modules.
And 200, converting the user input netlist into an equivalent netlist, wherein the module size difference of any two functional modules with traction relation in the equivalent netlist does not exceed a difference threshold. The equivalent netlist comprises at least one equivalent module with traction relation, each equivalent module is obtained by equivalent of one or more original spreadable modules in the user input netlist, the traction relation between the functional modules in the equivalent netlist is consistent with the traction relation between the original spreadable modules in the user input netlist, namely, when the original spreadable modules are equivalent to equivalent modules, the traction relation borne by the original spreadable modules is inherited to the equivalent modules.
When the original routable modules are equivalent to the corresponding equivalent modules, the original routable modules exist in the equivalent netlist in the form of the equivalent modules, and the original routable modules are not reserved in the equivalent netlist. In one embodiment, the equivalent netlist includes only the functional blocks belonging to the equivalent blocks, and does not include any functional blocks belonging to the original routable blocks, i.e., each original routable block in the user input netlist is treated as a corresponding equivalent block. In another embodiment, the equivalent netlist includes both equivalent modules and original routable modules, i.e., a portion of the original routable modules in the user input netlist are treated as corresponding equivalent modules and another portion of the original routable modules remain unchanged.
Step 300, determining position constraint information of each equivalent module in the equivalent netlist, wherein the position constraint information comprises constraint information of absolute positions of the functional modules on the FPGA chip and/or constraint information comprising relative positions among the functional modules.
And 400, solving and laying out the FPGA chip by utilizing a force-guided layout algorithm model based on the traction effect of each functional module in the equivalent netlist under the constraint of the position constraint information of the equivalent module to obtain the legal layout position of each functional module in the equivalent netlist.
Because the module size difference of each functional module with traction relation in the equivalent netlist does not exceed the difference threshold, namely the size difference between any two functional modules with traction relation is smaller, the stressing between the two functional modules can be ensured to be more accurate, and the layout result is more accurate.
In one embodiment, if the operation of placing the predetermined function modules in the legal layout positions is performed in advance, the module size difference between any predetermined function module and any function module in the equivalent netlist does not exceed the difference threshold, that is, because there is a traction relationship between the predetermined function module placed in advance and the original spreadable module, in order to ensure the stressing accuracy between the predetermined function module and the function module in the equivalent netlist, the size difference between the predetermined function module and the function module in the equivalent netlist must be ensured not to be too large. When the solving layout is performed in the step, the solving layout is performed on the FPGA chip by utilizing a force-guided layout algorithm model based on the traction action of each functional module in the equivalent netlist under the constraint that the preset functional modules are fixed at the legal layout positions of the corresponding functional modules and the position constraint information of the equivalent modules, so that the legal layout positions of the functional modules in the equivalent netlist are obtained.
And 500, obtaining the legal layout position of the corresponding original distributable module from the legal layout position of each equivalent module, namely restoring the equivalent module into the original distributable module according to the equivalent relation between the equivalent module and the original distributable module, and obtaining the legal layout position of the original distributable module before the equivalent. If the equivalent netlist only comprises equivalent modules, the legal layout positions of all original routable modules in the user input netlist can be obtained after the restoration. If the equivalent netlist includes original spreadable modules in addition to the equivalent modules, the original spreadable modules retained in the equivalent netlist can also obtain legal layout positions through step 400, and then the legal layout positions of the original spreadable modules obtained by the restoration of the equivalent modules are combined, so that the legal layout positions of all the original spreadable modules in the user input netlist can also be obtained.
If the function module is still preset, combining the legal layout positions of the preset function module to obtain the legal layout positions of all the function modules in the user input netlist, thereby completing the layout of the FPGA chip.
In the step 200, when the original spreadable module is equivalently processed into an equivalent module, there are mainly two cases (1) a large-size spreadable module is equivalently split into a plurality of small-size virtual small modules. Large-size routable modules are originally routable modules whose module size exceeds a first predetermined size threshold in the user input netlist, which module size can likewise be measured using module area and/or module size specifications. (2) And equivalently combining the plurality of small-size distributable modules to obtain a large-size virtual large module. The small-size routable module is an original routable module whose module size does not exceed a second predetermined size threshold in the user-input netlist.
When the original routable module in the user input netlist is subjected to equivalent processing, the first case can be only included, and the equivalent splitting operation is only performed on the original routable module. Or only the second case described above, and only the original routable module is subjected to an equivalent merge operation. Or the first condition and the second condition exist, namely, an equivalent splitting operation is performed on one part of original distributable modules, and an equivalent merging operation is performed on the other part of original distributable modules. The present application is described in terms of the following two embodiments, respectively, for the equivalent processing operations of the first case and the second case, and if the equivalent processing operations include both cases, the following two embodiments may be combined.
1. When converting a user input netlist into an equivalent netlist, the large-size distributable module is split into a plurality of small-size virtual small modules in an equivalent way, and the embodiment comprises the following steps, please refer to fig. 4:
step 410, obtaining a user input netlist corresponding to the FPGA chip.
And step 420, utilizing force to guide a layout algorithm model based on traction action among the original routable modules, and solving and laying out the FPGA chip according to the user input netlist to obtain an original layout result.
The step solves and lays out all the functional modules in the user input netlist, so that when the preset functional modules exist, the step solves and lays out the FPGA chip according to the user input netlist under the constraint that the preset functional modules are laid out at the corresponding legal layout positions to obtain an initial layout result. The guided layout algorithm model is a common layout algorithm, and the specific operation of the guided layout algorithm model is not repeated.
And 430, legally processing the large-size distributable modules to be equivalently split based on the initial layout result, and determining legal layout positions of the large-size distributable modules on the FPGA chip.
In the initial layout result, there is often a phenomenon that the layout positions of a part of functional modules overlap, and the layout positions of the functional modules in the initial layout result are illegal, and the conventional layout method needs to perform global legal processing on all original distributable modules in the initial layout result, and adjust the layout positions of all the functional modules so that all the functional modules have respective corresponding legal layout positions. And the application does not operate in this way, after the initial layout result is obtained, the application does not consider other original distributable modules temporarily, and legal treatment is carried out on all large-size distributable modules which need to be split equivalently later, so as to obtain legal layout positions of all large-size distributable modules, and all large-size distributable modules are fixed on corresponding legal layout positions. The specific legal treatment method can be realized by adopting a conventional method, and the application is not repeated.
And 440, equivalently splitting each large-size distributable module into a plurality of virtual small modules which are not overlapped and act on traction relation with other functional modules according to a preset splitting rule, wherein each virtual small module is formed into an equivalent module. And the module size difference between each virtual small module with traction relation and other functional modules in the equivalent netlist does not exceed a difference threshold.
The relative relation between each virtual small module and the large-size distributable module is known in the equivalent splitting process in the range defined by the legal layout position of the large-size distributable module, namely the relative position of the virtual small module in the large-size distributable module is known, and meanwhile the module size of each virtual small module can be determined. For example, in the splitting diagram shown in fig. 5, when the large-size distributable module M is equivalently split into 8 virtual small modules according to a predetermined splitting rule, the relative relationship between the 8 virtual small modules and the large-size distributable module M is known, and the module size of each virtual small module is also known.
There is at least one set of traction relationships between the large-size spreadable module and other functional modules, where the other functional modules include at least one of other original spreadable modules and predetermined functional modules. The large-size distributable module may have a traction relationship with one or more other functional modules, for example, please refer to fig. 5, and the large-size distributable module M has a traction relationship with 5 other functional modules A, B, C, D, E.
One or more sets of traction relationships may also exist between the large-size distributable module and each of the other functional modules. For example, in fig. 5, three sets of traction relationships LA1, LA2 and LA3 exist between the large-size distributable module M and the functional module a, two sets of traction relationships LB1 and LB2 exist between the large-size distributable module M and the functional module B, a set of traction relationships LC1 exists between the large-size distributable module M and the functional module C, and a set of traction relationships LD1 exists between the large-size distributable module M and the functional module D. A set of traction relationships LE1 exist between the large-size distributable module M and the functional module E.
For any one set of traction relation between each large-size distributable module and one other functional module, the traction relation acts on one stress application point on the large-size distributable module, and after the initial layout result is completed, each set of traction relation connected with the large-size distributable module and the stress application point of each set of traction relation on the large-size distributable module can be determined. For example, fig. 5 shows that the traction relationships of the various groups between the large-size module M and the other functional modules A, B, C, D, E are applied to the large-size module M at the points of application, i.e., the connection points with the large-size module M.
The traction relation between other functional modules and large-size distributable modules acts on the split virtual small modules. Specifically, for a set of traction relations between each large-size distributable module and one other functional module, the traction relations act on virtual small modules, which are obtained by equivalent splitting of the large-size distributable modules and are located at stress application points of the traction relations on the large-size distributable modules, at physical positions. For example, in the split schematic diagram shown in fig. 5, a set of traction relations LD1 exists between the large-size distributable module M and the functional module D to act on the virtual small module 5.
One virtual small module is acted with one set of traction relation or a plurality of sets of traction relations, and when one virtual small module is acted with a plurality of sets of traction relations, the plurality of sets of traction relations are used for connecting other identical or different functional modules. For example, in fig. 5, two sets of traction relationships LA2 and LB1 are applied to the split virtual small module 2, and the two sets of traction relationships are used to connect two different other functional modules a and B.
And step 450, obtaining legal layout positions of the virtual small modules on the FPGA chip according to the legal layout positions of the large-size distributable modules and the relative relation between the virtual small modules and the large-size distributable modules, and determining that the position constraint information of each virtual small module is the legal layout position of the virtual small module on the FPGA chip.
Based on the known legal layout position of the large-size distributable module on the FPGA chip, the legal layout position of each virtual small module can be determined by combining the relative relation between the virtual small module and the large-size distributable module, and in the embodiment, the legal layout position of each virtual small module on the FPGA chip is the position constraint information of the virtual small module and is the constraint information of the absolute position.
Step 460, on the basis that each virtual small module is fixed at each legal layout position, the force is utilized to guide the layout algorithm model based on the traction action of each virtual small module, and the FPGA chip is solved and laid out according to the equivalent netlist, so that the legal layout position of each functional module in the equivalent netlist is obtained.
The legal layout position of each virtual small module is fixed, each virtual small module is abstracted into a node, other functional modules are abstracted into a node respectively, and then the solution layout can be carried out by utilizing a force-oriented layout algorithm model according to the equivalent netlist, so that each other functional module can carry out the solution layout under the traction of the virtual small modules with the same module size, the stress application of the traction relation among the functional modules is more accurate, and the layout result is better.
When the preset functional module exists, solving and laying out the FPGA chip according to the equivalent netlist on the basis that the preset functional module and the virtual small module are respectively fixed at the legal layout positions of the preset functional module and the virtual small module, so that the legal layout positions of the functional modules in the equivalent netlist are obtained.
And 470, reducing each virtual small module into a large-size distributable module before equivalent splitting to obtain legal layout positions of all original distributable modules in the user input netlist, and completing the layout of the FPGA chip.
In step 440 of this embodiment, in one case, only one large-size distributable module is equivalently split to obtain virtual small modules with traction relations, for example, as shown in fig. 7, the large-size distributable module M is split to obtain equivalent modules 1, 2,3, 4, 5 and 6, and all the equivalent modules belong to at least one group of traction relations and are marked as virtual small modules. In another case, a large-size distributable module is not only split equivalently to obtain virtual small modules with traction relations, but also split to obtain at least one empty small module without any traction relations, and each empty small module is formed into an equivalent module. For example, in fig. 5 and 6, the large-size distributable module M is split to obtain equivalent modules 1 to 8, wherein the equivalent modules 1, 2,3, 4, 5 and 6 all act on at least one group of traction relations to belong to the virtual small modules, and the equivalent modules 7 and 8 all do not act on any traction relations to belong to the empty small modules.
Because the virtual small modules act in a traction relation, the stress application is accurate in order to ensure that the functional modules acting in the traction relation in the equivalent netlist are equivalent in size, and therefore, the module size difference of each virtual small module and the functional modules acting in the traction relation in the equivalent netlist does not exceed a difference threshold. The stress application accuracy of the traction relation between the functional modules in the layout re-solving process is hardly affected by the fact that the traction relation is not acted by the empty small modules, so that in an embodiment, the module size difference between each empty small module which does not act any traction relation and any other functional module in the equivalent netlist is not more than a difference threshold, or the module size difference between each empty small module and at least one other functional module in the equivalent netlist is more than a difference threshold. For example, as shown in fig. 5 or 6, the control modules 7 and 8 are similar to the module size of the virtual modules, or as shown in fig. 8, the module size of the empty module 7 is larger, i.e. the empty module has no strong constraint on the module size, and the module size hardly affects the subsequent layout quality.
In the embodiment shown in fig. 4, each equivalent module obtained by splitting a large-size distributable module has a certain module size and covers a certain layout area, and the relationship between a plurality of equivalent modules obtained by equivalent splitting and the module area of the original large-size distributable module is that (1) the sum of the module areas of all equivalent modules obtained by splitting each large-size distributable module is equal to the module area of the large-size distributable module, for example, as shown in fig. 5, the large-size distributable module M is split to obtain equivalent modules 1-8, the 8 virtual small modules respectively have a certain module size and are adjacently arranged mutually, and the sum of the module areas of the 8 equivalent modules is equal to the module area of the large-size distributable module M. (2) The sum of the module areas of all equivalent modules obtained by splitting each large-size distributable module is smaller than the module area of the large-size distributable module. For example, as shown in fig. 6, the large-size distributable module M is also split to obtain equivalent modules 1-8, and the 8 equivalent modules have certain module sizes, but compared with fig. 5, there is a predetermined distance between two equivalent modules, so that the sum of the module areas of the 8 equivalent modules is smaller than the module area of the large-size distributable module M. For example, as shown in fig. 7, the large-size distributable module M is split only at the stress application point to obtain virtual small modules 1-6, and the 6 virtual small modules are adjacent to each other, but do not cover the whole area of the large-size distributable module M, so that the sum of the module areas of the 6 virtual small modules is smaller than the module area of the large-size distributable module M.
As can be seen by comparing fig. 5 to 8, there are a plurality of predetermined splitting rules for a large-size distributable module, and the number, physical location and module size of the equivalent modules obtained by equivalent splitting can be determined according to practical situations, but a virtual small module needs to be ensured at each stress application point of each group of traction relations of the large-size distributable module. Thus, the module sizes of the virtual small modules obtained by splitting one large-size distributable module are equal, as shown in fig. 4. Or there are at least two virtual small modules of unequal module sizes, such as the virtual small module 2 and the virtual small module 8 of fig. 5, which are equal in module size and larger than the other virtual small modules.
The method for performing the equivalent split operation on one large-size distributable module is introduced above, and in practical application, the large-size distributable module for performing the equivalent split operation in the user input netlist comprises one or more large-size distributable modules. When a plurality of large-size distributable modules are included, the predetermined splitting rules adopted for performing the equivalent splitting operation on each large-size distributable module are the same, or the predetermined splitting rules adopted for performing the equivalent splitting operation on at least two large-size distributable modules are different. Finally, in the equivalent netlist, the module sizes of all the virtual small modules are equal, or the module sizes of at least two virtual small modules are unequal, and the two virtual small modules with unequal module sizes are obtained by equivalent splitting of the same large-size distributable module, or are obtained by equivalent splitting of two different large-size distributable modules. For example, one BRAM may be equivalently split according to the predetermined splitting rule shown in fig. 5, another BRAM may be equivalently split according to the predetermined splitting rule shown in fig. 6, and one DSP may be equivalently split according to the predetermined splitting rule shown in fig. 7.
2. In converting a user input netlist into an equivalent netlist, a plurality of small-size routable modules are equivalently combined into a virtual large module, which includes the following steps, please refer to fig. 9:
Step 910, obtaining a user input netlist corresponding to the FPGA chip.
In step 920, a plurality of small-size distributable modules in the user input netlist are equivalently combined to obtain a virtual large module, and the obtained virtual large module covers all small-size distributable modules, and one virtual large module is formed into an equivalent module. When the virtual big modules are obtained through combination, the relative relation between each small-size distributable module and the virtual big module is known, and the coverage area range of the virtual big module obtained through combination can be determined.
The case of equivalent merging can be regarded as the reverse of equivalent splitting, so similarly, when a virtual large module covers all small-sized routable modules, the module area is equal to or greater than the sum of the module areas of all small-sized routable modules. In one embodiment, each small-size distributable module combined to obtain one virtual large module is respectively used for acting the traction relation between at least one group and other functional modules, or at least one small-size distributable module is used for not acting any traction relation. As shown in fig. 10, the small-size distributable modules 1 to 8 are equivalently combined to obtain a virtual large module M, the small-size distributable modules 1 to 6 are acted on with traction relation, and the small-size distributable modules 7 and 8 are not acted on with any traction relation.
For a set of traction relationships between each small-size distributable module and one other functional module, the traction relationship acts on the virtual large module obtained by combining the small-size distributable modules. Specifically, the stress application point of the traction relation on the virtual large module is positioned at the physical position of the small-size distributable module in the virtual large module before equivalent combination.
In step 930, the relative layout positional relationship of the plurality of original routable modules included in each virtual big module is determined as the positional constraint information of the virtual big module. The small-size distributable modules which are equivalently combined into one virtual large module are generally function-related function modules, the relative layout position relationship among the small-size distributable modules needs to be kept unchanged during layout, and the relative layout position relationship among the small-size distributable modules is preset.
For example, a typical application is to combine multiple small-size distributable modules in Macro or Block or IP into one virtual large module, so as to realize layout of Macro or Block or IP and ensure that the relative layout position relationship and time sequence relationship between the small-size distributable modules in the constraint area are unchanged.
Step 940, on the basis that the relative layout position relationship of each small-size distributable module in the virtual large module is unchanged, solving and layout are carried out on the FPGA chip according to the equivalent netlist by utilizing a force-guiding layout algorithm model based on the traction action of each functional module. When the layout is solved, the equivalent large module is used as a whole for solving the layout, when the layout position of the equivalent large module is changed, the layout position of the corresponding small-size distributable module is correspondingly changed, and in the process of changing the layout position of the equivalent large module, the relative layout position of each corresponding small-size distributable module is kept unchanged.
And step 950, reducing each virtual large module into a small-size distributable module before equivalent splitting to obtain legal layout positions of all original distributable modules in the user input netlist, and completing the layout of the FPGA chip.
The legal layout position of the virtual large module can be obtained through step 940, and then the legal layout position of each small-size distributable module on the FPGA chip can be determined by combining the relative relation between each small-size distributable module and the virtual large module.
Claims (13)
1. A method for layout of a heterogeneous FPGA, the method comprising:
Obtaining a user input netlist corresponding to an FPGA chip, wherein the user input netlist comprises a plurality of original distributable modules which do not have legal layout positions yet, and the difference of the module sizes of at least two original distributable modules exceeds a difference threshold;
Converting the user input netlist into an equivalent netlist, wherein the module size difference of any two functional modules with traction relation in the equivalent netlist does not exceed the difference threshold, and the equivalent netlist only comprises equivalent modules or comprises equivalent modules and original spreadable modules; each equivalent module is obtained by equivalent of one or more original routable modules in the user input netlist, and the traction relation between the functional modules in the equivalent netlist is consistent with the traction relation between the original routable modules in the user input netlist;
determining position constraint information of each equivalent module in the equivalent netlist;
Under the constraint of the position constraint information of the equivalent module, solving and laying out the FPGA chip by utilizing a force-directed layout algorithm model based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout position of each functional module in the equivalent netlist;
And obtaining legal layout positions of the corresponding original routable modules from the legal layout positions of the equivalent modules, obtaining legal layout positions of all the original routable modules in the user input netlist, and completing the layout of the FPGA chip.
2. The method of claim 1, wherein the equivalent netlist includes a plurality of virtual small modules which are not coincident and act in traction relation with other functional modules and are obtained by equivalent splitting of one large-size distributable module, each virtual small module is formed into an equivalent module, position constraint information of each virtual small module is a legal layout position of the virtual small module on the FPGA chip, and the large-size distributable module is an original distributable module of which a module size in the user input netlist exceeds a first predetermined size threshold.
3. The method of claim 2, wherein the method of determining each virtual small module in the equivalent netlist and its position constraint information comprises:
Based on traction action among all original spreadable modules, utilizing a force-directed layout algorithm model, solving and laying out the FPGA chip according to the user input netlist to obtain an initial layout result, and legally processing large-size spreadable modules to be equivalently split based on the initial layout result to determine legal layout positions of all large-size spreadable modules on the FPGA chip;
And equivalently splitting each large-size distributable module into a plurality of misaligned virtual small modules according to a preset splitting rule, and obtaining the legal layout positions of each virtual small module on the FPGA chip according to the legal layout positions of the large-size distributable modules and the relative relation between each virtual small module and the large-size distributable modules.
4. The method according to claim 2, wherein for a set of traction relations between each large-size spreadable module and one other functional module, the traction relations act on virtual small modules of the large-size spreadable module, which are equally split, with physical positions at the stress points of the traction relations on the large-size spreadable module;
and on the basis that each virtual small module is fixed at the legal layout position, solving and layout are carried out on the FPGA chip according to the equivalent netlist by utilizing a force-guided layout algorithm model based on the traction action of each virtual small module.
5. The method of claim 1, wherein the equivalent netlist includes a virtual big module obtained by equivalent combination of a plurality of small-size distributable modules, the virtual big module covers all small-size distributable modules, the virtual big module is formed into an equivalent module, the position constraint information of each virtual big module is a relative layout position relationship of a plurality of original distributable modules contained in the virtual big module, and the small-size distributable modules are original distributable modules of which the module sizes in the user input netlist do not exceed a second predetermined size threshold.
6. The method of claim 5, wherein for a set of traction relationships between each small-size spreadable module and one other functional module, the traction relationships act on virtual large modules that are merged by the small-size spreadable modules, and force points of the traction relationships on the virtual large modules are located at physical locations of the small-size spreadable modules within the virtual large modules;
on the basis of unchanged relative layout position relation of each small-size distributable module in the virtual large module, solving and laying out the FPGA chip according to the equivalent netlist by utilizing a force-guiding layout algorithm model based on traction action of each functional module.
7. The method of claim 2, wherein the module sizes of all the virtual small modules in the equivalent netlist are equal, or the module sizes of at least two virtual small modules are unequal, and the two virtual small modules with unequal module sizes are obtained by equally splitting the same large-size distributable module, or by equally splitting different two large-size distributable modules.
8. The method of claim 2, wherein the sum of the module areas of all equivalent modules split for each large-size spreadable module is equal to or less than the module area of the large-size spreadable module.
9. The method of claim 2, wherein a large-size spreadable module is further equivalently split into at least one empty small module without any traction relationship, each empty small module being formed as an equivalent module.
10. The method of claim 9, wherein a module size difference between each empty small module and any other functional module in the equivalent netlist does not exceed the difference threshold, or wherein a module size difference between an empty small module and at least one other functional module in the equivalent netlist exceeds the difference threshold.
11. The method of claim 5, wherein each small-size distributable module combined to obtain a virtual large module is respectively acted on at least one group of traction relations with other functional modules, or is not acted on any traction relation on at least one small-size distributable module.
12. The method of claim 1, further comprising designating a number of predetermined functional modules in the user input netlist to be placed at respective legal placement locations, all but the predetermined functional modules of the user input netlist being original routable modules;
And under the constraint that the preset functional modules are fixed at the legal layout positions of the functional modules and the position constraint information of the equivalent modules, solving and laying out the FPGA chip by utilizing a force-guided layout algorithm model based on the traction action of the functional modules in the equivalent netlist to obtain the legal layout positions of the functional modules in the equivalent netlist.
13. The method of claim 12, wherein a module size difference between any one of the predetermined functional modules and any one of the functional modules in the equivalent netlist does not exceed a difference threshold.
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