CN115000133A

CN115000133A - Display substrate, preparation method and repair method thereof and display device

Info

Publication number: CN115000133A
Application number: CN202210225423.8A
Authority: CN
Inventors: 王海涛; 汪军; 王庆贺; 张扬; 刘军; 成军
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2022-03-09
Filing date: 2022-03-09
Publication date: 2022-09-02

Abstract

The embodiment of the disclosure provides a display substrate, a preparation method and a repair method thereof, and a display device. The display substrate comprises a plurality of pixel units arranged in an array, each pixel unit comprises a plurality of sub-pixels, at least one sub-pixel comprises a driving circuit layer arranged on a substrate, and the driving circuit layer comprises a standby signal line and a plurality of first signal lines which are in insulation intersection with the standby signal line; the first signal line includes reserve connection electrode, and there is first overlap area with reserve signal line orthographic projection on the basement in the orthographic projection of reserve connection electrode on the basement, and the technical scheme that this disclosed embodiment provided has overcome among the prior art and has shown that the base plate has the problem that the maintenance success rate is low.

Description

Display substrate, preparation method and repair method thereof and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display substrate, a preparation method, a repair method and a display device thereof.

Background

In the Display application field, electronic products such as Televisions (TVs) having displays are gradually developed toward large size and high PPI (also called pixel density unit), and Display devices such as Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) are generally used in the electronic products.

The research of the inventor of the application finds that the display substrate in the existing large-size display panel has the problem of low maintenance success rate.

Disclosure of Invention

The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, so as to overcome the problem that the display substrate in the prior art has a low maintenance success rate.

In order to solve the technical problem, the present disclosure provides a display substrate, including a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels, at least one sub-pixel including a driving circuit layer disposed on a base, the driving circuit layer including a spare signal line and a plurality of first signal lines intersecting the spare signal line in an insulated manner;

the first signal line comprises a spare connecting electrode, and a first overlapping area exists between the orthographic projection of the spare connecting electrode on the substrate and the orthographic projection of the spare signal line on the substrate.

In an exemplary embodiment, the driving circuit layer of at least one sub-pixel includes a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer sequentially disposed on the substrate, the spare signal line is located at the second conductive layer, and the plurality of first signal lines are located at the third conductive layer.

In an exemplary embodiment, the third insulating layer is provided with a spare half via filled with the spare connecting electrode, and an orthographic projection of the spare half via on the substrate is located within the range of the first overlapping area.

In an exemplary embodiment, in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel sequentially arranged along a first direction; the plurality of first signal lines include data signal lines, and the spare connection electrodes include first spare connection electrodes;

the data signal line is respectively arranged at each sub-pixel, the data signal line comprises a main body part and a first branch part, the first branch part comprises the first spare connection electrode, and the main body part of the data signal line extends along a second direction; the first spare connection electrodes in the first and third sub-pixels extend in a direction opposite to the first direction, and the first spare connection electrodes in the second and fourth sub-pixels extend in the first direction.

In an exemplary embodiment, in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along a first direction; the plurality of first signal lines include a first power line, and the spare connection electrode includes a second spare connection electrode;

the first power line includes a main portion and a branch portion, the branch portion of the first power line includes the second spare connection electrode, the main portion of the first power line is disposed between the second sub-pixel and the third sub-pixel, and the second spare connection electrode is located at the second sub-pixel and/or the third sub-pixel;

the main portion of the first power line extends in the second direction, the second alternate connection electrode in the second sub-pixel extends in the opposite direction of the first direction, and the second alternate connection electrode in the third sub-pixel extends in the first direction.

In an exemplary embodiment, in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along a first direction; the plurality of first signal lines include a compensation signal line, and the spare connection electrode includes a third spare connection electrode;

the compensation signal line is respectively arranged at the first sub-pixel and the fourth sub-pixel, the compensation signal line comprises a main body part and a branch part, the branch part of the compensation signal line comprises the third spare connection electrode, and the main body part of the compensation signal line extends along the second direction; in the first sub-pixel, the third spare connection electrode extends in the first direction; in the fourth sub-pixel, the third spare connection electrode extends in a direction opposite to the first direction.

In an exemplary embodiment, the spare signal lines are located in at least two pixel units.

In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a first transistor, a second transistor, and a third transistor; the active layers of the first transistor, the second transistor and the third transistor are located on the semiconductor layer, the gate electrodes of the first transistor, the second transistor and the third transistor are located on the second conductive layer, and the first poles and the second poles of the first transistor, the second transistor and the third transistor are located on the third conductive layer.

In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a shielding layer, the shielding layer is located on the first conductive layer, and an orthogonal projection of the active layer of the second transistor on the substrate is located within a range of an orthogonal projection of the shielding layer on the substrate.

In an exemplary embodiment, in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel sequentially arranged along a first direction; the shielding layer is reused as a first polar plate of the capacitor; the semiconductor layer includes a second plate formed at each sub-pixel;

the orthographic projection of the second polar plate on the substrate is positioned in the range of the orthographic projection of the first polar plate on the substrate; the area of the second plate in the first sub-pixel and the third sub-pixel is larger than the area of the second plate in the second sub-pixel and the fourth sub-pixel.

In an exemplary embodiment, the second conductive layer further includes a first scan signal line, a second scan signal line, and a second gate electrode; the first scanning signal line, the second scanning signal line and the standby signal line are arranged along a second direction;

the first scanning signal line comprises a main body part and a branch part, the main body part is a strip-shaped structure extending along a first direction and is positioned on one side of the second polar plate far away from the second scanning signal line in a second direction, the branch part extends along the second direction, the branch part comprises a first gate electrode corresponding to each sub-pixel, the first gate electrode is used as a gate electrode of a first transistor, and an overlapping region exists between the orthographic projection of the first gate electrode on the substrate and the orthographic projection of an active layer of the first transistor on the substrate;

the second scanning signal line is a strip-shaped structure extending along the first direction and is positioned on one side of the second polar plate far away from the first scanning signal line in the second direction, an overlapping region exists between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the active layer of the third transistor in each sub-pixel on the substrate, and the second scanning signal line in the overlapping region is used as a gate electrode of the third transistor;

the second gate electrode is used as a gate electrode of the second transistor, a second overlapping region exists between an orthographic projection of the second gate electrode on the substrate and an orthographic projection of an active layer of the second transistor on the substrate, and a third overlapping region exists between the orthographic projection of the second gate electrode, the second pole of the first transistor and the orthographic projection of the active layer of the first transistor on the substrate.

In an exemplary embodiment, the first signal line includes a data signal line disposed at each of the sub-pixels, respectively, the data signal line including a body portion and a second branch portion, the body portion of the data signal line extending along the second direction; the second branch portions in the first and third sub-pixels extend in a direction opposite to the first direction, and the second branch portions in the second and fourth sub-pixels extend in the first direction; the second branch portion is a first pole of the first transistor.

The embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the display substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, and at least one sub-pixel includes a driving circuit layer disposed on a substrate; the preparation method comprises the following steps:

forming a spare signal line in the driving circuit layer and a plurality of first signal lines which are insulated and crossed with the spare signal line; the first signal line comprises a spare connecting electrode, and a first overlapping area exists between the orthographic projection of the spare connecting electrode on the substrate and the orthographic projection of the spare signal line on the substrate.

The embodiment of the disclosure also provides a method for repairing a display substrate, where the display substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, at least one sub-pixel includes a driving circuit layer disposed on a substrate, and the driving circuit layer includes a spare signal line and a plurality of first signal lines crossing the spare signal line in an insulating manner; the first signal line comprises a spare connecting electrode, and a first overlapping area exists between the orthographic projection of the spare connecting electrode on the substrate and the orthographic projection of the spare signal line on the substrate; the repairing method comprises the following steps:

when any one first signal line is broken, the spare signal line is communicated with the spare connecting electrode on the first signal line with broken circuit, and the spare signal line is communicated with the spare connecting electrode on the first signal line without broken circuit, and the first signal line without broken circuit and the first signal line with broken circuit provide the same kind of signals.

The embodiment of the present disclosure further provides a display device, which includes the display substrate.

According to the display substrate and the preparation method, the repair method and the display device thereof, the standby signal line and the plurality of first signal lines which are in insulated intersection with the standby signal line are arranged on the driving circuit layer in the display substrate, each first signal line comprises the standby connection electrode, and a first overlapping area exists between the orthographic projection of the standby connection electrode on the substrate and the orthographic projection of the standby signal line on the substrate. When any one first signal line is broken, the standby signal line and the standby connection electrode on the first signal line with broken circuit are opened to realize electric connection, the standby signal line and the standby connection electrode on the first signal line without broken circuit are opened to realize electric connection, and the signal on the first signal line without broken circuit is provided to the first signal line with broken circuit, so that the problem that the existing display substrate is low in maintenance success rate is solved.

Of course, it is not necessary for any product or method of practicing the disclosure to achieve all of the advantages set forth above at the same time. Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. The objectives and other advantages of the disclosed embodiments may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

FIG. 1 is a schematic view of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 5a is a schematic diagram of a signal line with an open circuit;

FIG. 5b is a schematic cross-sectional view of the signal line of FIG. 5a at a repair open position;

FIG. 5c is a schematic cross-sectional view of another embodiment of the signal line open circuit repair shown in FIG. 5 a;

FIG. 6a is a schematic plane structure of a display substrate according to an embodiment of the disclosure;

FIG. 6b is a schematic cross-sectional view taken along line L-L of FIG. 6 a;

FIG. 7 is a schematic diagram showing an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in FIG. 6 a;

fig. 8 is a schematic view after a first conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

fig. 9a is a schematic view after a semiconductor layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 9b is a schematic plan view of the semiconductor layer of FIG. 9 a;

FIG. 9c is another schematic plan view of a semiconductor layer of an exemplary embodiment of the present disclosure;

fig. 10a is a schematic view after a second conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 10b is a schematic plan view of the second conductive layer in FIG. 10 a;

fig. 11a is a schematic view after a third insulation layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 11b is a schematic cross-sectional view taken at the position H-H in FIG. 11 a;

fig. 12a is a schematic view after a third conductive layer pattern is formed in an exemplary embodiment of the present disclosure;

FIG. 12b is a schematic plan view of the third conductive layer in FIG. 12 a;

fig. 12c is another schematic view after a third conductive layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 12d is a schematic plan view of the third conductive layer in FIG. 12 c;

fig. 13 is a schematic plan view illustrating a display substrate according to an exemplary embodiment of the disclosure;

FIG. 14a is a schematic cross-sectional view of FIGS. 12c and 13 at L-L;

FIG. 14b is a cross-sectional view of FIG. 12c at W-W;

FIGS. 15a to 15c are schematic diagrams illustrating repair of signal lines in a display substrate;

FIG. 15d is a schematic cross-sectional view of FIG. 15c at the U-U position.

Detailed Description

The embodiments in the present disclosure may be embodied in many different forms. Those skilled in the art can readily appreciate the fact that the present implementations and teachings can be modified into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of constituent elements, the thickness of layers, or regions may be exaggerated for clarity. Thus, any one implementation of the present disclosure is not necessarily limited to the dimensions shown in the figures, and the shapes and sizes of the components in the figures are not intended to reflect actual proportions. Further, the drawings schematically show ideal examples, and any one implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are provided to avoid confusion of the constituent elements, and are not limited in number.

In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of describing embodiments and simplifying description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components may be appropriately changed according to the direction of the described components. Therefore, the words described herein are not limited to the words described herein, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (or a drain electrode terminal, a drain connection region, or a drain electrode) and a source electrode (or a source electrode terminal, a source connection region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged in some cases. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.

In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. The "element having some kind of electric function" may be, for example, an electrode, a wiring, a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

In the present disclosure, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

In the present disclosure, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, etc. are not strictly defined, and may be an approximate triangle, a rectangle, a trapezoid, a pentagon, a hexagon, etc., and some small deformations caused by tolerances may exist, and a chamfer, an arc edge, and a deformation may exist.

"about" in this disclosure means that the limits are not strictly defined, and that values within the tolerances of the process and measurement are allowed.

Fig. 1 is a schematic structural diagram of a display device. As shown in fig. 1, the display device may include a timing controller connected to the data driver and the scan driver, respectively, the data driver connected to the plurality of data signal lines (D1 to D), respectively, the scan driver connected to the plurality of scan signal lines (S1 to Sm), respectively, and a pixel array. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver. The data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and D using the gray scale value and the control signal received from the timing controller. For example, the data driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to D in units of pixel rows, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, a third sub-pixel P3 emitting light of a third color, and a fourth sub-pixel P4 emitting light of a fourth color, and the four sub-pixels may each include a circuit unit and a light emitting device, the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, the pixel driving circuit is connected to the scan signal line and the data signal line, respectively, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light emitting device under the control of the scan signal line. The light emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a white subpixel (W) emitting white light, the third subpixel P3 may be a blue subpixel (B) emitting blue light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light.

In an exemplary embodiment, the shape of the sub-pixel may be a rectangular shape, a diamond shape, a pentagon shape, or a hexagon shape. In an exemplary embodiment, four sub-pixels may be arranged in a horizontal parallel manner to form an RWBG pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a Square (Square), Diamond (Diamond), or vertical parallel manner, and the disclosure is not limited thereto.

In an exemplary embodiment, a plurality of sub-pixels sequentially arranged in a horizontal direction are referred to as pixel rows, a plurality of sub-pixels sequentially arranged in a vertical direction are referred to as pixel columns, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array.

Fig. 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels of the display substrate. As shown in fig. 3, each sub-pixel in the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate, in a plane perpendicular to the display substrate.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light emitting structure layer 103 of each sub-pixel may include a light emitting device composed of a plurality of film layers, the plurality of film layers may include an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, the anode 301 is connected to the pixel driving circuit, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, the first encapsulation layer 401 and the third encapsulation layer 403 may use an inorganic material, the second encapsulation layer 402 may use an organic material, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, so as to ensure that external moisture cannot enter the light emitting structure layer 103.

In example embodiments, the organic light emitting layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), an light emitting layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an exemplary embodiment, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all the sub-pixels may be a common layer connected together, the light emitting layers of all the sub-pixels may be a common layer connected together, or may be isolated from each other, and the light emitting layers of adjacent sub-pixels may overlap by a small amount. In some possible implementations, the display substrate may include other film layers, and the disclosure is not limited thereto.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Fig. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in fig. 4, the pixel driving circuit has a 3T1C structure, and may include 3 transistors (a first transistor T1, a second transistor T2, and a third transistor T3), 1 storage capacitor C, and 6 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a compensation signal line S, a first power supply line VDD, and a second power supply line VSS).

In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensating transistor. A first pole of the storage capacitor C is coupled to the control pole of the second transistor T2, a second pole of the storage capacitor C is coupled to the second pole of the second transistor T2, and the storage capacitor C is used for storing the potential of the control pole of the second transistor T2. The control electrode of the first transistor T1 is coupled to the first scan signal line S1, the first electrode of the first transistor T1 is coupled to the data signal line D, the second electrode of the first transistor T1 is coupled to the control electrode of the second transistor T2, and the first transistor T1 is configured to receive the data signal transmitted by the data signal line D under the control of the first scan signal line S1, so that the control electrode of the second transistor T2 receives the data signal. The control electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, the second electrode of the second transistor T2 is coupled to the first electrode of the light emitting device, and the second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by the control electrode. A control electrode of the third transistor T3 is coupled to the second scan signal line S2, a first electrode of the third transistor T3 is coupled to the compensation signal line S, a second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2, and the third transistor T3 is used for extracting the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate the threshold voltage Vth.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked, the first electrode of the OLED being coupled to the second electrode of the second transistor T2, the second electrode of the OLED being coupled to the second power line VSS, the OLED for emitting light of a corresponding brightness in response to a current of the second electrode of the second transistor T2.

In an exemplary embodiment, the signal of the first power line VDD is a signal continuously supplying a high level, and the signal of the second power line VSS is a signal of a low level. The first through third transistors T1 through T3 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved.

In an exemplary embodiment, the first to third transistors T1 to T3 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, a Low Temperature polysilicon thin film transistor and an Oxide thin film transistor may be integrated on a display substrate to form a Low Temperature Polysilicon Oxide (LTPO) display substrate, and may use advantages of the two, may implement high resolution (Pixel Per inc, PPI for short), may perform Low frequency driving, may reduce power consumption, and may improve display quality. In an exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, taking 3 transistors as N-type transistors as an example, the operation process of the pixel driving circuit illustrated in fig. 4 may include:

in the first stage a1, the signals of the first scanning signal line S1 and the second scanning signal line S2 are high level signals, the data signal line D outputs a data voltage, the compensation signal line S outputs a compensation voltage, the signal of the first power line VDD is high level, and the signal of the second power line VSS is low level. The signal of the first scan signal line S1 is a high level signal, turning on the first transistor T1, writing the data voltage outputted from the data signal line D into the first node N1, pulling the potential of the first node N1 high, charging the storage capacitor C, and the potential of the first node N1 is V ₁ ＝V _data . The signal of the second scanning signal line S2 is a high level signal, the third transistor T3 is turned on, the compensation voltage outputted from the compensation signal line S is written into the second node N2, and the potential V of the second node N2 is at this time ₂ ＝V _s . Since the difference between the potentials of the first node N1 and the second node N2 is greater than the threshold voltage V of the second transistor T2 _th The second transistor T2 is turned on, and the power voltage output from the first power line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on second transistor T2, thereby driving the OLED to emit light.

In the second stage a2, the signals of the first scan signal line S1 and the second scan signal line S2 are low level signals, so that the first transistor T1 and the third transistor T3 are turned off, the voltage in the storage capacitor C still makes the second transistor T2 in an on state, the power voltage output by the first power line VDD keeps pulling up the potential of the second node N2, and the OLED keeps emitting light. When the potential of the second node N2 is equal to V _data -V _th At this time, the second transistor T2 is turned off and the OLED no longer emits light.

In an exemplary embodiment, in order to drive the OLED to normally emit light, both the OLED and the second transistor T2 are forward biased, and in the first stage, the first power line VDD outputs a power voltage greater than the data signal line D outputting a data voltage greater than the compensation voltage output by the compensation signal line S which outputs a compensation voltage greater than the power voltage output by the second power line VSS.

With the increase of the size of the display device and the improvement of PPI, signal lines in the display device (such as the display panel) are also more and more dense, because the size of the display panel is larger, the voltage at a position far away from the power supply device in the display panel is lower than that at a position near to the power supply device, which is called as resistance Drop (IR Drop), in order to reduce the resistance Drop of the large-size display panel, the film layer for manufacturing the signal lines is usually thickened, when the defect of the signal line disconnection type occurs in the process for manufacturing the display panel (for example, the signal line SD is disconnected at the position 01 in fig. 5 a), the metal powder is usually deposited at the disconnection position for maintenance, because the thicker film layer of the signal lines, the phenomenon of non-lap joint often occurs after the metal powder (such as tungsten powder) is deposited at the disconnection position of the signal line, thereby resulting in low maintenance success rate. There are two situations in the overlap joint of the deposited metal powder at the signal wire fracture position: in one case, as shown in fig. 5b, in order to repair the broken line at the position 01 in fig. 5a in a cross-sectional structure at the position N-N, when the signal line SD is connected at the broken position 01 of the signal line SD by depositing the tungsten powder layer 02, the side wall of the tungsten powder layer 02 at the broken position 01 is prone to creep rupture (in the figure, c1 is a creep rupture position), and thus the repair fails, because the thickness of the signal line SD is thick (the dimension in the third direction Z is large) and the thickness of the tungsten powder layer 02 is thin; another situation is shown in fig. 5c, which is another schematic cross-sectional view of repairing a broken line at a position N-N at a position 01 in fig. 5a, after the tungsten powder layer 02 is deposited, because the thickness of the tungsten powder layer 02 is too thin, the resistance is large, and a situation that the tungsten powder layer 02 is blown due to an excessively large resistance often occurs, and c2 is a position where the tungsten powder layer 02 is blown due to a large resistance.

In order to solve the problem that the existing display substrate is low in maintenance success rate, the embodiment of the disclosure provides a display substrate. The display substrate may include a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels, at least one of the sub-pixels including a driving circuit layer disposed on a base, the driving circuit layer including a spare signal line and a plurality of first signal lines crossing the spare signal line in an insulated manner;

In the display substrate provided by the embodiment of the disclosure, the driving circuit layer is provided with a spare signal line and a plurality of first signal lines which are in insulated intersection with the spare signal line, each first signal line comprises a spare connection electrode, and a first overlapping area exists between an orthographic projection of the spare connection electrode on the substrate and an orthographic projection of the spare signal line on the substrate. When any one first signal line is broken, the standby signal line and the standby connection electrode on the first signal line with broken circuit are opened to realize electric connection, the standby signal line and the standby connection electrode on the first signal line without broken circuit are opened to realize electric connection, and the signal on the first signal line without broken circuit is provided to the first signal line with broken circuit, so that the problem that the existing display substrate is low in maintenance success rate is solved.

Fig. 6a is a schematic plan view illustrating a display substrate according to an exemplary embodiment of the disclosure, and fig. 6b is a schematic cross-sectional view illustrating a position L-L in fig. 6 a. As shown in fig. 6a and 6b, fig. 6a is a schematic plane structure of a display substrate, fig. 6b is a schematic cross-sectional structure at a position L-L in fig. 6a, the display substrate may include a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, at least one sub-pixel includes a driving circuit layer disposed on a substrate, the driving circuit layer includes a spare signal line 53 and a plurality of first signal lines (61, 62, 63) intersecting with the spare signal line 53 in an insulated manner;

the first signal line comprises spare connecting electrodes (61-3, 62-2 and 63-1), and the orthographic projection of the spare connecting electrodes (61-3, 62-2 and 63-1) on the substrate 101 and the orthographic projection of the spare signal line 53 on the substrate 101 have a first overlapping area.

In the embodiment of the present disclosure, when the first signal line is disconnected, the spare connection electrode and the spare signal line may be connected in the first overlap region by laser melting.

Fig. 7 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the disclosure, illustrating a structure of a driving circuit layer in four sub-pixels (one pixel unit) of a bottom emission display substrate,

fig. 7 is a schematic diagram of an equivalent circuit of the pixel driving circuit in the four sub-pixels shown in fig. 6 a. As shown in fig. 7 and 7, at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4, each including a pixel driving circuit and a storage capacitor, sequentially arranged along a first direction X in a direction parallel to a display substrate. In the following description, the sub-pixels each refer to a region where a pixel driving circuit is disposed. In an exemplary embodiment, the at least one pixel unit may further include one first scan signal line 51, one second scan signal line 52, two compensation signal source lines 63, four data signal lines 62, one first power line 61, and four pixel driving circuits.

In an exemplary embodiment, the driving circuit layer of at least one sub-pixel includes a first conductive layer, a first insulating layer 20, a semiconductor layer, a second insulating layer 40, a second conductive layer, a third insulating layer 60, and a third conductive layer sequentially disposed on the substrate 101, the spare signal line 53 is located at the second conductive layer, and the plurality of first signal lines are located at the third conductive layer.

In an exemplary embodiment, the third insulating layer 60 is provided with a spare half via Vm filled with spare connection electrodes (62-2, 63-1, 61-3), an orthographic projection of the spare half via Vm on the substrate 101 being located within the range of the first overlapping region.

In the embodiment of the present disclosure, a spare half via hole Vm is formed in a third insulating layer between the spare connecting electrode and the spare signal line, so that more spare connecting electrodes can be contained in the spare half via hole Vm, and when the broken first signal line is repaired in a laser melting mode, the spare connecting electrode can be electrically connected with the spare signal line well in the laser melting state.

In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 sequentially arranged in a first direction in a plane of the display substrate; the plurality of first signal lines include a data signal line 62, and the spare connection electrode includes a first spare connection electrode 62-2;

the data signal line 62 is provided at each sub-pixel, respectively, the data signal line 62 including a main portion and a first branch portion, the first branch portion including a first spare connection electrode 62-2, the main portion of the data signal line 62 extending in the second direction Y; the first spare connection electrode 62-2 in the first and third sub-pixels P1 and P3 extends in the opposite direction of the first direction X, and the first spare connection electrode 62-2 in the second and fourth sub-pixels P2 and P4 extends in the first direction X.

In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 sequentially arranged in the first direction X in a plane of the display substrate; the plurality of first signal lines include a first power line 61, and the spare connection electrode includes a second spare connection electrode 61-3;

the first power line 61 includes a body portion and a branch portion, the branch portion of the first power line 61 includes a second spare connection electrode 61-3, the body portion of the first power line 61 is disposed between the second sub-pixel P2 and the third sub-pixel P3, and the second spare connection electrode 61-3 is located at the second sub-pixel P2 and/or the third sub-pixel P3;

the main portion of the first power line 61 extends in the second direction Y, the second spare connection electrode 61-3 in the second sub-pixel P2 extends in the opposite direction of the first direction X, and the second spare connection electrode 61-3 in the third sub-pixel P3 extends in the first direction X.

In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 sequentially arranged in the first direction X in a plane of the display substrate; the plurality of first signal lines include a compensation signal line 63, and the spare connection electrode includes a third spare connection electrode 63-1;

the compensation signal line 63 is disposed at the first subpixel P1 and the fourth subpixel P4, respectively, the compensation signal line 63 including a main portion and a branch portion, the branch portion of the compensation signal line 63 including the third spare connection electrode 63-1, the main portion of the compensation signal line 63 extending in the second direction Y; in the first subpixel P1, the third spare connection electrode 63-1 extends in the first direction X; in the fourth sub-pixel P4, the third spare connection electrode 63-1 extends in the opposite direction of the first direction X.

In an exemplary embodiment, the spare signal lines 53 are located in at least two pixel units.

In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a first transistor T1, a second transistor T2, and a third transistor T3; the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 are located at a semiconductor layer, the gate electrodes of the first transistor T1, the second transistor T2, and the third transistor T3 are located at a second conductive layer, and the first and second poles of the first transistor T1, the second transistor T2, and the third transistor T3 are located at a third conductive layer.

In an exemplary embodiment, in at least one sub-pixel, the driving circuit further includes a shielding layer on the first conductive layer, and an orthogonal projection of the active layer of the second transistor T2 on the substrate 101 is within a range of an orthogonal projection of the shielding layer on the substrate.

In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 sequentially arranged in the first direction X in a plane of the display substrate; the shielding layer can be multiplexed into a first plate of the capacitor; the semiconductor layer may include a second plate formed at each sub-pixel;

the orthographic projection of the second polar plate on the substrate is positioned in the range of the orthographic projection of the first polar plate on the substrate; the areas of the second plates in the first and third sub-pixels P1 and P3 are greater than the areas of the second plates in the second and fourth sub-pixels P2 and P4.

In an exemplary embodiment, the second conductive layer may further include a first scan signal line 51, a second scan signal line 52, and a second gate electrode 54; the first scanning signal line 51, the second scanning signal line 52, and the spare signal line 53 may be arranged in the second direction Y;

the first scan signal line 51 may include a main portion and a branch portion, the main portion of the first scan signal line 51 may be a stripe structure extending along the first direction X, located on a side of the second diode away from the second scan signal line 52 in the second direction Y, the branch portion of the first scan signal line 51 extending along the second direction Y, the branch portion of the first scan signal line 51 may include a first gate electrode 51-1 corresponding to each sub-pixel, the first gate electrode 51-1 may serve as a gate electrode of the first transistor T1, and an overlapping region exists between an orthographic projection of the first gate electrode 51-1 on the substrate 101 and an orthographic projection of an active layer of the first transistor T1 on the substrate 101;

the second scan signal line 52 is a stripe structure extending along the first direction X and located on a side of the second plate 34 away from the first scan signal line 51 in the second direction Y, an overlapping region exists between an orthogonal projection of the second scan signal line 52 on the substrate 101 and an orthogonal projection of the active layer of the third transistor T3 in each sub-pixel on the substrate 101, and the second scan signal line 52 in the overlapping region serves as a gate electrode of the third transistor T3;

the second gate electrode 54 serves as a gate electrode of the second transistor T2, a second overlapping region exists between an orthographic projection of the second gate electrode 54 on the substrate 101 and an orthographic projection of the active layer of the second transistor T2 on the substrate 101, and a third overlapping region exists between the second gate electrode 54, the second pole of the first transistor T1 and the orthographic projection of the active layer of the first transistor T1 on the substrate 101. Wherein the second overlapping area and the third overlapping area do not overlap.

In an exemplary embodiment, the first signal line may include a data signal line 62, the data signal line 62 being disposed at each of the sub-pixels, respectively, the data signal line 62 may include a main portion and a second branch portion, the main portion of the data signal line 62 extending along the second direction Y; the second branch portions of the data signal lines 62 in the first and third sub-pixels P1 and P3 extend in the opposite direction of the first direction Y, and the second branch portions of the data signal lines 62 in the second and fourth sub-pixels P2 and P4 extend in the first direction; the second branch portion of the data signal line 62 may serve as a first pole of the first transistor T1.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, the "thin film" is referred to as the "thin film" before the patterning process, and the "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of B is located within the range of the forward projection of a" or "the forward projection of a includes the forward projection of B" means that the boundary of the forward projection of B falls within the boundary range of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

In an exemplary embodiment, taking four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4) as an example, the fabrication process of the driving circuit layer may include the following operations.

(1) A first conductive layer pattern is formed.

In an exemplary embodiment, the forming of the first conductive layer pattern may include: a first conductive layer film is deposited on the substrate 101, and the first conductive film is patterned through a patterning process to form a pattern of a first conductive layer 11 disposed on the substrate 101, as shown in fig. 8, which is a schematic plan view of the first conductive layer.

In an exemplary embodiment, the patterning of the first conductive thin film through the patterning process may include: coating a layer of photoresist on the first conductive film, forming a photoresist pattern through masking, exposing and developing, forming an unexposed area in the first conductive layer pattern area, reserving the photoresist, forming an exposed area in the area except the first conductive layer pattern, having no photoresist, etching the first conductive layer film in the exposed area by using an etching process, and finally stripping off the residual photoresist to form a first conductive layer pattern.

In an exemplary embodiment, the first conductive layer pattern includes at least two power supply connection lines 11, two compensation connection lines 12, and a first plate 13 and an interlayer connection electrode 14 formed at a capacitance of each sub-pixel. In an exemplary embodiment, the first conductive layer may be referred to as a shield metal (SHL) layer.

In an exemplary embodiment, the two power connection lines 11 may be bar-shaped junctions extending in the first direction X and sequentially arranged in the second direction Y.

In an exemplary embodiment, two power connection lines 11 are respectively located at both sides of the first plate 13 along the second direction Y, and the two power connection lines 11 may be multiplexed by pixel cells adjacent along the second direction Y, for example, the power connection line 11 located at one side of the first plate 13 along the second direction Y may be multiplexed as a power connection line by the pixel cell located at one side of the first plate 13 along the second direction Y; the power connection line 11 on the side of the first plate 13 opposite to the second direction Y may be multiplexed as a power connection line by the pixel unit on the side of the first plate 13 opposite to the second direction Y.

In an exemplary embodiment, two power connection lines 11 are provided across the first to fourth sub-pixels P1 to P4.

In an exemplary embodiment, the two power connection lines 11 are configured to be connected to first power lines, which are formed later, respectively, and supply power voltages to the second transistors T2 of the first, second, third, and fourth sub-pixels P1, P2, P2, P3, and P4, respectively.

In an exemplary embodiment, the two compensation connecting lines 12 may be bar-shaped structures extending along the first direction X and sequentially arranged along the first direction X. The two compensation lines 12 are located on one side of the first plate 13 in the second direction Y and between the first plate 13 and the power connection line 11 in the second direction Y. One compensation connection line 12 is disposed across the first and second sub-pixels P1 and P2 and supplies a compensation voltage to the third transistor T3 of the first and second sub-pixels P1 and P2, respectively; another compensation connection line 12 is provided across the third and fourth sub-pixels P3 and P4 and supplies a compensation voltage to the third transistor T3 of the third and fourth sub-pixels P3 and P3, respectively.

In an exemplary embodiment, the interlayer connection electrode 14 may be a stripe structure extending in the second direction Y. In the exemplary embodiment, the interlayer connection electrode 14 is an integrally formed structure with the first electrode plate 13.

In an exemplary embodiment, the first plate 13 may be multiplexed as a shielding layer.

In an exemplary embodiment, the first conductive layer thin film may be formed using a sputtering process. In an exemplary embodiment, the material of the first conductive layer may be molybdenum oxide MoOx, which is black in color, and has stable properties and is easily obtained; the material of the light-shielding film can be replaced by other materials as long as the light-shielding film is ensured to be light-tight.

In an exemplary embodiment, the first electrode plate 13 may block light incident from a side of the substrate 101 away from the shielding layer from affecting the thin film transistor in the display substrate, so as to prevent the thin film transistor from being irradiated by external light to cause a change in electrical characteristics, and thus, stability of the thin film transistor may be improved. For example, a semiconductor material used for an active layer of a thin film transistor has a photoconductive effect, and electrical characteristics such as an on-state current and an off-state current thereof are greatly changed in an optical state and a non-optical state, that is, a problem such as drift is easily caused in the optical state, thereby causing instability of electrical characteristics.

(2) A semiconductor layer pattern is formed.

In an exemplary embodiment, the forming of the semiconductor layer pattern may include: a first insulating film and a semiconductor film are sequentially deposited on the substrate 101 formed with the aforementioned patterns, and the semiconductor film is patterned through a patterning process to form a first insulating layer 20 covering the first conductive layer and a semiconductor layer pattern disposed on the first insulating layer 20, the semiconductor layer pattern including at least a first active layer 31, a second active layer 32, a third active layer 33, and a second plate 34 of a capacitor formed at each sub-pixel, as shown in fig. 9a and 9b, and fig. 9b is a schematic plan view of the semiconductor layer in fig. 9 a.

In an exemplary embodiment, the first active layer 31 may be positioned at one side of the second plate 34 opposite to the second direction Y. The first active layer 31 may include a first region 31-1 and a second region 31-2 connected to each other. In an exemplary embodiment, the second region 31-2 of the first active layer 31 may be connected with the second electrode plate 34, and the first active layer 31 and the second electrode plate 34 may be an integral structure connected with each other.

In an exemplary embodiment, as shown in fig. 9b, the first region 31-1 of the first active layer 31 may include a first portion a1 and a second portion a2 connected to each other. The first portion a1 of the first and third sub-pixels P1 and P3 may have a stripe structure extending in the first direction X, the second portion a2 may have a stripe structure extending in the second direction Y, and the first portion a1 is located at one side of the second portion a2 in the first direction X. The first portion a1 of the second and fourth sub-pixels P2 and P4 may have a stripe structure extending in the first direction X, and the second portion a2 may have a stripe structure extending in a direction forming an angle of 30 ° to 80 ° with respect to the opposite direction of the first direction X, and the first portion a1 is located at one side of the second portion a2 opposite to the first direction X.

In an exemplary embodiment, as shown in fig. 9c, which is another schematic plan view of the semiconductor layer in fig. 9a, the first portion a1 in the second and fourth sub-pixels P2 and P4 may have a stripe structure extending along the first direction X, the second portion a2 may have a stripe structure extending along the second direction Y, and the first portion a1 is located at one side of the second portion a2 opposite to the first direction X.

In an exemplary embodiment, the second region 31-2 of the first active layer 31 may be a stripe structure extending along the second direction, and an orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with an orthographic projection of the first electrode plate 13 on the substrate.

In an exemplary embodiment, the second active layer 32 may be a stripe structure extending in the second direction Y. The second active layer 32 may be positioned at a side of the second plate 34 opposite to the second direction Y, and in the first and third sub-pixels P1 and P3, the second active layer 32 is positioned at a side of the second region 31-2 of the first active layer 31 opposite to the first direction X; in the second and fourth sub-pixels P2 and P4, the second active layer 32 is positioned at one side of the first direction X of the second region 31-2 of the first active layer 31. The orthographic projection of the second active layer 32 on the substrate 101 is within the range of the orthographic projection of the first plate 13 on the substrate 101. The second active layer 32 may include first and second regions 32-1 and 32-2 symmetrically disposed along a center line of the first direction X. The first plate 13 can shield the channel region of the second active layer 32, thereby preventing light from affecting the channel and reducing leakage current, and further preventing light from affecting the characteristics of the transistor.

In an exemplary embodiment, the third active layer 33 may be a stripe structure extending along the second direction Y, and the third active layer 33 is located at one side of the second plate 34 in the second direction Y. The third active layer 33 may include a first region 33-1 and a second region 33-2 symmetrically disposed along a center line of the first direction X.

In an exemplary embodiment, in each sub-pixel, the shape of the second plate 34 may be similar to the shape of the first plate 13 in the sub-pixel, and the orthographic projection of the second plate 34 on the substrate is within the range of the orthographic projection of the first plate 13 on the substrate. In an exemplary embodiment, the area of the second plate 34 in the first and third sub-pixels P1 and P3 is greater than the area of the second plate 34 in the second and fourth sub-pixels P2 and P4.

In example embodiments, the semiconductor layer may employ a metal oxide such as an oxide containing indium and tin, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, an oxide containing indium and gallium and zinc, or the like. The semiconductor layer may be a single layer, or may be a double layer, or may be a multilayer.

(3) Forming a second conductive layer pattern.

In an exemplary embodiment, the forming of the second conductive layer pattern may include: a second insulating film and a second conductive film are sequentially deposited on the substrate 101 on which the aforementioned patterns are formed, and the second conductive film is patterned through a patterning process to form a second insulating layer 40 covering the semiconductor layer and a second conductive layer pattern disposed on the second insulating layer 40, where the second conductive layer pattern at least includes the first scan signal line 51, the second scan signal line 52, the spare signal line 53, the second gate electrode 54, the auxiliary compensation line 55, the auxiliary data line 56, and the auxiliary power line 57, as shown in fig. 10a and 10b, and fig. 10b is a schematic plan view of the second conductive layer in fig. 10 a. In an exemplary embodiment, the second conductive layer may be referred to as a GATE metal (GATE) layer.

In the exemplary embodiment, the first scan signal line 51 is a stripe structure extending along the first direction X and is located at one side of the second direction Y of the second electrode 34. The first scanning signal line 51 spans the first sub-pixel P1 to the fourth sub-pixel P4, a first gate electrode 51-1 is disposed on the first scanning signal line 51 corresponding to each sub-pixel, the first gate electrode 51-1 is used as a gate electrode of the first transistor T1, and an overlapping region exists between an orthographic projection of the first gate electrode 51-1 on the substrate and an orthographic projection of the first active layer 31 on the substrate. In the exemplary embodiment, the first gate electrode 51-1 extends in the second direction Y, and an orthographic projection of the first gate electrode 51-1 on the substrate 101 has an overlapping region with an orthographic projection of the first portion a1 of the first active layer 31 on the substrate.

In an exemplary embodiment, the first scanning signal lines 51 may be disposed in an equal width, which is a dimension of the first scanning signal lines 51 in the second direction Y. The first scanning signal line 51 may be provided with a plurality of second through holes 59, an orthogonal projection of the plurality of second through holes 59 on the substrate may overlap an orthogonal projection of a first power line, a data signal line, and a compensation signal line formed later on the substrate 101, and the plurality of second through holes 59 may be configured to reduce parasitic capacitance between the first scanning signal line 51 and the first power line, the data signal line, and the compensation signal line. When one of the two first communication lines b1 located on both sides of the second through hole 59 in the second direction Y is short-circuited with the first power line, the data signal line, and the compensation signal line formed later, the first communication line b1 with the short circuit may be cut off, and the other first communication line b1 transmits an electrical signal, so that the part of the first power line, the data signal line, and the compensation signal line formed later that is short-circuited with the first scanning signal line 51 is maintained on the premise that the first scanning signal line 51 normally transmits signals.

In an exemplary embodiment, the second scan signal lines 52 are stripe structures extending along the first direction X and are located at one side of the second direction Y of the second plate 34. The second scan signal line 52 is disposed across the first to fourth sub-pixels P1 to P4, and there is an overlapping region where an orthogonal projection of the second scan signal line 52 on the substrate 101 and an orthogonal projection of the third active layer 33 in each sub-pixel on the substrate, and the second scan signal line 52 of the overlapping region serves as a gate electrode of the third transistor T3.

In an exemplary embodiment, the second scan signal lines 52 may be disposed with an equal width, which is a dimension of the second scan signal lines 52 in the second direction Y. A plurality of second vias 59 may be disposed on the second scan signal line 52, an orthogonal projection of the plurality of second vias 59 on the substrate 101 may overlap an orthogonal projection of the first power line, the data signal line, and the compensation signal line, which are formed later, on the substrate 101, and the plurality of second vias 59 may be configured to reduce parasitic capacitances between the second scan signal line 52 and the first power line, the data signal line, and the compensation signal line. When one of the two second communication lines b2 located at two sides of the second through hole 59 in the second direction Y is short-circuited with the first power line, the data signal line and the compensation signal line formed later, the second communication line b2 with the short circuit can be cut off, and an electric signal is transmitted by the other second communication line b2, so that the part of the second scanning signal line 52 with the short circuit of the first power line, the data signal line and the compensation signal line formed later is maintained on the premise that the second scanning signal line 52 is ensured to normally transmit signals.

In an exemplary embodiment, the first and second

scan signal lines

51 and 52 may be disposed in parallel.

In an exemplary embodiment, the spare signal lines 53 may have a stripe structure extending in the first direction X and located at one side of the second direction Y of the second scan signal lines 52. The second scan signal line 52 is spanned among the first to fourth sub-pixels P1 to P4. The spare signal lines 53 may be arranged with an equal width, which is the dimension of the spare signal lines 53 in the second direction Y.

In an exemplary embodiment, the second gate electrode 54 is formed within each sub-pixel as a gate electrode of the second transistor T2. In each sub-pixel, on the one hand, an overlapping region exists between an orthographic projection of the second gate electrode 54 on the substrate 101 and an orthographic projection of the second active layer 32 on the substrate, and on the other hand, an overlapping region exists between an orthographic projection of the second gate electrode 53 on the substrate and the second region 31-2 of the first active layer 31.

In an exemplary embodiment, the auxiliary compensation line 55 is formed in the first and fourth sub-pixels P1 and P4 in a stripe structure extending along the second direction Y. In the first subpixel P1, the auxiliary compensation line 55 is positioned at one side of the second plate 34 opposite to the first direction X. In the fourth sub-pixel P4, the auxiliary compensation line 55 is located at one side of the second plate 34 in the first direction X. The auxiliary compensation line 55 is configured to be connected to a compensation signal line formed later, so as to form a double-layered routing, ensure reliability of transmission of the compensation signal, and reduce resistance of the compensation signal line.

In an exemplary embodiment, the auxiliary data line 56 is formed within each sub-pixel in a stripe structure extending along the second direction Y. In the first and third sub-pixels P1 and P3, the auxiliary data line 45 is positioned at one side of the second plate 34 in the first direction X. In the second and fourth sub-pixels P2 and P4, the auxiliary data line 56 is positioned at one side of the second plate 34 opposite to the first direction X. The auxiliary data line 56 is configured to be connected to a subsequently formed data signal line, forming a double-layer wiring, ensuring reliability of data signal transmission, and reducing resistance of the data signal line.

In an exemplary embodiment, the auxiliary power supply line 57 is formed between the second and third sub-pixels P2 and P3 in a stripe structure extending along the second direction Y. The auxiliary power line 57 is configured to be connected to a first power line formed later, so that a double-layer wire is formed, reliability of power signal transmission is ensured, and resistance of the first power line is reduced.

In an exemplary embodiment, the second gate electrodes 54 in the first and fourth sub-pixels P1 and P4 may be mirror-symmetrically disposed with respect to a vertical axis (the auxiliary power line 57), the second gate electrodes 43 in the second and third sub-pixels P2 and P3 may be mirror-symmetrically disposed with respect to a vertical axis (the auxiliary power line 57), the auxiliary compensation lines 55 in the first and fourth sub-pixels P1 and P4 may be mirror-symmetrically disposed with respect to a vertical axis (the auxiliary power line 57), the first scan signal lines 51 may be mirror-symmetrically disposed with respect to a vertical axis, the second scan signal lines 52 may be mirror-symmetrically disposed with respect to a vertical axis, and the spare signal lines 53 may be mirror-symmetrically disposed with respect to a vertical axis.

In an exemplary embodiment, the main body portions of the auxiliary power line 55, the auxiliary data line 56, and the auxiliary compensation line 57 may be disposed in parallel.

In an exemplary embodiment, the process further includes a conductimerization process. The conductive treatment is a treatment of forming a second conductive layer pattern, then performing plasma treatment using the second conductive layer as a mask, and the semiconductor layer in the region masked by the first gate electrode, the second gate electrode, and the third gate electrode is treated as a channel region of the transistor, and the semiconductor layer in the region not masked by the second conductive layer is treated as a conductive layer, thereby forming the second electrode plate 34 which is conductive and the source-drain region which is conductive.

(4) A third insulating layer pattern is formed.

In an exemplary embodiment, the forming of the third insulation layer pattern may include: depositing a third insulating film on the substrate 101 with the patterns, patterning the third insulating film by using a patterning process to form a third insulating layer 60 covering the second conductive layer, wherein the third insulating layer is provided with a plurality of via holes, and the via holes at least comprise: fig. 11a and 11b show that fig. 11a is a schematic plan view of a plurality of vias, and fig. 11b is a schematic sectional view of H-H positions in fig. 11 a.

In an exemplary embodiment, a first via hole V1 may be disposed at each sub-pixel, an orthographic projection of the first via hole V1 on the substrate 101 is located within an orthographic projection of the first region 31-1 of the first active layer 31 on the substrate, and the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose a surface of the first region 31-1 (first portion a1) of the first active layer 31. In an exemplary embodiment, the first via V1 is configured to connect a subsequently formed data signal line with the first active layer 31 through the via.

In an exemplary embodiment, a second via V2 may be disposed at each sub-pixel, an orthographic projection of the second via V2 on the substrate 101 is within an orthographic projection of the second region 31-2 of the first active layer 31 on the substrate, and an orthographic projection of the second via V2 on the substrate 101 at least partially overlaps an orthographic projection of the second gate electrode 54 on the substrate 101, and the third insulating layer and the second insulating layer within the second via V2 are etched away while exposing a surface of the second region 31-2 of the first active layer 31 and a surface of the second gate electrode 54. The second via hole V2 may be a transit via hole or a trepan structure in which a transit via hole is composed of two half holes, one half hole is formed on the second region 31-2 of the first active layer 31 and the other half hole is formed on the second gate electrode 54, such that the transit via hole composed of two half holes simultaneously exposes the surface of the second region 31-2 of the first active layer 31 and the surface of the second gate electrode 54. In an exemplary embodiment, the second via V2 is configured to allow the second pole of the subsequently formed first transistor T1 to simultaneously connect with the second gate electrode 54 and the first active layer 31 through the via.

In an exemplary embodiment, a third via hole V3 may be disposed at each sub-pixel, an orthographic projection of the third via hole V3 on the substrate 101 is located within a range of an orthographic projection of the first region 32-1 of the second active layer 32 on the substrate 101, and the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose a surface of the first region 32-1 of the second active layer 32. In an exemplary embodiment, the third via hole V3 is configured to allow a subsequently formed first power line or fifth connection electrode to be connected to the second active layer 32 through the via hole.

In an exemplary embodiment, a fourth via V4 may be disposed at each sub-pixel, an orthographic projection of the fourth via V4 on the substrate 101 at least partially overlaps an orthographic projection of the second region 32-2 of the second active layer 32 on the substrate on the one hand, and at least partially overlaps an orthographic projection of the first plate 13 on the substrate on the other hand, and the third insulating layer, the second insulating layer, and the first insulating layer within the fourth via V4 are etched away while exposing a surface of the second region 32-2 of the second active layer 32 and a surface of the first plate 13. In an exemplary embodiment, the fourth via V4 is configured to connect the second pole of the subsequently formed second transistor T2 with the first plate 13 and the second active layer 32 simultaneously through the via.

In an exemplary embodiment, a fifth via V5 may be disposed at each sub-pixel, an orthographic projection of the fifth via V5 on the substrate at least partially overlaps an orthographic projection of the first region 33-1 of the third active layer 33 on the substrate on the one hand and an orthographic projection of the compensation link line 12 on the substrate on the other hand, and the third insulating layer, the second insulating layer and the first insulating layer within the fifth via V5 are etched away while exposing a surface of the first region 33-1 of the third active layer 33 and a surface of the compensation link line 12. In an exemplary embodiment, the fifth via V5 is configured to connect the first pole of the subsequently formed third transistor T3 to the compensation connection line 12 and the third active layer 33 at the same time through the via.

In an exemplary embodiment, a sixth via V6 may be disposed at each sub-pixel, an orthographic projection of the sixth via V6 on the substrate 101 at least partially overlaps an orthographic projection of the second region 33-2 of the third active layer 33 on the substrate on the one hand and an orthographic projection of the interlayer connection electrode 14 on the substrate on the other hand, and the third insulating layer, the second insulating layer and the first insulating layer within the sixth via V6 are etched away while exposing a surface of the second region 33-2 of the third active layer 33 and a surface of the interlayer connection electrode 14. In an exemplary embodiment, the sixth via V6 is configured such that the second pole of the subsequently formed third transistor T3 is simultaneously connected with the interlayer connection electrode 14 and the third active layer 33 through the via, and the third transistor T3 is connected with the first plate 13 of the capacitor through the connection of the interlayer connection electrode 14.

In an exemplary embodiment, the seventh via V7 may be disposed between the second sub-pixel p2 and the third sub-pixel p3, an orthogonal projection of the seventh via V7 on the substrate is located within an orthogonal projection of the middle portion of the power connection line 11 on the substrate, and the third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 are etched away to expose a surface of the middle portion of the power connection line 11. In an exemplary embodiment, the seventh via V7 is configured to connect the first power line formed later with the power connection line 11 through the via.

In an exemplary embodiment, the eighth via V8 may be disposed at the first and fourth sub-pixels P1 and P4, an orthogonal projection of the eighth via V8 on the substrate is located within a range of orthogonal projections of both ends of the power connection line 11 on the opposite side of the first plate 13 in the second direction Y on the substrate, and the third, second, and first insulating layers within the eighth via V8 are etched away to expose surfaces of both ends of the power connection line 11. In an exemplary embodiment, the eighth via V8 is configured to connect the first pole of the subsequently formed second transistor T2 located in the third and fourth sub-pixels p3 and p4 with the end of the power connection line 11 through the via.

In an exemplary embodiment, a ninth via V9 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, an orthogonal projection of the ninth via V9 on the substrate is within an orthogonal projection of the auxiliary power line 57 on the substrate, and the third insulating layer in the ninth via V9 is etched away to expose a surface of the auxiliary power line 57. In an exemplary embodiment, the ninth via V9 is configured to allow a subsequently formed first power line to be connected to the auxiliary power line 57 through the via. In an exemplary embodiment, the ninth via V9 may include a plurality, and the plurality of ninth vias V9 may be sequentially arranged along the second direction Y to increase the connection reliability of the first power line and the auxiliary power line 57.

In an exemplary embodiment, a tenth via V10 may be disposed at each sub-pixel, an orthographic projection of the tenth via V10 on the substrate is within an orthographic projection of the auxiliary data line 56 on the substrate, and the third insulating layer within the tenth via V10 is etched away to expose a surface of the auxiliary data line 56. In an exemplary embodiment, the tenth via V10 is configured to connect a subsequently formed data signal line with the auxiliary data line 56 through the via. In an exemplary embodiment, the tenth via V10 may include a plurality, and a plurality of tenth vias V10 may be sequentially arranged along the second direction Y to increase the connection reliability of the data signal line and the auxiliary data line 56.

In an exemplary embodiment, an eleventh via V11 may be disposed at the first and fourth sub-pixels P1 and P4, an orthogonal projection of the eleventh via V11 on the substrate is located within an orthogonal projection of the auxiliary compensation line 55 on the substrate, and the third insulating layer in the eleventh via V11 is etched away to expose a surface of the auxiliary compensation line 55. In an exemplary embodiment, the eleventh via V11 is configured to connect a subsequently formed compensation signal line with the auxiliary compensation line 55 through the via. In an exemplary embodiment, the eleventh via V11 may include a plurality, and the plurality of eleventh vias V11 may be sequentially arranged along the second direction Y to increase the connection reliability of the compensation signal line and the auxiliary compensation line 55.

In an exemplary embodiment, the spare half via Vm may be disposed at the first to fourth sub-pixels P1 to P4, an orthogonal projection of the spare half via Vm on the substrate is located within a range of an orthogonal projection of the spare signal line 53 on the substrate, a portion of the third insulating layer within the spare half via Vm is etched, and a surface of the spare signal line 53 is not exposed. In the exemplary embodiment, the spare half via Vm is configured such that at least one of the first power line 61, the data signal line 62, and the compensation signal line 63, which are formed later, is connected to the spare signal line 53 by opening the spare half via.

(5) Forming a third conductive layer pattern.

In an exemplary embodiment, the forming of the third conductive layer may include: depositing a third conductive film on the substrate on which the patterns are formed, patterning the third conductive film by adopting a patterning process, and forming a third conductive layer arranged on the third insulating layer, wherein the third conductive layer at least comprises: the first power line 61, the data signal line 62, the compensation signal line 63, the first connection electrode 64, the second connection electrode 65, the third connection electrode 66, the fourth connection electrode 67, and the fifth connection electrode 68, as shown in fig. 12a and 12b, and fig. 12b is a schematic plan view of the third conductive layer in fig. 12 a. In an exemplary embodiment, the third conductive layer may be referred to as a source drain metal (SD) layer.

In an exemplary embodiment, the first power line 61 is disposed between the second and third sub-pixels P2 and P3, and a main portion of the first power line 61 extends in the second direction Y. The first power line 61 is connected to the auxiliary power line 57 through a plurality of 9 th vias V9 such that the first power line 61 and the auxiliary power line 57 form a double-layered routing.

In the exemplary embodiment, the first power supply line 61 is provided with a first protrusion 61-1 and a second protrusion 61-2. The first end of the first protrusion 61-1 is connected to the first power line 61, the second end of the first protrusion 61-1 extends to the second sub-pixel P2 along the reverse direction of the first direction X, and is connected to the first region 32-1 of the second active layer 32 through the third via hole V3 of the sub-pixel, writing the power signal to the second transistor T2 of the second sub-pixel P2. A first end of the second protrusion 61-2 is connected to the first power line 61, a second end of the second protrusion 61-2 extends to the third sub-pixel P3 along the first direction X, and is connected to the first region 32-1 of the second active layer 32 through the third via hole V3 of the sub-pixel, writing a power signal to the second transistor T2 of the third sub-pixel P3.

In an exemplary embodiment, the data signal line 62 is disposed at each sub-pixel, respectively, and a main portion of the data signal line 62 extends along the second direction Y. On one hand, the data signal line 62 is connected to the first region 31-1 of the first active layer 31 through the first via V1 to implement writing of the data signal into the first transistor T1, and on the other hand, the data signal line 62 is connected to the auxiliary data line 56 through the tenth vias V10, such that the data signal line 62 and the auxiliary data line 56 form a dual-layer trace.

In an exemplary embodiment, the data signal line 62 is provided with a signal line connection portion 62-1 (i.e., the second branch portion of the data signal line 62 described above) and a first spare connection electrode 62-2. The signal line connection part 62-1 and the first spare connection electrode 62-2 in the first and third sub-pixels P1 and P3 extend along the opposite side of the body portion of the data signal line 62 in the first direction X, and the signal line connection part 62-1 is connected to the first region 31-1 of the first active layer 31 through the first via hole V1, enabling writing of a data signal into the first transistor T1; the signal line connection part 62-1 and the first spare connection electrode 62-2 in the second and fourth sub-pixels P2 and P4 extend in the body portion first direction X of the data signal line 62, and the signal line connection part 62-1 is connected to the first region 31-1 of the first active layer 31 through the first via hole V1, enabling writing of a data signal into the first transistor T1; the orthographic projection of the spare half via Vm on the substrate is positioned in the range of the orthographic projection of the first spare connecting electrode 62-2 on the substrate, and the spare half via Vm is opened to realize the electrical connection between the first spare connecting electrode 62-2 and the spare signal line 53. In an exemplary embodiment, the first spare connection electrode 62-2 and the data signal line 62 may be an integrally formed structure.

In an exemplary embodiment, the compensation signal lines 63 are disposed at the first and fourth sub-pixels P1 and P4, respectively, and a main portion of the compensation signal lines 63 extends along the second direction Y. On the one hand, the compensation signal line 63 is connected to the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fourth connection electrode 67 and the fifth via V5 to implement writing of the compensation signal into the third transistor T3, and on the other hand, the compensation signal line 63 is connected to the auxiliary compensation line 55 through the plurality of eleventh vias V11 such that the compensation signal line 63 and the auxiliary compensation line form a dual-layer trace.

In an exemplary embodiment, the first connection electrode 64 is disposed at each sub-pixel, respectively, and may have a rectangular shape. The first connection electrode 64 in each sub-pixel is simultaneously connected with the second region 31-2 of the first active layer 31 and the second gate electrode 54 through the second via hole V2. In an exemplary embodiment, the first connection electrode 64 serves as a second pole of the first transistor T1. Since the second region 31-2 of the first active layer 31 is connected to the second plate 34, the first connection electrode 64 makes the second pole of the first transistor T1, the second gate electrode 54, and the second plate 34 have the same potential, i.e., the potential of the first node N1.

In an exemplary embodiment, the second connection electrode 65 is disposed at each sub-pixel, respectively, and may have a rectangular shape. The second connection electrode 65 in each sub-pixel is simultaneously connected with the second region 32-2 of the second active layer 32 and the first plate 13 through the fourth via hole V4. In an exemplary embodiment, the second connection electrode 65 serves as a second pole of the second transistor T2. Since the second connection electrode 65 is connected to the first pad 13, the second connection electrode 65 makes the second pole of the second transistor T2 and the first pad 13 have the same potential, i.e., the potential of the first node N2.

In an exemplary embodiment, the third connection electrode 66 is disposed at each sub-pixel, respectively, and may have a rectangular shape. The third connection electrode 66 in each sub-pixel is simultaneously connected with the second region 33-2 of the third active layer 33 and the interlayer connection electrode 14 through the sixth via hole V6. In an exemplary embodiment, the third connection electrode 66 serves as a second pole of the third transistor T3. Since the interlayer connection electrode 14 is connected to the first plate 13, the third connection electrode 66 makes the second pole of the third transistor T3 and the first plate 13 have the same potential.

Since the second connection electrode 65 makes the first plate 13 and the second pole of the second transistor T2 have the same potential and the third connection electrode 66 makes the first plate 13 and the second pole of the third transistor T3 have the same potential, the second pole of the second transistor T2, the second pole of the third transistor T3 and the first plate 11 have the same potential, that is, the potential of the second node N2.

In an exemplary embodiment, the fourth connection electrode 67 is disposed at the first and fourth sub-pixels P1 and P4, respectively, and may be a stripe structure extending in the first direction X; the fourth connection electrode 67 and the compensation signal line 63 disposed in the first sub-pixel P1 may be of an integrally molded structure, the fourth connection electrode 67 is located at one side of the compensation signal line 63 in the first direction X, and the fourth connection electrode 67 in the first sub-pixel P1 is simultaneously connected with the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fifth via hole V5 of the sub-pixel. In an exemplary embodiment, the fourth connection electrode 67 serves as a first pole of the third transistor T3. Since the compensation connection line 12 is connected to the compensation signal line 63, the fourth connection electrode 67 may write a compensation signal to the third transistor T3 of the first subpixel P1. The fourth connection electrode 67 and the compensation signal line 63 disposed in the fourth sub-pixel P4 may be of an integrally molded structure, the fourth connection electrode 67 is located at a side opposite to the first direction X of the compensation signal line 63, and the fourth connection electrode 67 in the fourth sub-pixel P4 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 12 through the fifth via hole V5 of the sub-pixel. In an exemplary embodiment, the fourth connection electrode 67 serves as a first pole of the third transistor T3. Since the compensation connection line 12 is connected to the compensation signal line 63, the fourth connection electrode 67 may write a compensation signal to the third transistor T3 of the fourth sub-pixel P4.

In an exemplary embodiment, the fifth connection electrode 68 is disposed at the first and fourth sub-pixels P1 and P4, respectively, and may be a stripe structure extending along the second direction Y. A first end of the fifth connection electrode 68 is connected to the power connection line 11 through the eighth via V8, and a second end of the fifth connection electrode 68 is connected to the first region 32-1 of the second active layer 32 through the third via V3 of the sub-pixel. In an exemplary embodiment, the fifth connection electrode 68 serves as a first pole of the second transistor T2. Since the power connection line 11 is connected to the first power line 61, the fifth connection electrode 68 may write the power signal to the second transistor T2 of the first and fourth sub-pixels P1 and P4.

The present exemplary embodiment realizes the writing of the power supply signal to the second transistors T2 of the four sub-pixels, respectively, by providing the first power supply line 61 extending along the second direction Y and the power supply connection line 11 extending along the first direction X. Here, in the second and third sub-pixels P2 and P3, the first power line 61 is directly connected to the second transistor T2 through a via hole, respectively. In the first and fourth sub-pixels P1 and P4, the first power line 61 is connected to the second transistor T2 through the fifth connection electrode 68, respectively.

In an exemplary embodiment, as shown in fig. 12c and 12d, fig. 12d is a schematic plan view of the third conductive layer in fig. 12 c. At least one side of the body portion of the first power line 61, which is on the side of the first direction X and on the side opposite to the first direction X, may be provided with a second spare connection electrode 61-3, the second spare connection electrode 61-3 being in the second sub-pixel P2 and/or the third sub-pixel P3; a second spare connection electrode 61-3 in the second subpixel P2, a first end of the second spare connection electrode 61-3 being connected to the first power line 61, a second end of the second spare connection electrode 61-3 extending in a direction opposite to the first direction X; and a second alternate connection electrode 61-3 in the third subpixel P3, a first end of the second alternate connection electrode 61-3 being connected to the first power line 61, and a second end of the second alternate connection electrode 61-3 extending in the first direction X. The orthographic projection of the spare half via hole Vm on the substrate is positioned in the range of the orthographic projection of the second spare connecting electrode 61-3 on the substrate, and the electrical connection between the second spare connecting electrode 61-3 and the spare signal line 53 can be realized by opening the spare half via hole Vm. In an exemplary embodiment, the second spare connection electrode 61-3 and the first power line 61 may be an integrally molded structure.

In an exemplary embodiment, the compensation signal line 63 may be provided with a third spare connection electrode 63-1 at one side of the first direction X and/or an opposite direction of the first direction X, the third spare connection electrode 63-1 being positioned in the first and fourth sub-pixels P1 and P4, the third spare connection electrode 63-1 in the first sub-pixel P1, a first end of the third spare connection electrode 63-1 being connected to the compensation signal line 63, a second end of the third spare connection electrode 63-1 extending in the first direction X; and a third alternate connection electrode 63-1 positioned in the fourth subpixel P4, a first end of the third alternate connection electrode 63-1 being connected to the compensation signal line 63, and a second end of the third alternate connection electrode 63-1 extending in a direction opposite to the first direction X. The orthographic projection of the spare half via hole Vm on the substrate is positioned in the range of the orthographic projection of the third spare connecting electrode 63-1 on the substrate, and the spare half via hole Vm is opened to realize the electric connection between the third spare connecting electrode 63-1 and the spare signal line 53. In an exemplary embodiment, the third spare connection electrode 63-1 and the compensation signal line 63 may be an integrally formed structure. In an exemplary embodiment, as shown in fig. 13, two adjacent pixel units may share one compensation signal line 53, and both sides of the compensation signal line 53 in the two adjacent pixel units are provided with a third spare connection electrode 63-1 and a fourth connection electrode 67.

In an exemplary embodiment, in the structure shown in fig. 13, each pixel unit includes four sub-pixels P1 to P4, wherein the first sub-pixel P1 may be a green sub-pixel (G) emitting green light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 may be a red sub-pixel (R) emitting red light, and the fourth sub-pixel P4 may be a white sub-pixel (W) emitting white light. As shown in fig. 13, the areas of the plates (the first plate 13 and the second plate 34) of the capacitors in the first sub-pixel P1 and the third sub-pixel P3 in the plane of the display substrate are larger than the areas of the plates (the first plate 13 and the second plate 34) of the capacitors in the second sub-pixel P2 and the fourth sub-pixel P4 in the plane of the display substrate, so that the capacitors in the first sub-pixel P1 and the third sub-pixel P3 can store more electric quantity to satisfy the larger driving current required for driving the light emitting diodes corresponding to the red sub-pixel (i.e., the third sub-pixel P3) and the green sub-pixel (i.e., the first sub-pixel P1).

The present exemplary embodiment realizes the third transistor T3 for writing the compensation signals to the four sub-pixels, respectively, by providing two compensation signal lines 63 having the body portions extending in the second direction Y and two compensation connection lines 12 extending in the first direction X. Here, in the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line 53 is directly connected to the third transistor T3 through a via hole, respectively. In the second sub-pixel P2 and the third sub-pixel P3, the compensation signal line 63 is connected to the third transistor T3 through the compensation connection line 12, respectively. The two compensation signal lines are arranged to provide the compensation signals for the four sub-pixels, so that the RC delay of the compensation signals before being written into the transistor can be basically the same, and the display uniformity is ensured.

The present exemplary embodiment achieves writing of data signals to the first transistors T1 of the four sub-pixels, respectively, by providing the data signal line 62 extending in the second direction Y in each sub-pixel, the data signal line 62 being connected to the first transistor T1 of the present sub-pixel through a via hole.

In an exemplary embodiment, the first power line 61, the data signal line 62, and the compensation signal line 63 may be straight lines or polygonal lines of equal width, or straight lines or polygonal lines of unequal width.

Fig. 14a is a schematic sectional view at L-L in fig. 12c and fig. 13, and fig. 14b is a schematic sectional view at W-W in fig. 12 c.

As shown in fig. 15a, in order to repair the disconnected position of the data signal line 62 through the spare signal line 53, for example, in the case where the data signal D13 of the third subpixel P3 in the first pixel unit M1 is transmitted in the data signal line 62 in the reverse direction of the second direction Y, and the data signal line 62 of the third subpixel P3 in the first pixel unit M1 is disconnected at the a1 position, the data signal D13 cannot be acquired by the third subpixel P3 located at the disconnection position a1 on the reverse side of the second direction Y, the crossing position of the data signal line 62 at the reverse side of the second direction Y where the disconnection position a1 occurs and the spare signal line 53 at the reverse side of the second direction Y where the disconnection position a1 occurs (i.e., the position of the first spare connection electrode 62-2, the B1 position in fig. 15 a) is laser-punched, so that the first spare connection electrode 62-2 and the spare signal line 53 are fused, the spare signal line 53 is electrically connected to the data signal line 62 with the broken line, the data signal line 62 of the third pixel P3 in the second pixel unit M2 is laser-punched at the C1 position, so that the first spare connection electrode 62-2 at the C1 position is melted with the spare signal line 53, the spare signal line 53 is electrically connected to the data signal line 62 at the C1 position, and since the data signal lines 62 at the B1 position and the C1 position are electrically connected to the spare signal line 53, the signal provided by the data signal line 62 of the third sub-pixel P3 in the second pixel unit M2 can be transmitted from the spare signal line 53 to the data signal line 62 of the third sub-pixel P3 in the first pixel unit M1, thereby realizing the repair of the data signal line 62 with the broken line.

As shown in fig. 15B, for example, in the first pixel cell M1, the first power line 61 is broken at a position a2, the pixel cell located at the opposite side of the broken line position a2 in the second direction Y cannot obtain several first power signals, the first power line 61 at the opposite side of the second direction Y at the broken line position a2 is laser-punched at the crossing position (i.e., the position of the second spare connection electrode 61-3, the position of B2 in fig. 15B) of the first power line 61 at the opposite side of the second direction Y at the broken line position a2 and the spare signal line 53 at the opposite side of the second direction Y at the broken line position a2, so that the second spare connection electrode 61-3 is fused with the spare signal line 53, the spare signal line 53 is electrically connected to the first power line 61 at which the broken line occurs, the first power line 61 in the second pixel cell M2 is laser-punched at a position C2, the second spare connection electrode 61-3 at the position of C2 is fused with the spare signal line 53, so that the spare signal line 53 is electrically connected with the first power line 61 at the position of C2, and since the first power line 61 at the positions of B2 and C2 are electrically connected with the spare signal line 53, the signal provided by the first power line 61 in the second pixel unit M2 can be transmitted to the first power line 61 of the first pixel unit M1 through the spare signal line 53, so that the maintenance of the first power line 61 with broken line is realized.

As shown in fig. 15C, in order to repair the disconnected position of the compensation signal line 63 through the spare signal line 53, for example, the compensation signal line 63 between the first pixel cell M1 and the second pixel cell M2 is disconnected at the A3 position, the pixel cell located at the opposite side of the disconnection position A3 in the second direction Y cannot acquire the number compensation signal, the crossing position of the compensation signal line 63 at the opposite side of the second direction Y at the disconnection position A3 and the spare signal line 53 at the opposite side of the second direction Y at the disconnection position A3 (i.e., the position of the third spare connection electrode 63-1, the B3 position in fig. 15C) is laser-punched, so that the third spare connection electrode 63-1 and the spare signal line 53 are melted, the spare signal line 53 is electrically connected to the compensation signal line 63 at which the disconnection occurs, the compensation signal line 63 at the second direction Y side of the second pixel cell M2 is laser-punched at the C3 position, the third spare connection electrode 63-1 at the position of C3 is fused with the spare signal line 53, so that the spare signal line 53 is electrically connected with the compensation signal line 63 at the position of C3, and since the compensation signal lines 63 at the positions of B3 and C3 are electrically connected with the spare signal line 53, the signal provided by the compensation signal line 63 at the side of the second pixel unit M2 along the first direction X can be transmitted to the compensation signal line 63 of the first pixel unit M1 through the spare signal line 53, so that the maintenance of the compensation signal line 63 with broken lines is realized.

In an exemplary embodiment, in fig. 15c, the third spare connection electrode 63-1 at the position B4 and the spare signal line 53 may be laser-punched to electrically connect the spare signal line 53 and the compensation signal line 63 in the first pixel cell M1, in which a disconnection occurs; the third spare connection electrode 63-1 at the position of C4 and the spare signal line 53 are laser-punched to electrically connect the spare signal line 53 and the compensation signal line 63 of the second pixel unit M2.

FIG. 15d is a schematic cross-sectional view taken along the line U-U in FIG. 15c, wherein Q is the position where the third spare connecting electrode 63-1 is electrically connected to the spare signal line 53 after being melted after laser drilling.

In an embodiment of the present disclosure, the first active layer may be an active layer of the first transistor, the second active layer may be an active layer of the second transistor, and the third active layer may be an active layer of the third transistor.

The embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the display substrate may include a plurality of pixel units arranged in an array, each pixel unit includes a plurality of sub-pixels, and at least one sub-pixel includes a driving circuit layer disposed on a substrate; the preparation method comprises the following steps:

when any one first signal line is broken, the spare signal line is communicated with the spare connecting electrode on the first signal line with broken circuit, and the spare signal line is communicated with the spare connecting electrode on the first signal line without broken circuit, and the first signal line without broken circuit and the first signal line with broken circuit provide the same signal.

In an exemplary embodiment, a pixel unit in which the first signal line in which the open circuit occurs is located and a pixel unit in which the first signal line in which the open circuit does not occur is located include the same spare signal line.

In an exemplary embodiment, the first signal line may include a data signal line, a first power line, and a compensation signal line, and the spare connection electrode may include a first spare connection electrode on the data signal line, a second spare connection electrode on the first power line, and a third spare connection electrode on the compensation signal line.

In the exemplary embodiment, the first power supply signal lines in different pixel units are all supplied with power supply signals, which can be regarded as the same kind of signals. The compensation signal lines in different pixel units all provide compensation signals, which can be considered as the same kind of signals. When the same pixel unit comprises four sub-pixels, namely a first sub-pixel p1, a second sub-pixel p2, a third sub-pixel p3 and a fourth sub-pixel p4, four data signal lines for providing data signals to the four sub-pixels p1 to p4 provide signals which are not the same type of signals; the two data signal lines of the two pixel units supplying the data signal to the first subpixel p1 belong to the same kind of signal, for example, the data signal line supplying the data signal to the first subpixel p1 in the first pixel unit and the data signal line supplying the data signal to the first subpixel p1 in the second pixel unit supply the same kind of signal, that is, the data signal line supplying the data signal to the same kind of subpixel, the supplied signals belong to the same kind of signal, and the data signal lines supplying the data signal to the different kinds of subpixels, the supplied signals do not belong to the same kind of signal.

In an exemplary embodiment, when the first signal line with the open circuit is a data signal line, for example, the data signal line of the first sub-pixel p1 in the first pixel unit M1 has an open circuit, the first spare connection electrode on the data signal line with the open circuit in the first pixel unit M1 is connected to the spare signal line, and the first spare connection electrode on the data signal line of the first sub-pixel p1 in the second pixel unit M2 is connected to the spare signal line, so that the data signal line of the first sub-pixel p1 in the second pixel unit M2 provides a corresponding data signal to the first sub-pixel p1 in the first pixel unit M1.

In an exemplary embodiment, when the first signal line in which the open circuit occurs is a first power line, for example, the first power line in the first pixel unit M1 is open, the second spare connection electrode on the first power line in which the open circuit occurs in the first pixel unit M1 is opened with the spare signal line, and the second spare connection electrode on the first power line in the second pixel unit M2 is opened with the spare signal line, so that the first power line in the second pixel unit M2 supplies the power signal to the sub-pixel in the first pixel unit M1.

In an exemplary embodiment, when the disconnected first signal line is a compensation signal line, for example, the compensation signal line in the first pixel unit M1 is disconnected, the third spare connection electrode on the compensation signal line in the first pixel unit M1 is opened to the spare signal line, and the third spare connection electrode on the compensation signal line in the second pixel unit M2 is opened to the spare signal line, so that the compensation signal line in the second pixel unit M2 provides the compensation signal to the corresponding sub-pixel in the first pixel unit M1. In another embodiment, when the first pixel unit M1 includes two compensation signal lines, and one of the compensation signal lines is disconnected, the third spare connection electrode on the compensation signal line with the disconnection in the first pixel unit M1 may be connected to the compensation signal line, and the third spare connection electrode on the compensation signal line without the disconnection in the first pixel unit M1 may be connected to the compensation signal line, so that the compensation signal line without the disconnection provides the compensation signal to the sub-pixel corresponding to the disconnection.

The embodiment of the present disclosure further provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display substrate is characterized by comprising a plurality of pixel units arranged in an array, wherein each pixel unit comprises a plurality of sub-pixels, at least one sub-pixel comprises a driving circuit layer arranged on a substrate, and the driving circuit layer comprises a standby signal line and a plurality of first signal lines which are insulated and crossed with the standby signal line;

2. The display substrate according to claim 1, wherein the driving circuit layer of at least one sub-pixel comprises a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer sequentially disposed on the substrate, wherein the spare signal line is disposed on the second conductive layer, and the plurality of first signal lines are disposed on the third conductive layer.

3. The display substrate according to claim 2, wherein the third insulating layer is provided with a spare half via filled with the spare connecting electrode, and an orthographic projection of the spare half via on the base is within a range of the first overlapping area.

4. The display substrate according to any one of claims 1 to 3, wherein in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines include data signal lines, and the spare connection electrodes include first spare connection electrodes;

5. The display substrate according to any one of claims 1 to 3, wherein in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines include a first power line, and the spare connection electrode includes a second spare connection electrode;

the main portion of the first power line extends in the second direction, the second dummy connection electrode in the second sub-pixel extends in a direction opposite to the first direction, and the second dummy connection electrode in the third sub-pixel extends in the first direction.

6. The display substrate according to any one of claims 1 to 3, wherein in a plane of the display substrate, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged in sequence along a first direction; the plurality of first signal lines include a compensation signal line, and the spare connection electrode includes a third spare connection electrode;

7. The display substrate according to any one of claims 1 to 3, wherein the spare signal lines are located in at least two pixel units.

8. The display substrate according to claim 2 or 3, wherein in at least one of the sub-pixels, the driving circuit further comprises a first transistor, a second transistor, and a third transistor; the active layers of the first transistor, the second transistor and the third transistor are located on the semiconductor layer, the gate electrodes of the first transistor, the second transistor and the third transistor are located on the second conductive layer, and the first poles and the second poles of the first transistor, the second transistor and the third transistor are located on the third conductive layer.

9. The display substrate of claim 8, wherein in at least one of the sub-pixels, the driving circuit further comprises a shielding layer, the shielding layer is located on the first conductive layer, and an orthographic projection of the active layer of the second transistor on the substrate is within an orthographic projection range of the shielding layer on the substrate.

10. The display substrate according to claim 9, wherein in a plane of the display substrate, the plurality of sub-pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel which are sequentially arranged along a first direction; the shielding layer is reused as a first polar plate of the capacitor; the semiconductor layer includes a second plate formed at each sub-pixel;

11. The display substrate according to claim 10, wherein the second conductive layer further comprises a first scan signal line, a second scan signal line, and a second gate electrode; the first scanning signal line, the second scanning signal line and the standby signal line are arranged along a second direction;

the first scanning signal line comprises a main body part and a branch part, the main body part is of a strip-shaped structure extending along a first direction and is positioned on one side, far away from the second scanning signal line, of the second polar plate in a second direction, the branch part extends along the second direction, the branch part comprises a first gate electrode corresponding to each sub-pixel, the first gate electrode is used as a gate electrode of a first transistor, and an overlapping region exists between the orthographic projection of the first gate electrode on the substrate and the orthographic projection of an active layer of the first transistor on the substrate;

the second gate electrode is used as a gate electrode of a second transistor, a second overlapping region exists between an orthographic projection of the second gate electrode on the substrate and an orthographic projection of an active layer of the second transistor on the substrate, and a third overlapping region exists between the second gate electrode, the second pole of the first transistor and the orthographic projection of the active layer of the first transistor on the substrate.

12. The display substrate according to claim 8, wherein the first signal line comprises a data signal line provided at each of the sub-pixels, respectively, the data signal line comprising a main portion and a second branch portion, the main portion of the data signal line extending in the second direction; the second branch portions in the first and third sub-pixels extend in a direction opposite to the first direction, and the second branch portions in the second and fourth sub-pixels extend in the first direction; the second branch portion is a first pole of the first transistor.

13. The preparation method of a display substrate is characterized in that the display substrate comprises a plurality of pixel units which are arranged in an array, each pixel unit comprises a plurality of sub-pixels, and at least one sub-pixel comprises a driving circuit layer arranged on a substrate; the preparation method comprises the following steps:

14. The method for repairing the display substrate is characterized in that the display substrate comprises a plurality of pixel units which are arranged in an array mode, each pixel unit comprises a plurality of sub-pixels, at least one sub-pixel comprises a driving circuit layer arranged on a base, and the driving circuit layer comprises a spare signal line and a plurality of first signal lines which are in insulation intersection with the spare signal line; the first signal line comprises a spare connecting electrode, and a first overlapping area exists between the orthographic projection of the spare connecting electrode on the substrate and the orthographic projection of the spare signal line on the substrate; the repairing method comprises the following steps:

15. A display device comprising the display substrate according to any one of claims 1 to 12.