CN115000087A - Array substrate and preparation method thereof - Google Patents

Abstract

The application provides an array substrate and a preparation method thereof, wherein the array substrate comprises: a substrate; a buffer layer on one side of the substrate; the buffer layer comprises a first surface, a first inclined surface and a second inclined surface, the first inclined surface and the second inclined surface are respectively connected with two ends of the first surface, and the first inclined surface and the second inclined surface are respectively inclined relative to the first surface; and an active layer on the buffer layer; the active layer comprises a source region, a drain region and a channel region positioned between the source region and the drain region; the channel region, the source region and the drain region are respectively positioned on the first surface, the first inclined surface and the second inclined surface; the grid electrode is positioned on one side of the active layer and is opposite to the position of the channel region; and the source electrode and the drain electrode are positioned on one side of the active layer and are respectively electrically connected with the source electrode region and the drain electrode region. According to the TFT three-dimensional structure design, under the condition that the physical size of the TFT is not changed, the occupied area of the TFT is reduced, and therefore the overall size of the TFT is reduced.

Description

Array substrate and preparation method thereof

technical field

The present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof.

Background technique

With the development of display technology, the requirements for the display effect of display devices are getting higher and higher. In order to achieve the ultimate display effect, the array substrate needs to have characteristics such as high pixel density, high aperture ratio, and narrow frame.

In order to achieve the above technical effects, it is necessary to reduce the occupied space of a thin film transistor (Thin Film Transistor, TFT) and reduce the display size of the TFT device. However, direct scaling down of TFT device size can degrade TFT device performance.

SUMMARY OF THE INVENTION

In view of this, the present application provides an array substrate and a preparation method thereof. Through the TFT three-dimensional structure design, the footprint of the TFT is reduced while the physical size of the TFT is kept unchanged, thereby reducing the overall size of the TFT.

The present application provides an array substrate, including:

base;

a buffer layer, located on one side of the substrate; the buffer layer includes a first surface, a first inclined surface and a second inclined surface, the first inclined surface and the second inclined surface are respectively connected to the first surface The two ends are connected, the first inclined surface and the second inclined surface are respectively inclined with respect to the first surface; and

an active layer located on the buffer layer; the active layer includes a source region, a drain region and a channel region between the source region and the drain region; the channel region, the source region and the drain region are respectively located on the first surface, the first inclined surface and the second inclined surface;

a gate, located on one side of the active layer and opposite to the channel region;

The source electrode and the drain electrode are located on one side of the active layer and are respectively electrically connected to the source electrode region and the drain electrode region.

In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on the same side of the first surface, a groove is formed on the buffer layer, and the first surface is The bottom surface of the groove, the first inclined surface and the second inclined surface are respectively two side walls of the groove.

In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on the same side of the first surface, a boss is formed on the buffer layer, and the first surface is The top surface of the boss, the first inclined surface and the second inclined surface are respectively two inclined surfaces of the boss.

In an optional embodiment of the present application, the first inclined surface and the second inclined surface are located on opposite sides of the first surface.

In an optional embodiment of the present application, a slope angle between the first inclined surface and the first surface is α ₁ , and a slope angle between the second inclined surface and the first surface is α ₂ , the difference between the active layer area and the projected area of the active layer on the substrate is L ₁ *W ₁ *(1-cosα ₁ )

+L ₂ *W ₂ *(1-cosα ₂ ), where L ₁ is the slope length of the first inclined surface, L ₂ is the slope length of the second inclined surface, W ₁ is the width of the first inclined surface, and W ₂ is the The width of the second inclined surface.

In an optional embodiment of the present application, the gradient angle α ₁ is equal to the gradient angle α ₂ .

In an optional embodiment of the present application, the gradient angle α ₁ and the gradient angle α ₂ are not equal.

In an optional embodiment of the present application, the source region includes a first heavily doped region and a first lightly doped region located between the first heavily doped region and the channel region, the The drain region includes a second heavily doped region and a second lightly doped region located between the second heavily doped region and the channel region; the source electrode is electrically connected to the first heavily doped region connected, the drain is electrically connected to the second heavily doped region.

In an optional embodiment of the present application, the array substrate further includes:

a light shielding layer, the light shielding layer is located between the substrate and the buffer layer, the projection of the light shielding layer on the substrate and the first lightly doped region, the channel region and the second light shielding layer The projections of the lightly doped regions on the substrate are coincident;

a gate insulating layer, the gate insulating layer is located between the active layer and the gate;

a dielectric layer located between the gate electrode and the source electrode and the drain electrode; the dielectric layer has a first region parallel to the first inclined surface, and a second region parallel to the second inclined surface region, a third region parallel to the first surface, the source on the first region, the drain on the second region

The present application provides a method for preparing an array substrate, comprising the following steps:

provide a base;

A buffer layer is formed on the substrate, and a pattern is formed on the buffer layer, the pattern has a first surface, a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are respectively connected with both ends of the first surface, the first inclined surface and the second inclined surface are respectively inclined relative to the first surface;

An active layer is formed on the buffer layer, the active layer includes a source region, a drain region and a channel region located between the source region and the drain region, the channel region, the source region and the drain region are respectively located on the first surface, the first inclined surface and the second inclined surface;

forming a gate insulating layer on the active layer;

forming a gate on the gate insulating layer, the gate is opposite to the channel region;

forming a dielectric layer on the gate;

forming a first via hole and a second via hole on the dielectric layer and the gate insulating layer, the first via hole and the second via hole are respectively located on two sides of the gate;

A source electrode and a drain electrode are formed on the dielectric layer, the source electrode is electrically connected to the source electrode region through the first via hole, and the drain electrode is electrically connected to the drain electrode region through the second via hole area electrical connection.

The present application provides an array substrate and a method for preparing the same. By patterning the buffer layer of the array substrate, a sloped surface with a certain slope is formed on the buffer layer, and at least part of the active layer is located on the sloped surface. , which can reduce the footprint of the active layer (that is, the projected area of the active layer on the substrate) while keeping the physical length of the active layer unchanged, so that the overall size of the TFT is reduced to facilitate the production of high pixel density. , Array substrate with high aperture ratio and narrow frame.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic structural diagram of an array substrate in the prior art.

FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application.

FIG. 3 is a schematic structural diagram of an array substrate according to another embodiment of the present application.

FIG. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present application.

FIG. 5 is a schematic flowchart of a method for fabricating an array substrate provided by the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, Rather than indicating or implying that the referred device or element must have a particular orientation, be constructed and operate in a particular orientation, it should not be construed as a limitation on the application. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as "first", "second" may expressly or implicitly include one or more of said features. In the description of this application, "plurality" means two or more, unless expressly and specifically defined otherwise.

The application may repeat reference numerals and/or reference letters in different implementations for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various implementations and/or arrangements discussed.

The array substrate and its preparation method provided by the present application will be described in detail below with reference to specific embodiments and accompanying drawings.

In order to achieve the ultimate display effect, the array substrate needs to have characteristics such as high pixel density, high aperture ratio, and narrow frame. In the prior art, the display size of the TFT device is usually reduced by reducing the space occupied by the TFT. However, direct scaling down of TFT device size can degrade TFT device performance.

As shown in FIG. 1 , it is a schematic diagram of the structure of an array substrate commonly used in the prior art. The entire active layer 400 of the array substrate 10 is on the same plane and occupies a large area, making the corresponding TFT device larger in size , which affects the display effect of the panel.

Please refer to FIG. 2 , FIG. 3 and FIG. 4 , which are schematic diagrams of the structure of an array substrate provided by the present application. By patterning the buffer layer 300 in the present application, an inclined surface with a certain slope is formed on the buffer layer 300 , and at least Part of the active layer 400 is located on the sloped surface, that is, the footprint of the active layer 400 (that is, the projected area of the active layer 400 on the substrate 100 can be reduced) under the condition that the physical length of the active layer 400 remains unchanged. ), so that the overall size of the TFT is reduced, so as to facilitate the fabrication of an array substrate with high pixel density, high aperture ratio and narrow frame.

Please refer to FIG. 2 , which is a specific embodiment of an array substrate provided by the present application.

The array substrate 10 includes a base 100 , a light shielding layer 200 , a buffer layer 300 , an active layer 400 , a gate insulating layer 500 , a gate 600 , a dielectric layer 700 , a flat layer 800 , and a source electrode 810 and a drain electrode 820 .

The substrate 100 may be, but not limited to, a glass substrate, a resin substrate, and the like.

The light shielding layer 200 is located on one side of the substrate 100 for shielding part of the incident light. The material of the light shielding layer 200 may be at least one of molybdenum (Mo), aluminum (Al), or molybdenum aluminum alloy.

The buffer layer 300 is located on the side of the light shielding layer 200 away from the substrate 100 and covers the light shielding layer 200 . The material of the buffer layer 300 may be at least one of SiO _x and SiN _x . The buffer layer 300 plays the role of buffering and isolating alkali metal ions in the glass substrate.

Specifically, a groove-shaped pattern is formed on the side of the buffer layer 300 away from the substrate 100 , and the groove has a first surface 301 (ie, the bottom surface of the groove), a first inclined surface 302 and a second The inclined surface 303 (ie, the two side walls of the groove), the first inclined surface 302 and the second inclined surface 303 are respectively connected with both ends of the first surface 301 , and the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301 , and the first surface 301 is parallel to the substrate 100 .

Specifically, as shown in FIG. 2 , the angle range of the slope angle (taper angle) α ₁ between the first inclined surface 302 and the first surface 301 is: 0°<α ₁ <90°, preferably 45° ≤α ₁ ≤60°, in order to reduce the difficulty of the process and balance the process risk; the slope angle (taper angle) α ₂ between the second inclined surface 303 and the first surface 301 is in the range of: 0°<α ₂ <90°, preferably 45°≤α ₁ ≤60°, in order to reduce the difficulty of the process and balance the risk of the process. Wherein, the taper angle α ₁ and the taper angle α ₂ may be equal or unequal, and may be set according to actual process requirements.

The reason why the buffer layer 300 is selected to form the inclined surface pattern is that the buffer layer 300 is a film layer independent of the TFT structure, and only plays the role of buffering and isolating alkali metal ions in the glass substrate. The change of the buffer layer 300 has no effect on the electrical properties of the TFT. Playing a decisive role, in the design process, the projected area of the TFT can be adjusted by adjusting the thickness of the buffer layer 300 and the taper angle of the inclined surface without affecting the electrical function of the TFT.

The active layer 400 is located on the side of the buffer layer 300 away from the substrate 100 , and the active layer 400 includes a source region 410 , a drain region 420 and located on the source region 410 and the drain The channel region 430 between the regions 420; the channel region 430, the source region 410 and the drain region 420 are located on the first surface 301, the first inclined surface 302 and the first surface respectively on the two inclined surfaces 303 . The material of the active layer 400 may be, but not limited to, amorphous silicon a-Si.

Specifically, both the source region 410 and the drain region 420 are ion-doped through a doping process, and the doping ions may be but not limited to phosphorus ions. The ion-doping of the active layer is to change the its electrical conductivity.

Specifically, the source region 410 includes a first heavily doped region 411 and a first lightly doped region 412 located between the first heavily doped region 411 and the channel region 430 , and the drain The region 420 includes a second heavily doped region 421 and a second lightly doped region 422 located between the second heavily doped region 421 and the channel region 430 . The first heavily doped region 411 and the second heavily doped region 421 are N-type doped with high concentration, which can make the TFT easy to make ohmic contact; the first lightly doped region 412 and the second lightly doped region 412 The region 422 is used to reduce the electric field strength of the source-drain junction region and improve the stability of the device.

The difference between the area of the active layer 400 and the projected area of the active layer 400 on the substrate 100 is L ₁ *W ₁ *(1-cosα ₁ )+L ₂ *W ₂ *(1-cosα ₂ ), wherein L ₁ is the slope length of the first inclined surface, L ₂ is the slope length of the second inclined surface, W ₁ is the width of the first inclined surface, and W ₂ is the width of the second inclined surface. During the design process, the projected area of the active layer 400 on the substrate 100 can be controlled by adjusting the taper angle α ₁ and the taper angle α ₂ , thereby reducing the footprint of the active layer.

The projection of the light shielding layer 200 on the substrate 100 coincides with the projections of the first lightly doped region 412 , the channel region 430 and the second lightly doped region 422 on the substrate 100 , In order to make the light shielding layer 200 block the backlight (light source under the TFT) from being incident into the TFT to generate a photo-generated leakage current.

The gate insulating layer 500 is located on a side of the active layer 400 away from the buffer layer 300 and covers the active layer 400 to insulate the gate 600 from the active layer 400 . The material of the gate insulating layer 500 may be, but not limited to, SiO _x .

The gate 600 is located on the side of the gate insulating layer 500 away from the active layer 400 . The projection of the gate 600 on the substrate 100 and the channel region 430 on the substrate 100 , so that the gate 600 acts as a shield to facilitate ion doping of the source region 410 on the first inclined surface 302 and the drain region 420 on the second inclined surface 303 miscellaneous.

The dielectric layer 700 is located on a side of the gate electrode 600 away from the gate insulating layer 500 and covers the gate electrode 600 to insulate the gate electrode 600 from the source and drain electrodes. The material of the dielectric layer 700 may be at least one of SiO _x and SiN _x . The dielectric layer 700 includes a first via hole 701 and a second via hole 702 , and the first via hole 701 and the second via hole 702 are located on two sides of the gate 600 respectively. The first via hole 701 penetrates through the gate insulating layer 500 to expose one side of the first heavily doped region 411 ; the second via hole 702 penetrates through the gate insulating layer 500 to expose the first heavily doped region 411 . One side of the doubly doped region 421 .

The source electrode 810 is located on the side of the dielectric layer 700 away from the gate electrode 600 , and the source electrode 810 is electrically connected to the side of the first heavily doped region 411 through the first via hole 701 . The material of the source electrode 810 may be, but not limited to, Ti/Al/Ti/, Mo/Al/Mo metal stack, and the like.

The drain 820 is located on the side of the dielectric layer 700 away from the gate 600 , and the drain 820 is electrically connected to the side of the second heavily doped region 421 through the second via 702 . The material of the drain electrode 820 may be, but not limited to, Ti/Al/Ti/, Mo/Al/Mo metal stack, and the like.

Specifically, the dielectric layer 700 has a first region 710 parallel to the first inclined surface 302 , a second region 720 parallel to the second inclined surface 303 , and a third region parallel to the first surface 301 730 , the source electrode 810 is located on the first region 710 , and the drain electrode 820 is located on the second region 720 . The source electrode 810 and the drain electrode 820 are located on the sloped first region 710 and the second region 720, which can reduce the thickness of the TFT.

The planarization layer 800 is located on the side of the dielectric layer 700 away from the gate electrode 600 and covers the source electrode 810 and the drain electrode 820 , so as to planarize the pattern surface on the array substrate 10 . The material of the flat layer 800 may be, but not limited to, an organic photoresist material.

In other embodiments, the array substrate 10 further includes a BITO (Back side Indium Tin Oxides) layer 900 , a passivation layer 1000 and a TITO (Top-Indium Tin Oxides) layer 1100 .

Specifically, the flat layer 800 includes a first through hole, and the first through hole exposes one side of the drain electrode 820 .

The BITO layer 900 is located on the side of the flattened layer 800 away from the dielectric layer 700 , and the BITO layer 900 is made of indium tin oxide (Indium Tin Oxides, ITO). The BITO layer includes second through holes corresponding to the first through holes.

The passivation layer 1000 is located on the side of the BITO layer 900 away from the flat layer 800 , and the material of the passivation layer 1000 may be at least one of SiO _x and SiN _x . The passivation layer 1000 includes third through holes corresponding to the second through holes.

The TITO layer 1100 is located on the side of the passivation layer 1000 away from the BITO layer 900 , and the TITO layer 1100 passes through the third through hole and the second through hole and the first through hole and the drain hole. The electrodes 820 are electrically connected to form pixel electrodes.

Please refer to FIG. 3 , which is another specific embodiment of an array substrate provided by the present application.

The structure of the array substrate 10 provided by another specific embodiment of the present application is basically the same as the structure of the array substrate 10 described in a specific embodiment of the above-mentioned one of the array substrates, and the difference only lies in:

A boss-shaped pattern is formed on the side of the buffer layer 300 away from the substrate 100 , and the boss has a first surface 301 (ie, the top surface of the boss), a first inclined surface 302 and a second inclined surface 303 (that is, the two inclined surfaces of the boss), the first inclined surface 302 and the second inclined surface 303 are respectively connected with both ends of the first surface 301 , the first inclined surface 302 and the The second inclined surfaces 303 are respectively inclined with respect to the first surfaces 301 , and the first surfaces 301 are parallel to the substrate 100 .

Please refer to FIG. 4 , which is another specific embodiment of an array substrate provided by the present application.

The structure of the array substrate 10 provided by another specific embodiment of the present application is basically the same as the structure of the array substrate 10 described in a specific embodiment of the above-mentioned one of the array substrates, and the difference only lies in:

A pattern consisting of a first surface 301 , a first inclined surface 302 and a second inclined surface 303 is formed on the side of the buffer layer 300 away from the substrate 100 , the first inclined surface 302 and the second inclined surface 303 are respectively connected with both ends of the first surface 301, the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301, the first surface 301 and the The substrates 100 are parallel, and the first inclined surface 302 and the second inclined surface 303 are located on opposite sides of the first surface 301 . Specifically, as shown in FIG. 4 , the first inclined surface 302 is located on the first inclined surface 302 . A surface 301 is located on a side away from the substrate 100 , and the second inclined surface 303 is located on a side of the first surface 301 close to the substrate 100 .

In the above-mentioned embodiment of the present application, by patterning the buffer layer, the first surface, the first inclined surface and the second inclined surface are formed on the buffer layer, and the first inclined surface and the second inclined surface are formed on the buffer layer. The inclined surfaces are respectively connected with both ends of the first surface, the first surface is parallel to the base, the first inclined surface and the second inclined surface are respectively inclined relative to the first surface, the first inclined surface is The taper angle α1 of an inclined plane and the taper angle α2 _of the _second inclined plane can be adjusted, and the channel region, the source region and the drain region are located on the first surface, the first On the inclined surface and the second inclined surface, by controlling the angle sizes _of α1 and _{α2 (} the angle sizes _of α1 and α2 are easily controlled by the etching process parameters), the first inclined surface and the first inclined surface are adjusted. The slope of the two inclined planes can reduce the footprint of the active layer (that is, the projected area of the active layer on the substrate) while keeping the physical length of the active layer unchanged, thereby reducing the footprint of the TFT , in order to facilitate the manufacture of array substrates with high pixel density, high aperture ratio and narrow frame, and the channel region is located on the first surface, that is, the channel region remains on the plane, which is conducive to maintaining the stability of the device .

Please refer to FIG. 5 , the present application also provides a method for preparing an array substrate, comprising the steps of:

providing a substrate 100;

A buffer layer 300 is formed on the substrate 100 , and a pattern is formed on the buffer layer 300 , and the pattern has a first surface 301 , a first inclined surface 302 and a second inclined surface 303 , the first inclined surface 302 and the The second inclined surface 303 is respectively connected with both ends of the first surface 301 , and the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301 ;

An active layer 400 is formed on the buffer layer 300 , and the active layer 400 includes a source region 410 , a drain region 420 and a channel region between the source region 410 and the drain region 420 430; the channel region 430, the source region 410 and the drain region 420 are respectively located on the first surface 301, the first inclined surface 302 and the second inclined surface 303;

forming a gate insulating layer 500 on the active layer 400;

forming a gate electrode 600 on the gate insulating layer 500, the gate electrode 600 is positioned opposite to the channel region 430;

forming a dielectric layer 700 on the gate 600;

A first via hole 701 and a second via hole 702 are formed on the dielectric layer 700 and the gate insulating layer 500 , and the first via hole 701 and the second via hole 702 are respectively located at the gate Both sides of 600;

A source electrode 810 and a drain electrode 820 are formed on the dielectric layer 700 , the source electrode 810 is electrically connected to the source region 410 through a first via hole 701 , and the drain electrode 820 is connected to the source region 410 through a second via hole 702 . The drain region 420 is electrically connected.

In some embodiments, the manufacturing method of the array substrate further includes the following steps:

A flat layer 800 is formed on the dielectric layer 700 and covers the source electrode 810 and the drain electrode 820 .

A BITO layer 900 is formed on the flat layer 800 .

A passivation layer 1000 is formed on the BITO layer 900 .

A TITO layer 1100 is formed on the passivation layer 1000 .

The present application provides a specific preparation method of the array substrate 10, including the steps:

A substrate 100 is provided, and the substrate 100 may be, but is not limited to, a glass substrate.

A light shielding layer 200 is first formed on the substrate 100 by a physical vapor deposition (Physical Vapour Deposition, PVD) process. Then, the light shielding layer 200 is patterned through a patterning process (eg, including exposure, development, and etching) to obtain a light shielding layer pattern. The material of the light shielding layer 200 may be molybdenum (Mo), aluminum (Al), or molybdenum-aluminum alloy.

The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (Chemical Vapour Deposition, CVD) process. The material of the buffer layer 300 may be at least one of SiO _x and SiN _x . Then, the buffer layer 300 is patterned through a patterning process (eg, including exposure, development, and etching), so that a groove-shaped pattern is formed on the buffer layer 300, and the groove has a first surface 301 (ie The bottom surface of the groove), the first inclined surface 302 and the second inclined surface 303 (ie, the two side walls of the groove), the first inclined surface 302 and the second inclined surface 303 are respectively connected to the Two ends of the first surface 301 are connected, the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301 , and the first surface 301 is parallel to the substrate 100 . The angle range of the taper angle α ₁ between the first inclined surface 302 and the first surface 301 is: 0°<α ₁ <90°, preferably 45°≤α ₁ ≤60°; the second inclined surface The angle range of the taper angle α ₂ between 303 and the first surface 301 is: 0°<α ₂ <90°, preferably 45°≤α ₁ ≤60°. The taper angle α ₁ and the taper angle α ₂ may be equal or unequal, and are set according to actual process requirements.

The active layer 400 is deposited on the buffer layer 300 by a chemical vapor deposition process. The material of the active layer 400 may be, but not limited to, amorphous silicon a-Si. By an excimer laser annealing (ELA) process, a -Si is converted into polysilicon, forming a polysilicon active layer. The active layer 400 is patterned through a patterning process (eg, including exposure, development, and etching) to obtain an active layer pattern. Wherein, the active layer 400 includes a source region 410, a drain region 420, and a channel region 430 located between the source region 410 and the drain region 420; the channel region 430, the The source region 410 and the drain region 420 are respectively located on the first surface 301 , the first inclined surface 302 and the second inclined surface 303 .

Phosphorus ions are heavily doped on the source region 410 and the drain region 420 through exposure and development processes, a first heavily doped region 411 is formed on the first inclined surface 302, and a first heavily doped region 411 is formed on the second inclined surface 302. A second heavily doped region 421 is formed on the inclined surface 303 .

A gate insulating layer 500 is deposited on the buffer layer 300 and the active layer 400 through a chemical vapor deposition process, and the gate insulating layer 500 covers the active layer 400 . The material of the gate insulating layer may be, but not limited to, SiO _x .

A gate electrode 600 is deposited on the gate insulating layer 500 by a physical vapor deposition process, and the material of the gate electrode 600 may be, but not limited to, metals such as molybdenum (Mo). Then, the gate electrode 600 is patterned through a patterning process (eg, including exposure, development, and etching) to produce a gate electrode pattern, and the gate electrode 600 is positioned opposite to the channel region 430 . Then, using the gate 600 as a mask, the active layer 400 is lightly doped with phosphorus ions to form a first lightly doped region 412 and a second lightly doped region 422 . The first lightly doped region 412 is located between the first heavily doped region 411 and the channel region 430 ; the second lightly doped region 422 is located between the second heavily doped region 421 and the channel region 430 . between the channel regions 430 .

A dielectric layer 700 is deposited on the gate insulating layer 500 and the gate electrode 600 by a chemical vapor deposition process, the dielectric layer 700 covers the gate electrode 600, and the material of the dielectric layer can be SiO _x and at least one of SiN _x . Then, the channel region 430 is activated by hydrogenation through a rapid thermal annealing process, and then the dielectric layer 700 is patterned through a patterning process (eg, including exposure, development, and etching). A first via hole 701 and a second via hole 702 are formed thereon, and the first via hole 701 and the second via hole 702 are respectively located on two sides of the gate 600 . Wherein, the first via hole 701 penetrates through the gate insulating layer 500 to expose one side of the first heavily doped region 411 ; the second via hole 702 penetrates through the gate insulating layer 500 to expose all the One side of the second heavily doped region 421 is described.

A source and drain metal layer is deposited on the dielectric layer 700 by a physical vapor deposition process, and then a source electrode 810 and a drain electrode are fabricated on the dielectric layer 700 by a patterning process (eg, including exposure, development, and etching). 820 pattern, the material of the source electrode 810 and the drain electrode 820 may be Ti/Al/Ti/, Mo/Al/Mo metal stack, and the like. The source electrode 810 is electrically connected to one side of the first heavily doped region 411 through the first via hole 701 ; the drain electrode 820 is electrically connected to the second heavily doped region through the second via hole 702 One side of the region 421 is electrically connected.

A layer of organic photoresist material is coated on the dielectric layer 700 as a planarization layer 800 , and the planarization layer 800 covers the source electrode 810 and the drain electrode 820 . Then, a first through hole is formed on the flat layer 800 through a patterning process (eg, including exposure, development, and etching), and the first through hole exposes one side of the drain electrode 820 .

A BITO layer 900 is deposited on the flat layer 800 by a physical vapor deposition process, and the material of the BITO layer 900 is indium tin oxide, and then a patterning process (eg, including exposure, development, and etching) is performed on the BITO layer 900 A BITO pattern is formed, and a second through hole corresponding to the first through hole is fabricated on the BITO layer 900 .

A passivation layer 1000 is deposited on the flat layer 800 and the BITO layer 900 by a chemical vapor deposition process, the passivation layer 1000 covers the BITO layer 900, and the material of the passivation layer 1000 may be SiO _x and at least one of SiN _x ). Then, third through holes corresponding to the second through holes are formed in the passivation layer 1000 through a patterning process (eg, including exposure, development, and etching).

A TITO layer 1100 is deposited on the passivation layer 1000 by a physical vapor deposition process, and the material of the TITO layer 1100 is indium tin oxide. Then, a TITO pattern is fabricated on the TITO layer 1100 through a patterning process (eg, including exposure, development, and etching). The TITO layer 1100 is electrically connected to the drain electrode 820 through the third through hole, the second through hole and the first through hole to form a pixel electrode.

The present application provides another specific preparation method of the array substrate 10:

The steps of another specific preparation method provided by the present application are basically the same as those of the above-mentioned one specific preparation method of the array substrate 10, and the difference is only that the buffer layer is formed with different patterns. The specific steps are:

The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (Chemical Vapour Deposition, CVD) process. The material of the buffer layer 300 may be at least one of SiO _x and SiN _x . Then, the buffer layer 300 is patterned through a patterning process (eg, including exposure, development, and etching), so that a boss-shaped pattern is formed on the buffer layer 300, and the boss has a first surface 301 (that is, the (the top surface of the boss), the first inclined surface 302 and the second inclined surface 303 (that is, the two inclined surfaces of the boss), the first inclined surface 302 and the second inclined surface 303 are respectively connected with the first inclined surface 302 and the second inclined surface 303. Two ends of a surface 301 are connected, the first inclined surface 302 and the second inclined surface 303 are respectively inclined relative to the first surface 301 , and the first surface 301 is parallel to the substrate 100 .

The present application provides another specific preparation method of the array substrate 10:

The steps of another specific preparation method provided by the present application are basically the same as those of the above-mentioned one specific preparation method of the array substrate 10, and the difference is only in that the buffer layer is formed with different patterns. The specific steps are:

The buffer layer 300 is deposited on the surface of the light shielding layer 200 by a chemical vapor deposition (Chemical Vapour Deposition, CVD) process. The material of the buffer layer 300 may be at least one of SiO _x and SiN _x . Then, the buffer layer 300 is patterned through a patterning process (eg, including exposure, development, and etching), so that the buffer layer 300 is formed with a first surface 301 , a first inclined surface 302 and a second inclined surface 303 The pattern formed, the first inclined surface 302 and the second inclined surface 303 are respectively connected with both ends of the first surface 301, and the first inclined surface 302 and the second inclined surface 303 are respectively opposite The first surface 301 is inclined, the first surface 301 is parallel to the substrate 100 , the first inclined surface 302 and the second inclined surface 303 are located on opposite sides of the first surface 301 , specifically , the first inclined surface 302 is located on the side of the first surface 301 away from the substrate 100 , and the second inclined surface 303 is located on the side of the first surface 301 close to the substrate 100 .

In other embodiments, the described structures and steps are not limited to the above-mentioned structures and steps, and can be adjusted according to actual conditions.

To sum up, although the present application has disclosed the above-mentioned preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art, without departing from the spirit and scope of this application, can Therefore, the scope of protection of the present application is subject to the scope defined by the claims.

Claims (10)

1. An array substrate, characterized in that, comprising: base; a buffer layer, located on one side of the substrate; the buffer layer includes a first surface, a first inclined surface and a second inclined surface, the first inclined surface and the second inclined surface are respectively connected to the first surface The two ends are connected, the first inclined surface and the second inclined surface are respectively inclined with respect to the first surface; and an active layer located on the buffer layer; the active layer includes a source region, a drain region and a channel region between the source region and the drain region; the channel region, the source region and the drain region are respectively located on the first surface, the first inclined surface and the second inclined surface; a gate, located on one side of the active layer and opposite to the channel region; The source electrode and the drain electrode are located on one side of the active layer and are respectively electrically connected to the source electrode region and the drain electrode region. 2 . The array substrate according to claim 1 , wherein the first inclined surface and the second inclined surface are located on the same side of the first surface, and grooves are formed on the buffer layer, so that the The first surface is the bottom surface of the groove, and the first inclined surface and the second inclined surface are two side walls of the groove, respectively. 3 . The array substrate of claim 1 , wherein the first inclined surface and the second inclined surface are located on the same side of the first surface, and a boss is formed on the buffer layer, so that the The first surface is the top surface of the boss, and the first inclined surface and the second inclined surface are respectively two inclined surfaces of the boss. 4 . The array substrate of claim 1 , wherein the first inclined surface and the second inclined surface are located on opposite sides of the first surface. 5 . 5 . The array substrate of claim 1 , wherein a slope angle between the first inclined surface and the first surface is α ₁ , and the angle between the second inclined surface and the first surface is α 1 . The slope angle between them is α ₂ , and the difference between the area of the active layer and the projected area of the active layer on the substrate is L ₁ *W ₁ *(1-cosα ₁ )+L ₂ *W ₂ * (1-cosα ₂ ), wherein L ₁ is the slope length of the first inclined surface, L ₂ is the slope length of the second inclined surface, W ₁ is the width of the first inclined surface, and W ₂ is the width of the second inclined surface. 6 . The array substrate of claim 5 , wherein the slope angle α ₁ is equal to the slope angle α ₂ . 7 . 7 . The array substrate of claim 5 , wherein the slope angle α ₁ and the slope angle α ₂ are not equal. 8 . 8. The array substrate of claim 1, wherein the source region comprises a first heavily doped region and a first lightly doped region between the first heavily doped region and the channel region a doped region, the drain region includes a second heavily doped region and a second lightly doped region between the second heavily doped region and the channel region; the source and the first A heavily doped region is electrically connected, and the drain is electrically connected to the second heavily doped region. 9. The array substrate of claim 8, wherein the array substrate further comprises: a light shielding layer, the light shielding layer is located between the substrate and the buffer layer, the projection of the light shielding layer on the substrate and the first lightly doped region, the channel region and the second light shielding layer The projections of the lightly doped regions on the substrate are coincident; a gate insulating layer, the gate insulating layer is located between the active layer and the gate; a dielectric layer located between the gate electrode and the source electrode and the drain electrode; the dielectric layer has a first region parallel to the first inclined surface, and a second region parallel to the second inclined surface region, a third region parallel to the first surface, the source electrode is located on the first region, and the drain electrode is located on the second region. 10. A method for preparing an array substrate, comprising the following steps: provide a base; A buffer layer is formed on the substrate, and a pattern is formed on the buffer layer, the pattern has a first surface, a first inclined surface and a second inclined surface, and the first inclined surface and the second inclined surface are respectively connected with both ends of the first surface, the first inclined surface and the second inclined surface are respectively inclined relative to the first surface; An active layer is formed on the buffer layer, the active layer includes a source region, a drain region and a channel region located between the source region and the drain region, the channel region, the source region and the drain region are respectively located on the first surface, the first inclined surface and the second inclined surface; forming a gate insulating layer on the active layer; forming a gate on the gate insulating layer, the gate is opposite to the channel region; forming a dielectric layer on the gate; forming a first via hole and a second via hole on the dielectric layer and the gate insulating layer, the first via hole and the second via hole are respectively located on two sides of the gate; A source electrode and a drain electrode are formed on the dielectric layer, the source electrode is electrically connected to the source electrode region through the first via hole, and the drain electrode is electrically connected to the drain electrode region through the second via hole area electrical connection.

Images