CN115000076A

CN115000076A - Methods to improve the reliability of SONOS memory

Info

Publication number: CN115000076A
Application number: CN202210702671.7A
Authority: CN
Inventors: 陈冬; 刘政红; 齐瑞生; 黄冠群
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2022-06-21
Filing date: 2022-06-21
Publication date: 2022-09-02

Abstract

The invention provides a method for improving the reliability of a SONOS memory, and provides a substrate on which a control gate and a selection gate formed on both sides of the control gate are formed; and a photoresist layer covering the control gate and the selection gate is formed on the substrate. Then, the photoresist layer is opened by photolithography, so that the substrate beyond the floating gate to the control gate area is exposed; ion implantation is performed on the exposed substrate to change the threshold voltage of the selection gate. In the present invention, ion implantation is performed after the selection gate and the control gate structure are formed, so as to avoid ion diffusion between the selection gate and the control gate, reduce the induced drain leakage current leakage of the selection gate, and improve the reliability of the SONOS storage device.

Description

Method for improving reliability of SONOS memory

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for improving the reliability of an SONOS memory.

Background

Flash memory (Flash memory) is a new type of non-volatile semiconductor memory. A typical SONOS memory cell structure is composed of a silicon substrate (S) -a tunnel oxide (O) -a charge storage layer silicon nitride (N) -a blocking oxide (O) -a polysilicon gate (S). Data writing and storing are performed by electron tunneling (FN tunneling), and data erasing is performed by hole injection.

SONOS is a memory cell based on the storage of charge in discrete traps in an insulating dielectric (Si3N4) with a dielectric layer of silicon dioxide between the insulating dielectric layer and the substrate and gate electrode, respectively, as opposed to electrons stored in a floating gate as in floating gate technology. With the continuous reduction of design dimensions, the reliability problem caused by GIDL (gate induced drain leakage) leakage is also increasing. Under the condition of the existing selective gate threshold voltage ion implantation process, because the ion implantation is carried out before the deposition of a gate, the electric leakage from the selective gate to a control gate is easily caused, and the reliability problem of a device is caused.

To solve the above problems, a method for improving reliability of the SONOS memory is needed.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for improving reliability of a SONOS memory device, which is used to solve the problem of device reliability caused by leakage from a select gate to a control gate due to implantation before gate deposition under the condition of a select gate threshold voltage ion implantation process in the prior art.

To achieve the above and other related objects, the present invention provides a method for improving reliability of a SONOS memory, including:

providing a substrate, wherein a control gate and selection gates formed on two sides of the control gate are formed on the substrate;

forming a photoresist layer covering the control gate and the select gate on the substrate, and opening the photoresist layer through photoetching to expose the substrate from the floating gate to the region outside the control gate region;

and step three, carrying out ion implantation on the exposed substrate for changing the threshold voltage of the selection gate.

Preferably, the substrate in the first step is a silicon substrate.

Preferably, in the first step, first select gates, first control gates, second control gates, and second select gates are sequentially formed on the substrate at intervals.

Preferably, the select gate and the control gate in the first step are formed by a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a gate which are stacked in sequence from bottom to top.

Preferably, in the first step, the tunneling oxide layer and the blocking oxide layer are both made of silicon dioxide.

Preferably, the material of the charge storage layer in the first step is silicon nitride.

Preferably, the material of the gate in the first step is polysilicon.

As described above, the method for improving reliability of the SONOS memory according to the present invention has the following beneficial effects:

according to the invention, after the selection gate and the control gate structure are formed, ion implantation is carried out, so that ion diffusion between the selection gate and the control gate is avoided, leakage current and leakage current of the induced drain electrode of the selection gate are reduced, and the reliability of the SONOS memory device is improved.

Drawings

FIG. 1 is a schematic process flow diagram of the present invention;

FIG. 2 is a schematic view of an ion implantation process according to the present invention;

FIG. 3 is a schematic diagram of the present invention for removing photoresist.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Referring to fig. 1, the present invention provides a method for improving reliability of a SONOS memory, including:

providing a substrate, wherein a Control Gate (CG) and Selection Gates (SG) formed at two sides of the control gate are formed on the substrate;

in the embodiment of the invention, the substrate in the first step is a silicon substrate, and after the control gate and the select gate structure are formed, a P-well or an N-well can be formed on the silicon substrate through ion implantation.

In the embodiment of the invention, the first selection gate, the first control gate, the second control gate and the second selection gate are sequentially formed on the substrate in the first step.

In the embodiment of the invention, the select gate and the control gate in the first step are formed by sequentially stacking a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a gate from bottom to top, which is a typical SONOS memory cell structure.

In the embodiment of the invention, in the first step, the tunneling oxide layer and the blocking oxide layer are made of silicon dioxide.

In an embodiment of the present invention, in the first step, the material of the charge storage layer is silicon nitride.

In the embodiment of the present invention, the material of the gate in the first step is polysilicon.

Step two, referring to fig. 2, a photoresist layer covering the control gate and the select gate is formed on the substrate, and then the photoresist layer is opened through exposure, development, film erection, baking and other photoetching steps, so that the substrate outside the region from the floating gate to the control gate is exposed, and the residual photoresist remains between the select gate and the control gate, thereby avoiding the influence on the channel between the select gate and the control gate during ion implantation, and improving the reliability of the device;

and step three, carrying out ion implantation on the exposed substrate for changing the threshold voltage of the selection gate, and when the device is converted from depletion to inversion, experiencing a state that the concentration of Si surface electrons is equal to that of holes. The device is in a critical conducting state at this time, and the gate voltage of the device is defined as the threshold voltage.

In the embodiment of the present invention, after the ion implantation is completed, the photoresist is removed to form the structure shown in fig. 3, and then the subsequent process flow may be performed.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

In summary, in the invention, after the selection gate and the control gate structure are formed, ion implantation is performed, so that ion diffusion between the selection gate and the control gate is avoided, leakage current and leakage current of the induced drain of the selection gate are reduced, and the reliability of the SONOS memory device is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for improving reliability of SONOS memory is characterized by at least comprising the following steps:

2. The method of claim 1, wherein the SONOS memory is configured to be operated in a SONOS memory cell, and wherein: the substrate in the first step is a silicon substrate.

3. The method of claim 1, wherein the SONOS memory is configured to: and sequentially forming a first selection gate, a first control gate, a second control gate and a second selection gate which are distributed at intervals on the substrate in the first step.

4. The method of claim 1, wherein the SONOS memory is configured to be operated in a SONOS memory cell, and wherein: and in the first step, the selection gate and the control gate are sequentially stacked from bottom to top, and comprise a tunneling oxide layer, a charge storage layer, a blocking oxide layer and a grid.

5. The method of claim 4, wherein the SONOS memory is configured to be operated in a SONOS memory mode, and wherein: in the first step, the tunneling oxide layer and the blocking oxide layer are made of silicon dioxide.

6. The method of claim 4, wherein the SONOS memory is configured to be operated in a SONOS memory mode, and wherein: in the first step, the charge storage layer is made of silicon nitride.

7. The method of claim 4, wherein the SONOS memory is configured to be operated in a SONOS memory mode, and wherein: in the first step, the grid is made of polysilicon.