[go: up one dir, main page]

CN114976582A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

Info

Publication number
CN114976582A
CN114976582A CN202110219310.2A CN202110219310A CN114976582A CN 114976582 A CN114976582 A CN 114976582A CN 202110219310 A CN202110219310 A CN 202110219310A CN 114976582 A CN114976582 A CN 114976582A
Authority
CN
China
Prior art keywords
antenna
layer
electronic package
carrier structure
substrate body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110219310.2A
Other languages
English (en)
Other versions
CN114976582B (zh
Inventor
柯仲禹
赖佳助
陈亮斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN114976582A publication Critical patent/CN114976582A/zh
Application granted granted Critical
Publication of CN114976582B publication Critical patent/CN114976582B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • H01Q1/246Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM specially adapted for base stations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/40Radiating elements coated with or embedded in protective material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00Antenna arrays or systems
    • H01Q21/28Combinations of substantially independent non-interacting antenna units or systems
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04Resonant antennas
    • H01Q9/0407Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0414Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Details Of Aerials (AREA)
  • Waveguide Aerials (AREA)

Abstract

本发明涉及一种电子封装件及其制法,包括:具有多个天线馈入线路的第一承载结构,以及设于该第一承载结构上的天线模块,且该天线模块包含有基板本体,其具有多个不同深度的凹部,以于该多个凹部中形成有天线层,使该天线层电磁耦合该天线馈入线路,以提升该天线组件的整体辐射效率。

Description

电子封装件及其制法
技术领域
本发明关于一种电子封装件,特别是关于一种具有天线结构的电子封装件及其制法。
背景技术
现今无线通讯技术已广泛应用于各式消费性电子产品(如手机、平板电脑等),以利接收或发送各种无线信号。为满足消费性电子产品的便于携带性及上网便利性(如观看多媒体内容),无线通讯模块的制造与设计朝轻、薄、短、小的需求作开发,其中,平面天线(Patch Antenna)因具有体积小、重量轻与制造容易等特性而广泛利用在电子产品的无线通讯模块中。
此外,由于目前的多媒体内容因画质的提升而造成其文件数据量变得更大,故无线传输的频宽也需变大,因而产生第五代的无线传输(5G),另5G因传输频率较高,其相关无线通讯模块的要求也较高。
有关5G的应用是未来全面商品化的趋势,其应用频率范围约在1GHz~1000GHz之间的高频频段,其商业应用模式为5G搭配4G LTE,并于户外架设一蜂巢式基站以配合设于室内的小基站,故5G行动通讯会于基站内使用大量天线以符合5G系统的大容量快速传输且低延迟。
图1为现有无线通讯模块1的立体示意图。如图1所示,该无线通讯模块1包括:一基板10、设于该基板10上的多个电子元件11、一天线结构12以及封装材13。该基板10为电路板并呈矩形体。该电子元件11设于该基板10上且电性连接该基板10。该天线结构12为平面型且具有一天线本体120与一导线121,该天线本体120经由该导线121电性连接该电子元件11。该封装材13覆盖该电子元件11与该部分导线121。
以应用于智能手机为例,5G频段可分为3.5Ghz~6Ghz、28Ghz、39Ghz、60Ghz、71Ghz~73Ghz等,且5G系统因信号品质与传输速度要求,而需更多天线配置,以提升信号的品质与传输速度。
然而,现有无线通讯模块1中,该天线结构12为平面型,且该基板10的长宽尺寸均为固定,致使线路布线空间(层数)有限,因而限制该天线结构12的功能,造成该无线通讯模块1无法提供运行5G系统所需的电性功能,难以达到5G系统的天线运行的需求。
此外,若于该基板10的表面上增加布设区域以形成多种频率的天线本体120,将使该基板10的宽度增加,导致难以缩小该无线通讯模块1的宽度,造成该无线通讯模块1无法达到微小化的需求。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷,本发明提供一种电子封装件及其制法,可以提升该天线组件的整体辐射效率。
本发明的电子封装件,包括:第一承载结构,其具有多个天线馈入线路;以及天线模块,其设于该第一承载结构上,且该天线模块包含具有相对的第一表面与第二表面的基板本体,以令该基板本体以其第一表面设于该第一承载结构上,其中,该基板本体的第一表面上具有多个不同深度的凹部,以于该多个凹部中形成有第一天线层,且基板本体的第二表面上具有对应该第一天线层配置的第二天线层,使该第一天线层电磁耦合该天线馈入线路与第二天线层。
前述的电子封装件中,该第一天线层与该天线馈入线路之间形成空气间隔。
前述的电子封装件中,该天线模块经由支撑件设于该第一承载结构上。
前述的电子封装件中,该第一承载结构具有相对两侧,以令该天线模块设于该第一承载结构的其中一侧上,且该电子封装件还包括:第二承载结构,其经由多个导电体堆叠于该第一承载结构的另一侧上;以及至少一电子元件,其设于该第一承载结构与第二承载结构之间并电性连接该导电体。
前述的电子封装件中,该第一承载结构经由该导电体电性连接该第二承载结构。
前述的电子封装件中,该天线馈入线路电性连接该导电体,以电性导通至该电子元件。
前述的电子封装件中,还包括包覆层,其形成于该第一承载结构与第二承载结构之间以包覆该电子元件。
前述的电子封装件中,还包括形成于该第二承载结构上的多个导电元件,其与该导电体分别位于该第二承载结构的不同侧。
本发明还提供一种电子封装件的制法,包括:提供一基板本体,其具有相对的第一表面与第二表面,且该第二表面上具有第二天线层;形成多个不同深度的凹部于该基板本体的第一表面上;形成第一天线层于该多个凹部中,使该第一天线层电磁耦合该第二天线层;以及将该基板本体以其第一表面设于一具有多个天线馈入线路的第一承载结构上,使该第一天线层电磁耦合该天线馈入线路。
前述的制法中,该第一天线层与该天线馈入线路之间形成空气间隔。
前述的制法中,该基板本体经由支撑件设于该第一承载结构上。
前述的制法中,该基板本体的第一表面上以蚀刻方式形成该多个凹部。
前述的制法,该第一承载结构具有相对两侧,以令该天线模块设于该第一承载结构的其中一侧上,且该制法还包括将第二承载结构经由多个导电体堆叠于该第一承载结构的另一侧上,且将至少一电子元件设于该第一承载结构与第二承载结构之间并电性连接该导电体。
前述的制法中,该第一承载结构经由该导电体电性连接该第二承载结构。
前述的制法中,该天线馈入线路电性连接该导电体,以电性导通至该电子元件。
前述的制法中,还包括于该第一承载结构与第二承载结构之间形成包覆该电子元件的包覆层。
前述的制法中,还包括于该第二承载结构上设置多个导电元件,其与该导电体分别位于该第二承载结构的不同侧。
由上可知,本发明的电子封装件及其天线组件与制法,经由该凹部的设计,以当第一天线层电磁耦合该天线馈入线路与第二天线层时,可提升该电子封装件(或该天线组件)的天线结构的整体辐射效率,故相比于现有技术,本发明可提升天线的效能增益及效率,并使天线的电场强度增强而有利于传输信号,因而可达到5G系统的天线运行的需求。
此外,本发明经由该多个不同深度的凹部的设计,可调整该第一天线层与第二天线层电磁耦合的距离而产生不同频率,使该电子封装件(或该天线组件)的天线可依需求传递不同的天线信号,故相比于现有技术,本发明的单一该电子封装件即可对应多种频率的射频产品的需求,以取代多个对应不同频率的封装模块,因而可缩减产品尺寸,以利于该电子封装件(或该天线组件)符合微小化的需求。
另外,本发明经由将该天线模块叠置于该第一承载结构上,因而无需于该第一承载结构上增加布设区域,故可于预定的第一承载结构尺寸下制作各种频率的天线,以利于该电子封装件(或该天线组件)符合微小化的需求。
附图说明
图1为现有无线通讯模块的剖面示意图。
图2A至图2F为本发明的电子封装件的制法的第一实施例的剖视示意图。
图3A至图3E为本发明的电子封装件的制法的第二实施例的剖视示意图。
图3C-1为图3C的另一实施例示意图。
图4A至图4C为本发明的电子封装件的天线模块的制法的剖视示意图。
附图标记说明
1:无线通讯模块
10:基板
11,21:电子元件
12:天线结构
120:天线本体
121:导线
13:封装材
2,3:电子封装件
2’,3’:天线组件
2a,3a:封装模块
2b:天线模块
20,30:第一承载结构
20a,30a:第一侧
20b,30b:第二侧
200:第一绝缘层
201,301:第一线路层
21a:作用面
21b:非作用面
21c:固晶层
210:电极垫
211,212:保护膜
213,313:导电凸块
22,32:第二承载结构
220:第二绝缘层
221,321:第二线路层
23,33:导电体
24:导电元件
240:凸块底下金属层
25:包覆层
26:支撑件
27,29:天线本体
27a:低频天线部
270:第一天线馈入线路
271,291:第一天线层
272,292:第二天线层
28:基板本体
28a:第一表面
28b:第二表面
280,281:凹部
29a:高频天线部
290:第二天线馈入线路
300,320:绝缘体
302:绝缘保护层
302a,900:开孔
330:核心块
331:导电材
35:底胶
9:承载板
A:空旷区
A1,A2:空气间隔
D1,D2,L1,L2:距离
H1,H2:深度
S:切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2F图为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示,于一承载板9上设有第一承载结构20,该第一承载结构20具有相对的第一侧20a与第二侧20b,且该第一承载结构20以其第二侧20b结合至该承载板9上。接着,于该第一侧20a上形成多个电性连接该第一承载结构20的导电体23,且设置至少一电子元件21于该第一承载结构20的第一侧20a上。
于本实施例中,该第一承载结构20为无核心层(coreless)的线路构造,其包括至少一第一绝缘层200与设于该第一绝缘层200上的第一线路层201,如线路重布层(redistribution layer,简称RDL),其具有第一天线馈入线路(feed line)270与第二天线馈入线路290,使该第一承载结构20可做为天线基板。例如,形成该第一线路层201的材料为铜,且形成该第一绝缘层200的材料为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材。
此外,该承载板9例如为半导体材料(如硅或玻璃)的圆形板体,其供该第一承载结构20的第一绝缘层200接置。
另外,该导电体23例如为柱状体、线状体或球状体,其设于该第一线路层201上并电性连接该第一线路层201(或该第一天线馈入线路270与第二天线馈入线路290),且形成该导电体23的材料为如铜、金的金属材或焊锡材。应可理解地,该导电体23的种类繁多,例如也可为被动元件,并不限于上述。
另外,该电子元件21为主动元件、被动元件或其二者组合,且该主动元件为例如半导体芯片,而该被动元件为例如电阻、电容及电感。于本实施例中,该电子元件21为半导体芯片,其具有相对的作用面21a与非作用面21b,该电子元件21以其非作用面21b经由一固晶层21c粘固于该第一承载结构20的第一侧20a上,且该作用面21a具有多个电极垫210,并于该多个电极垫210上形成有多个导电凸块213及至少一用以覆盖该些电极垫210与导电凸块213的保护膜(本实施例以两层保护膜211,212进行说明),其中,该些保护膜211,212例如为聚对二唑苯(PBO)、氮化物(如氮化硅)、氧化物(如氧化硅),且该些导电凸块213为如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud),但不限于此。应可理解地,该电子元件21也可以其作用面21a经由该些导电凸块213以覆晶方式结合并电性连接该第一承载结构20。因此,有关该电子元件21连接该承载结构的方式繁多,如打线封装方式,并不限于上述。
如图2B所示,形成一包覆层25于该第一承载结构20的第一侧20a上,以令该包覆层25包覆该电子元件21与该些导电体23,再经由整平制程,令上层的保护膜212、该导电体23的端面与该导电凸块213的端面外露于该包覆层25,使该包覆层25的上表面齐平该上层的保护膜212、该导电体23的端面与该导电凸块213的端面。
于本实施例中,该包覆层25为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dryfilm)、环氧树脂(epoxy)或封装材(molding compound),其可用压合(lamination)或模压(molding)的方式形成于该第一承载结构20的第一侧20a上。
此外,该整平制程经由研磨方式,移除该导电体23、保护膜212、导电凸块213与包覆层25的部分材料,而使该包覆层25的上表面齐平该保护膜212、该导电体23的端面与该导电凸块213的端面。
如图2C所示,形成一第二承载结构22于该包覆层25上,使该第二承载结构22堆叠于该第一承载结构20上以形成一封装模块2a,且令该第二承载结构22电性连接该些导电体23与该导电凸块213。
于本实施例中,该第二承载结构22为无核心层的线路构造,其包括多个第二绝缘层220、及设于该第二绝缘层220上的多个如RDL的第二线路层221,且最外层的第二绝缘层220可作为防焊层,以令最外层的第二线路层221外露于该防焊层。或者,该第二承载结构22也可仅包括单一第二绝缘层220及单一第二线路层221。
此外,形成该第二线路层221的材料为铜,且形成该第二绝缘层220的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)的介电材。
另外,该第一线路层201经由该些导电体23电性连接该第二线路层221,以令该第一天线馈入线路270与第二天线馈入线路290电性连接至该电子元件21。
另外,形成多个如焊球的导电元件24于最外层的第二线路层221上。例如,可形成一凸块底下金属层(Under Bump Metallurgy,简称UBM)240于最外层的第二线路层221上,以利于结合该导电元件24。
如图2D所示,移除该承载板9,并翻转整体结构,以令最外侧第一绝缘层200作为绝缘保护层,且于该最外侧第一绝缘层200上形成多个开孔900,以令部分该第一线路层201外露于该些开孔900。
于本实施例中,也可再形成一如防焊层的绝缘保护层(图未示)于该第一承载结构20的第二侧20b上,且于该绝缘保护层中形成多个开孔,以令部分该第一线路层201外露于该些开孔。因此,有关该封装模块2a的种类繁多,并不限于上述。
如图2E所示,经由多个支撑件26将一天线模块2b堆叠于该封装模块2a的第一承载结构20的第二侧20b上,使该天线模块2b与该第一承载结构20之间形成空旷区A。
于本实施例中,该天线模块2b包含有一基板本体28,其为封装基板型式,例如为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构,以于介电材上经由溅镀(sputtering)、蒸镀(vaporing)、电镀、无电电镀、化镀或贴膜(foiling)等方式形成多个厚度轻薄的天线本体27,29。例如,该基板本体28定义有相对的第一表面28a与第二表面28b,以令该基板本体28以其第一表面28a经由该些支撑件26设于该第一承载结构20的第二侧20b上,且该天线本体27,29具有相互分离且相对应配置于该第一表面28a与该第二表面28b的一第一天线层271,291与一第二天线层272,292。具体地,该第一天线层271,291作为内天线,且该第二天线层272,292作为外天线。
此外,该第一天线层271,291与该第二天线层272,292以耦合方式传输信号。例如,该第一天线层271,291与该第二天线层272,292可由交变电压、交变电流或辐射变化产生辐射能量,且该辐射能量为电磁场,以令该第一天线层271,291与该第二天线层272,292能相互电磁耦合,使天线信号能于该第一天线层271,291与该第二天线层272,292之间传递。具体地,该些第一天线层271,291也电磁耦合该第一天线馈入线路270与第二天线馈入线路290,使天线信号能于该些天线本体27,29与该第一线路层201之间传递(如发送或接收),故该天线模块2b与该第一承载结构20形成天线组件2’,且该天线本体27,29及第一天线馈入线路270与第二天线馈入线路290可视为天线结构。
另外,该基板本体28的第一表面28a上具有多个深度H1,H2不同的凹部280,281,其分别对应该些天线本体27,29配置,以令该第一天线层271,291形成于该凹部280,281的底面上。经由该第一天线层271,291与该第一天线馈入线路270及第二天线馈入线路290的距离D1,D2愈大,则频宽愈宽的特性,因而有利于调整辐射频率。因此,相比于形成于该第一表面28a上的天线层,形成于该凹部280,281中的天线层,将增加该第一天线层271,291与该第一天线馈入线路270及第二天线馈入线路290之间的距离D1,D2。另一方面,经由该第一天线层271,291与该第二天线层272,292之间的距离L1,L2愈短,则频率愈高的特性,而可依需求调控该凹部280,281的深度H1,H2进而调控该第一天线层271,291与该第二天线层272,292之间的距离L1,L2,以获取所需的多个频率。
另外,该支撑件26为柱状或墙状,其接合该些开孔900中的第一线路层201但未信号连接该第一线路层201,故该支撑件26仅作为支撑用而不具有信号传输功能。例如,该支撑件26可为绝缘材或如焊锡的导电材,并无特别限制。
如图2F所示,沿如图2E所示的切割路径S进行切单制程,以完成该电子封装件2的制法。
于本实施例中,该电子封装件2可经由该些导电元件24接置一如电路板的电子装置(图略),且该天线模块2b利用该第一天线馈入线路270及第二天线馈入线路290经由该导电体23及第二承载结构22,以接收/传递天线信号至该电子元件21。
本实施例主要经由在第一天线层271,291与该第一天线馈入线路270及第二天线馈入线路290之间采用低介电常数构造,其包含空气间隔(air gap)A1,A2(其由空旷区A与凹部280,281构成)作为信号传递介质,使该电子封装件2(或该天线组件2’)的天线结构的整体辐射效率提升。
此外,经由该凹部280,281的设计,以调整该空气间隔A1,A2的高度,即调整该第一天线层271,291与该第二天线层272,292电磁耦合的距离L1,L2而可产生不同频率的5G毫米波,使该电子封装件2(或该天线组件2’)的天线结构可依需求传递不同的天线信号,例如,该第一天线馈入线路270、第一天线层271与第二天线层272之间作为低频天线部27a,且该第二天线馈入线路290、第一天线层291与第二天线层292之间作为高频天线部29a。具体地,该电子元件21经由该低频天线部27a收发28吉赫(GHz)频率的5G毫米波信号;或者,该电子元件21经由该高频天线部29a收发60吉赫(GHz)频率的5G毫米波信号。
因此,相比于现有技术,本实施例经由该天线模块2b包含多种频率的天线部(该低频天线部27a及高频天线部29a)的设计,使单一该电子封装件2即可对应多种频率的射频产品的需求,以取代多个对应不同频率的封装模块2a,因而可缩减产品尺寸,以利于该电子封装件2(或该天线组件2’)符合微小化的需求。
另外,本发明将该天线模块2b叠置于该第一承载结构20上,因而无需于该第一承载结构20上增加布设区域,使本实施例的制法能于预定的第一承载结构20尺寸下制作各种频率的天线(即毫米波式天线),进而使该电子封装件2(或该天线组件2’)能符合微小化的需求。
图3A至图3E为本发明的电子封装件3的第二实施例的制法的剖视示意图。本实施例与第一实施例大致相同,故以下仅说明相异处,而不再赘述相同处。
如图3A所示,提供一设有多个导电体33的第一承载结构30、及一设有电子元件21的第二承载结构32。
所述的第一承载结构30具有相对的第一侧30a及第二侧30b,且该第一侧30a及第二侧30b上形成有例如防焊层的绝缘保护层302。于本实施例中,该第一承载结构30为封装基板,其包含具有核心层的线路构造或无核心层的线路构造,该线路构造包含如介电材的绝缘体300及形成于该绝缘体300上的第一线路层301,如扇出(fan out)型RDL,且该第一线路层301具有第一天线馈入线路270与第二天线馈入线路290,使该第一承载结构30可视为天线基板。具体地,该介电材为例如预浸材(PP)、聚酰亚胺(PI)、环氧树脂或玻纤(glassfiber),且形成该第一线路层301的材料为金属,如铜。应可理解地,该第一承载结构30也可为其它承载芯片的载体,如有机板材、晶圆(wafer)、或其它具有金属布线(routing)的载板,并不限于上述,且该第一承载结构30因属于板材而可免用如图2A所示的承载件9。
此外,该绝缘保护层302形成有多个开孔302a,以令该第一线路层301的部分表面外露于该些开孔302a。
所述的第二承载结构32为封装基板,其包含具有核心层的线路构造或无核心层的线路构造,该线路构造包含如介电材的绝缘体320及形成于该绝缘体320上的第二线路层321,如扇出型RDL。具体地,该介电材为例如预浸材(PP)、聚酰亚胺(PI)、环氧树脂或玻纤(glass fiber),且形成该第二线路层321的材料为金属,如铜。应可理解地,该第二承载结构32也可为其它承载芯片的载体,如有机板材、晶圆(wafer)、或其它具有金属布线(routing)的载板,并不限于上述。
所述的电子元件21以其电极垫210经由多个如焊锡材料的导电凸块313以覆晶方式电性连接该第二承载结构32。
所述的导电体33形成于该第一承载结构30的第一侧30a上。于本实施例中,该导电体33为多种材料形式,其具有核心块330与包覆该核心块330的导电材331,其中,该核心块330为如塑料球的绝缘材或如铜球的金属材,且该导电材331为焊锡材,如镍锡、锡铅或锡银,但不限于此。应可理解地,该导电体33也可为被动元件或如图2A所示的单一材料形式。
如图3B所示,将该第一承载结构30经由该些导电体33堆叠于该第二承载结构32上,并回焊该导电材331,使该第一承载结构30固接该第二承载结构32以形成一封装模块3a,且该电子元件21位于该第一承载结构30与该第二承载结构32之间。
于本实施例中,该第一承载结构30经由该些导电体33电性连接该第二承载结构32。
如图3C所示,形成一包覆层25于该第一承载结构30与该第二承载结构32之间,以包覆该些导电体33、导电凸块313与该电子元件21。
于本实施例中,如图3C-1所示,也可先形成底胶35于该第二承载结构32与该电子元件21之间以包覆该些导电凸块313,再形成该包覆层25,以包覆该些导电体33、底胶35与该电子元件21。
如图3D所示,接续图3C所示的制程,于该第一承载结构30上经由多个支撑件26堆叠天线模块2b,且令第一天线层271,291的位置对应该第一天线馈入线路270与第二天线馈入线路290的位置,使天线信号能于天线本体27,29与该第一线路层301之间传递,其中,该天线模块2b与该第一承载结构30视为天线组件3’,且该第一天线馈入线路270与第二天线馈入线路290、第一天线层271,291及第二天线层272,292视为天线结构。
于本实施例中,该些支撑件26接合该些开孔302a中的第一线路层301但未信号连接该第一线路层301,故该支撑件26仅作为支撑用而不具有信号传输功能。
如图3E所示,形成多个如焊球的导电元件24于该第二承载结构32上,且沿如图3D所示的切割路径S进行切单制程,以完成该电子封装件3的制法。
本实施例经由在第一天线层271,291与该第一天线馈入线路270及第二天线馈入线路290之间采用空气间隔A1,A2作为信号传递介质,使该电子封装件3的天线组件3’的整体辐射效率提升。
此外,经由该凹部280,281的设计,以调整该空气间隔A1,A2的高度,即调整该第一天线层271,291与该第二天线层272,292电磁耦合的距离L1,L2而可产生不同频率的5G毫米波,使该电子封装件3(或该天线组件3’)的天线结构可依需求传递不同的天线信号。因此,相比于现有技术,本实施例经由该天线模块2b包含多种频率的天线部(该低频天线部27a及高频天线部29a)的设计,使单一该电子封装件3即可对应多种频率的射频产品的需求,以取代多个对应不同频率的封装模块3a,因而可缩减产品尺寸,以利于该电子封装件2(或该天线组件3’)符合微小化的需求。
另外,本实施例将该天线模块2b叠置于该第一承载结构30上,因而无需于该第一承载结构30上增加布设区域,使本发明的制法能于预定的第一承载结构30尺寸下制作各种频率的天线(即毫米波式天线),进而使该电子封装件3能符合微小化的需求。
图4A至图4C为本发明的天线模块2b的制法的剖视示意图。
如图4A所示,提供一基板本体28,其具有相对的第一表面28a与第二表面28b,以于该基板本体28的第二表面28b上以电镀金属材方式形成第二天线层272,292,从而作为外天线。
如图4B所示,于该基板本体28的第一表面28a上以例如蚀刻方式形成多个深度H1,H2不同的凹部280,281。
如图4C所示,于该凹部280,281的底面上以电镀金属材方式形成第一天线层271,291,从而作为内天线,且于该基板本体28的第一表面28a上的外围区域形成多个支撑件26。
应可理解地,有关形成天线层的方式繁多,并不限于上述,且形成凹部280,281的方式也相当多种,并不限于上述。例如,可先形成该凹部280,281,再制作该第二天线层272,292。
本发明还提供一种电子封装件2,3,包括:一具有第一天线馈入线路270与第二天线馈入线路290的第一承载结构20,30以及一天线模块2b。
所述的天线模块2b设于第一承载结构20,30上,且该天线模块2b包含有一基板本体28,其具有相对的第一表面28a与第二表面28b,以令该基板本体28以其第一表面28a设于该第一承载结构20,30上,其中,该基板本体28的第一表面28a上具有多个不同深度H1,H2的凹部280,281,以于该多个凹部280,281中形成有第一天线层271,291,且基板本体28的第二表面28b上具有对应该第一天线层271,291配置的第二天线层272,292,使该第一天线层271,291电磁耦合第一天线馈入线路270及第二天线馈入线路290与第二天线层272,292。
于一实施例中,该第一天线层271,292与该第一天线馈入线路270及第二天线馈入线路290之间形成空气间隔A1,A2。
于一实施例中,该天线模块2b经由多个支撑件26设于该第一承载结构20,30上。
于一实施例中,该电子封装件2,3还包括:第二承载结构22,32以及至少一电子元件21,且该第一承载结构20,30具有相对的第一侧20a,30a与第二侧20b,30b,以令该天线模块2b设于该第一承载结构20,30的第二侧20b,30b上。
所述的第二承载结构22,32经由多个导电体22,33堆叠于该第一承载结构20,30的第一侧20a,30a上。
所述的电子元件21设于该第一承载结构20,30与第二承载结构22,32之间并电性连接该导电体23,33。
于一实施例中,该第一承载结构20,30经由该导电体23,33电性连接该第二承载结构22,32。
于一实施例中,该第一天线馈入线路270与第二天线馈入线路290电性连接该导电体23,33,以电性导通至该电子元件21。
于一实施例中,所述的电子封装件2,3还包括一包覆层25,其形成于该第一承载结构20,30与第二承载结构22,32之间,以包覆该电子元件21。
于一实施例中,所述的电子封装件2,3还包括形成于该第二承载结构22,32上的多个导电元件24,其与该导电体23,33分别位于该第二承载结构22,32的不同侧。
综上所述,本发明的电子封装件及其制法暨天线组件与其制法,经由在第一天线层与天线馈入线路之间采用空气间隔作为信号传递介质,以提升该电子封装件(或该天线组件)的天线结构的整体辐射效率。
此外,本发明经由该多个不同深度的凹部的设计,以调整该第一天线层与第二天线层电磁耦合的距离而产生不同频率,使该电子封装件(或该天线组件)的天线可依需求传递不同的天线信号,故本发明的单一该电子封装件即可对应多种频率的射频产品的需求,以取代多个对应不同频率的封装模块,因而可缩减产品尺寸,以利于该电子封装件(或该天线组件)符合微小化的需求。
另外,经由将该天线模块叠置于该第一承载结构上,因而无需于该第一承载结构上增加布设区域,故能于预定的第一承载结构尺寸下制作各种频率的天线,以利于该电子封装件(或该天线组件)符合微小化的需求。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。

Claims (17)

1.一种电子封装件,其特征在于,包括:
第一承载结构,其具有多个天线馈入线路;以及
天线模块,且设于该第一承载结构上,且该天线模块包含具有相对的第一表面与第二表面的基板本体,以令该基板本体以其第一表面设于该第一承载结构上,其中,该基板本体的第一表面上具有多个不同深度的凹部,以于该多个凹部中形成有第一天线层,且基板本体的第二表面上具有对应该第一天线层配置的第二天线层,使该第一天线层电磁耦合该天线馈入线路与第二天线层。
2.如权利要求1所述的电子封装件,其特征在于,该第一天线层与该天线馈入线路之间形成空气间隔。
3.如权利要求1所述的电子封装件,其特征在于,该天线模块经由支撑件设于该第一承载结构上。
4.如权利要求1所述的电子封装件,其特征在于,该第一承载结构具有相对两侧,以令该天线模块设于该第一承载结构的其中一侧上,且该电子封装件还包括:
第二承载结构,其经由多个导电体堆叠于该第一承载结构的另一侧上;以及
至少一电子元件,其设于该第一承载结构与第二承载结构之间并电性连接该导电体。
5.如权利要求4所述的电子封装件,其特征在于,该第一承载结构经由该导电体电性连接该第二承载结构。
6.如权利要求4所述的电子封装件,其特征在于,该天线馈入线路电性连接该导电体,以电性导通至该电子元件。
7.如权利要求4所述的电子封装件,其特征在于,该电子封装件还包括包覆层,其形成于该第一承载结构与第二承载结构之间以包覆该电子元件。
8.如权利要求4所述的电子封装件,其特征在于,该电子封装件还包括形成于该第二承载结构上的多个导电元件,其与该导电体分别位于该第二承载结构的不同侧。
9.一种电子封装件的制法,其特征在于,包括:
提供一基板本体,其具有相对的第一表面与第二表面,且该第二表面上具有第二天线层;
形成多个不同深度的凹部于该基板本体的第一表面上;
形成第一天线层于该多个凹部中,使该第一天线层电磁耦合该第二天线层;以及
将该基板本体以其第一表面设于一具有多个天线馈入线路的第一承载结构上,使该第一天线层电磁耦合该天线馈入线路。
10.如权利要求9所述的电子封装件的制法,其特征在于,该第一天线层与该天线馈入线路之间形成空气间隔。
11.如权利要求9所述的电子封装件的制法,其特征在于,该基板本体经由支撑件设于该第一承载结构上。
12.如权利要求9所述的电子封装件的制法,其特征在于,该基板本体的第一表面上以蚀刻方式形成该多个凹部。
13.如权利要求9所述的电子封装件的制法,其特征在于,该第一承载结构具有相对两侧,以令该该基板本体设于该第一承载结构的其中一侧上,且该制法还包括:
将第二承载结构经由多个导电体堆叠于该第一承载结构的另一侧上,且将至少一电子元件设于该第一承载结构与第二承载结构之间并电性连接该导电体。
14.如权利要求13所述的电子封装件的制法,其特征在于,该第一承载结构经由该导电体电性连接该第二承载结构。
15.如权利要求13所述的电子封装件的制法,其特征在于,该天线馈入线路电性连接该导电体,以电性导通至该电子元件。
16.如权利要求13所述的电子封装件的制法,其特征在于,该制法还包括于该第一承载结构与第二承载结构之间形成包覆该电子元件的包覆层。
17.如权利要求13所述的电子封装件的制法,其特征在于,该制法还包括于该第二承载结构上设置多个导电元件,其与该导电体分别位于该第二承载结构的不同侧。
CN202110219310.2A 2021-02-18 2021-02-26 电子封装件及其制法 Active CN114976582B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110105520 2021-02-18
TW110105520A TWI762197B (zh) 2021-02-18 2021-02-18 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
CN114976582A true CN114976582A (zh) 2022-08-30
CN114976582B CN114976582B (zh) 2025-02-18

Family

ID=82198949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110219310.2A Active CN114976582B (zh) 2021-02-18 2021-02-26 电子封装件及其制法

Country Status (3)

Country Link
US (2) US11682826B2 (zh)
CN (1) CN114976582B (zh)
TW (1) TWI762197B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220131116A (ko) * 2021-03-19 2022-09-27 삼성전자주식회사 안테나 구조 및 이를 포함하는 전자 장치
TWI859849B (zh) * 2023-05-10 2024-10-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI865198B (zh) * 2023-11-27 2024-12-01 友達光電股份有限公司 天線封裝結構

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002019464A2 (en) * 2000-08-30 2002-03-07 Koninklijke Philips Electronics N.V. An antenna device
CN103050482A (zh) * 2011-10-17 2013-04-17 矽品精密工业股份有限公司 封装结构及其制法
CN104752820A (zh) * 2014-11-12 2015-07-01 中国人民解放军国防科学技术大学 一种背腔缝隙天线阵列
US20190319347A1 (en) * 2018-04-17 2019-10-17 Siliconware Precision Industries Co., Ltd. Electronic package and electronic device having the electronic package

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7675465B2 (en) * 2007-05-22 2010-03-09 Sibeam, Inc. Surface mountable integrated circuit packaging scheme
US8457581B2 (en) * 2009-06-09 2013-06-04 Broadcom Corporation Method and system for receiving I and Q RF signals without a phase shifter utilizing a leaky wave antenna
US8508422B2 (en) * 2009-06-09 2013-08-13 Broadcom Corporation Method and system for converting RF power to DC power utilizing a leaky wave antenna
TWI659518B (zh) * 2017-05-18 2019-05-11 矽品精密工業股份有限公司 電子封裝件及其製法
US11509038B2 (en) * 2017-06-07 2022-11-22 Mediatek Inc. Semiconductor package having discrete antenna device
US10957982B2 (en) * 2018-04-23 2021-03-23 Samsung Electro-Mechanics Co., Ltd. Antenna module formed of an antenna package and a connection member
US20190348747A1 (en) * 2018-05-14 2019-11-14 Mediatek Inc. Innovative air gap for antenna fan out package
US11424197B2 (en) * 2018-07-27 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same
US10971798B2 (en) * 2018-10-18 2021-04-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
TWI696255B (zh) * 2019-04-09 2020-06-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI700801B (zh) * 2019-09-16 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
CN111564373A (zh) * 2020-05-20 2020-08-21 甬矽电子(宁波)股份有限公司 具有天线的基板的制作方法、封装天线结构和电子设备
CN115036669B (zh) * 2022-06-22 2025-02-14 江苏长电科技股份有限公司 天线封装结构及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002019464A2 (en) * 2000-08-30 2002-03-07 Koninklijke Philips Electronics N.V. An antenna device
CN103050482A (zh) * 2011-10-17 2013-04-17 矽品精密工业股份有限公司 封装结构及其制法
CN104752820A (zh) * 2014-11-12 2015-07-01 中国人民解放军国防科学技术大学 一种背腔缝隙天线阵列
US20190319347A1 (en) * 2018-04-17 2019-10-17 Siliconware Precision Industries Co., Ltd. Electronic package and electronic device having the electronic package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
袁诚等: ""一种新型亚毫米波反射面天线设计"", 《计算机仿真》, 15 August 2020 (2020-08-15) *

Also Published As

Publication number Publication date
US12057618B2 (en) 2024-08-06
CN114976582B (zh) 2025-02-18
US11682826B2 (en) 2023-06-20
US20230275337A1 (en) 2023-08-31
TW202234604A (zh) 2022-09-01
US20220263221A1 (en) 2022-08-18
TWI762197B (zh) 2022-04-21

Similar Documents

Publication Publication Date Title
TWI745238B (zh) 電子封裝件
CN112510019B (zh) 电子封装件及其制法
TWI696255B (zh) 電子封裝件及其製法
TWI762197B (zh) 電子封裝件及其製法
TWI698046B (zh) 電子封裝件及其製法
TWI769119B (zh) 電子封裝件及其製法
TW202320408A (zh) 電子裝置及其製造方法
CN116073133A (zh) 电子装置及其制造方法
US20240379590A1 (en) Electronic package and manufacturing method thereof
TWI793024B (zh) 電子封裝件及其製法
TWI815314B (zh) 電子封裝件及其製法
TW201947727A (zh) 電子封裝件及其製法
US20240145908A1 (en) Electronic package and manufacturing method thereof
CN115706330A (zh) 封装基板

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant