CN114968685B - Testing Method for Single Event Upset Cross Section of EDAC Hardened Microprocessor - Google Patents

Abstract

The present invention discloses a test method for a single particle upset cross section of an EDAC reinforced microprocessor, the steps of which include: S1. configuring a test program of the tested EDAC reinforced microprocessor, and testing the time taken by the test program to complete one operation and the area of the SRAM component of the tested EDAC reinforced microprocessor used in the operation; S2. initializing the high-energy particle injection rate according to the time and area obtained by the test; S3. continuously injecting high-energy particles to irradiate the tested EDAC reinforced microprocessor according to the high-energy particle injection rate, and starting the test program of the tested EDAC reinforced microprocessor, and counting the number of soft errors that the test program is not completed within the time and the number of wrong operation results, until the total injection amount reaches a preset value; S4. calculating the single particle upset cross section of the tested EDAC reinforced microprocessor according to the statistical number of soft errors and the total injection amount. The present invention has the advantages of simple implementation method, high test efficiency and high precision.

Description

Testing Method for Single Event Upset Cross Section of EDAC Hardened Microprocessor

Technical Field

The invention relates to the technical field of single particle effect testing, and in particular to a testing method for a single particle upset cross section of an EDAC reinforced microprocessor.

Background technique

Microprocessors have been increasingly widely used in the fields of aviation and aerospace due to their high integration, strong computing power, and rich IO interfaces. However, the SRAM components that store programs and data inside microprocessors used in harsh radiation environments such as aviation and aerospace are prone to single-event upsets (SEUs) under the bombardment of high-energy particles in space, resulting in soft errors and inestimable losses. Therefore, it is particularly important to accurately test the sensitivity of microprocessors to single-event upsets.

The sensitivity of a microprocessor to single-particle upset effects is generally expressed using a single-particle upset cross section C. The single-particle upset cross section C refers to the area of the microprocessor where soft errors will occur when bombarded by high-energy particles with a certain LET (Linear Energy Transfer). When testing the single-particle upset cross section of a microprocessor on the ground, high-energy particles are generally generated by a high-energy particle accelerator. For example, Chinese patent application 200780027325.7 discloses a single-particle upset test circuit and method, which tests the single-particle upset effect of its internal storage unit by configuring the microprocessor in a scan chain mode; and Chinese patent application 201810193529.8 discloses a test method for the single-particle upset cross section of a microprocessor, which comprehensively reflects the single-particle upset sensitivity of the entire microprocessor under test by testing the single-particle upset cross sections of the microprocessor core, internal memory, and peripheral components separately and summing them.

However, when used in harsh radiation environments such as aviation and aerospace, the SRAM components that store programs and data inside the microprocessor often need to use EDAC (Error Detection And Correction) circuits for single-particle upset reinforcement. When the microprocessor reads multi-bit data stored at a certain address in the SRAM component, the EDAC circuit will decode and check the data. If it is found that the data has an SEU (single-particle upset), the EDAC circuit will correct it. As the size of semiconductor processes decreases, a high-energy particle may cause SEU to occur simultaneously in multiple physically adjacent storage bits in the SRAM component inside the microprocessor, which is the multi-bit upset effect (Multi-Bit Upset, MBU). This may cause the number of data bits that have SEU in the multi-bit data stored at one address in the SRAM component to exceed the number of error-correctable bits of the EDAC circuit, thereby causing the EDAC circuit to fail.

In the prior art, when testing the single particle upset cross section of a microprocessor on the ground, a very high fluence rate is usually used to shorten the test time. The fluence rate is the number of high-energy particles that bombard the microprocessor per unit area per unit time. For example, during testing, the high-energy particle fluence rate is often more than 10,000 times the high-energy particle flux in actual space. However, the flux of high-energy particles in actual space is very low, and if the fluence rate of high-energy particles is high, the single particle upset cross section of the EDAC reinforced microprocessor may be mistakenly overestimated. The single particle upset cross section test methods of microprocessors in the prior art do not consider the impact of the high-energy particle fluence rate on the single particle upset resistance of the EDAC circuit in the microprocessor, so the test accuracy and effectiveness are not high.

Summary of the invention

The technical problem solved by the present invention is: in view of the technical problems existing in the prior art, a testing method for the single particle upset cross section of an EDAC reinforced microprocessor is proposed, which has a simple implementation method, high testing efficiency and high precision. The method can take into account the influence of the high-energy particle injection rate on the single particle upset resistance capability of the EDAC circuit in the microprocessor, and realize efficient and accurate testing of the single particle upset resistance capability of the EDAC circuit in the microprocessor.

In order to solve the above technical problems, the technical solution proposed by the present invention is:

A method for testing the single event upset cross section of an EDAC-reinforced microprocessor, comprising the following steps:

S1. A test program configured to test the EDAC reinforced microprocessor under test, and to test the time T taken to complete a run of the test program, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used by the test program to run;

S2. The time T taken to complete a run of the test program obtained from the test, the area S of the tested EDAC reinforced microprocessor SRAM component used to initialize the high-energy particle fluence rate F;

S3. Continuously injecting high-energy particles according to the high-energy particle injection rate F to irradiate the EDAC reinforced microprocessor under test, and starting the test program of the EDAC reinforced microprocessor under test, and counting the number of soft errors of the test program not being completed within the time T and the number of soft errors of the running results being wrong, until the total injection amount reaches a preset value;

S4. Calculate the single event upset cross section of the EDAC reinforced microprocessor under test according to the number of soft errors counted in step S3 and the total injection amount.

Furthermore, in step S2, the high-energy particle fluence rate F is initialized according to the number of error bits m that can be corrected by the EDAC circuit in the EDAC hardened microprocessor under test, the time T taken by the test program to complete one run, and the area S of the SRAM component of the EDAC hardened microprocessor under test used in the test program run.

Furthermore, in step S2, the high-energy particle fluence rate F is initialized specifically according to the following formula:

F＝(C ₀ ·m)/(T·S)

Wherein, m is the number of error bits that can be corrected by the EDAC circuit in the EDAC reinforced microprocessor under test, _C0 is a preset coefficient, T is the time taken by the test program to complete one run, and S is the area of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run.

Furthermore, the preset coefficient C ₀ is a real number between 0.1 and 1.

Furthermore, the steps of step S3 include:

S301. Initialize the soft error count variable K=0;

S302. Irradiate the EDAC reinforced microprocessor under test according to the high-energy particles at a fluence rate F and start counting the total fluence Q;

S303. Determine whether the current total injection volume Q reaches the preset value, if yes, proceed to step S306, otherwise proceed to step S304;

S304. Control the EDAC reinforced microprocessor under test to start running the test program. If the test program completes one run within the time T and outputs the run result, go to S305. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303.

S305. Determine whether the running result currently output by the test program is correct. If it is correct, go to step S303. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303.

S306. Stop high-energy particle irradiation and output the current value of the soft error count variable K and the current total injection amount.

Furthermore, in step S4, the single event upset cross section C of the EDAC reinforced microprocessor under test is calculated according to the following formula:

C = K/Q;

Wherein, K is the soft error count value, and Q is the total injection amount.

Furthermore, the EDAC circuit in the EDAC reinforced microprocessor under test has a correction-one-check-two function.

Compared with the prior art, the advantages of the present invention are: the testing method of the single particle upset cross section of the EDAC reinforced microprocessor of the present invention first tests the time taken by the test program to complete one run and the area of the SRAM component of the tested EDAC reinforced microprocessor used in the test program running, initializes the high-energy particle fluence rate based on the time and area, and then irradiates the tested EDAC reinforced microprocessor according to the high-energy particle fluence rate to realize the test of the single particle upset cross section of the tested EDAC reinforced microprocessor, and can use a suitable high-energy particle fluence rate during the single particle upset cross section test to avoid excessively high fluence rate, thereby ensuring that the EDAC circuit in the microprocessor works normally during the high-energy particle irradiation process, so that the single particle upset resistance capability of the EDAC circuit will not be affected, and the accuracy of the single particle upset cross section test of the EDAC reinforced microprocessor is greatly improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the implementation flow of the method for testing the single event upset cross section of an EDAC-reinforced microprocessor according to this embodiment.

FIG. 2 is a schematic diagram of a detailed implementation flow of a single-event upset cross-section test for an EDAC-reinforced microprocessor in a specific application embodiment of the present invention.

Detailed ways

The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

As the size of semiconductor processes shrinks, a high-energy particle may cause SEU to occur simultaneously in multiple physically adjacent storage bits in the SRAM component inside the microprocessor, i.e., the multi-bit upset effect (Multi-Bit Upset, MBU), which may cause the number of data bits that experience SEU in the multi-bit data stored in one address of the SRAM component to exceed the number of bits that can be corrected by the EDAC circuit, causing the EDAC circuit to fail. In order to suppress the failure of the EDAC circuit caused by MBU, the bit interleaving technology is usually used while using the EDAC circuit, that is, the physically adjacent storage bits in the SRAM component inside the microprocessor are distributed at different addresses. Even if MBU occurs in multiple physically adjacent storage bits, each storage bit that is flipped is also located at a different address, so the number of data bits that are flipped in the multi-bit data stored at one address will not exceed the number of bits that can be corrected by the EDAC circuit, ensuring that the EDAC circuit can correct the flipped bits even if multiple bits are flipped in the microprocessor. However, if the high-energy particle injection rate is high, the number of high-energy particles bombarding the microprocessor in the interval between two detections of the same address by the EDAC circuit exceeds the number of bits that can be corrected by the EDAC circuit, and the EDAC circuit may still fail.

The present invention takes the above-mentioned problems into consideration, first tests the time T taken for the test program to complete one run, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run, initializes the high-energy particle fluence rate F based on the time T and the area S, and then irradiates the EDAC reinforced microprocessor under test according to the high-energy particle fluence rate F to implement the test of calculating the single particle upset cross section C of the EDAC reinforced microprocessor under test. Since the high-energy particle fluence rate F is determined by using the time T taken for the test program of the EDAC reinforced microprocessor under test to complete one run, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run, it can avoid the fluence rate being too high, ensure the normal operation of the EDAC circuit in the microprocessor during the high-energy particle irradiation process, so that the single particle upset resistance capability of the EDAC circuit will not be affected, and greatly improve the accuracy of the single particle upset cross section test of the EDAC reinforced microprocessor.

As shown in FIG. 1 , the specific steps of the method for testing the single event upset cross section of an EDAC-reinforced microprocessor in this embodiment include:

S1. A test program configured to test the EDAC reinforced microprocessor under test, and to test the time T taken to complete a run of the test program, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used by the test program to run;

S2. The time T taken to complete a run of the test program obtained from the test, the area S of the tested EDAC reinforced microprocessor SRAM component used to initialize the high-energy particle injection rate F;

S3. Continuously inject high-energy particles according to the high-energy particle injection rate F to irradiate the EDAC reinforced microprocessor under test, and start the test program of the EDAC reinforced microprocessor under test, and count the number of soft errors of the test program not being completed within the time T and the number of soft errors of the running results being wrong, until the total injection amount reaches a preset value;

S4. Calculate the single event upset cross section of the EDAC reinforced microprocessor under test according to the number of soft errors counted in step S3 and the total injection amount.

The test program in the above step S1 can adopt the test method of single-particle upset cross section of microprocessor disclosed in Chinese patent application 201810193529.8 to realize the test of area S of the EDAC reinforced microprocessor SRAM component under test. Of course, the test program can also be designed by other methods in the prior art according to actual needs.

In step S2 of this embodiment, the high-energy particle fluence rate F is initialized according to the number of correctable error bits m of the EDAC circuit in the EDAC reinforced microprocessor under test, the time T used to complete one run of the test program, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run. Considering that physically adjacent storage bits in the SRAM component inside the microprocessor are distributed at different addresses, even if multiple physically adjacent storage bits have MBU, each storage bit that has flipped is also located at a different address, then the number of data bits flipped in the multi-bit data stored at one address will not exceed the number of correctable error bits of the EDAC circuit. This embodiment comprehensively determines the high-energy particle fluence rate F by combining the number of correctable error bits m of the EDAC circuit in the EDAC reinforced microprocessor under test, the time T used to complete one run of the test program, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run, so that a suitable high-energy particle fluence rate F can be reasonably determined to avoid the fluence rate being too high to affect the test accuracy.

In step S2 of this embodiment, the high-energy particle fluence rate F is initialized according to the following formula:

F＝(C ₀ ·m)/(T·S) (1)

Wherein, m is the number of error bits that can be corrected by the EDAC circuit in the tested EDAC reinforced microprocessor, _C0 is a preset coefficient, which can be a real number between 0.1 and 1, preferably, _C0 can be selected as 0.8. T is the time taken by the test program to complete one run, and S is the area of the SRAM component of the tested EDAC reinforced microprocessor used in the test program run.

By initializing the high-energy particle fluence rate F through the above formula, the number of correctable error bits m of the EDAC circuit in the EDAC reinforced microprocessor under test, the time T taken for the test program to complete one run, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the test program run can be comprehensively considered, and finally an optimal high-energy particle fluence rate F can be determined, thereby further improving the test accuracy of the single-particle upset cross section of the EDAC reinforced microprocessor.

In this embodiment, the specific steps of step S3 include:

S301. Initialize the soft error count variable K=0;

S302. Irradiate the EDAC reinforced microprocessor under test according to the high-energy particles at a fluence rate F and start counting the total fluence Q;

S303. Determine whether the current total injection volume Q reaches the preset value, if yes, proceed to step S306, otherwise proceed to step S304;

S304. Control the EDAC reinforced microprocessor under test to start running the test program. If the test program completes one run within the time T and outputs the run result, go to S305. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303.

S305. Determine whether the running result currently output by the test program is correct. If it is correct, go to step S303. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303.

S306. Stop high-energy particle irradiation and output the value of the current soft error count variable K and the current total injection amount.

In step S4 of this embodiment, the single event upset cross section C of the EDAC reinforced microprocessor under test is calculated specifically according to the following formula:

C＝K/Q(2)

Among them, K is the soft error count value, Q is the total injection amount, and the total injection amount is the number of high-energy particles bombarding the microprocessor per unit area. That is, when the total high-energy particle injection amount is Q, the number of soft errors that occur in the microprocessor under the bombardment of these high-energy particles is K, and the single-event upset cross section of the EDAC-hardened microprocessor under test is C=K/Q.

The preset value of the total injection amount in the above step S3 can be set specifically in accordance with the requirements for the total injection amount of high-energy particles in QJ10005A-2018.

In a specific application embodiment, the EDAC circuit in the EDAC reinforced microprocessor under test has a correction-one-detection-two function, that is, correcting a 1-bit error and detecting a 2-bit error, such as using an extended Hamming code encoding and decoding circuit with correction-one-detection-two. The EDAC circuit can also use other error correction and detection circuits with correction-m-detection-n (m＜n) functions, which can be specifically configured according to actual needs.

The present invention is further described below by taking the above method of the present invention in a specific application embodiment to implement a single event upset test on a certain type of EDAC reinforced microprocessor as an example, as shown in FIG2 , the detailed steps are as follows:

Step 1, design a test program for the EDAC reinforced microprocessor under test, which can output the running results and measure the time T taken by the test program to complete one run (specifically measured as T=0.5 seconds), and the area S of the SRAM component of the EDAC reinforced microprocessor under test used in the running of the test program (specifically measured as S=1.6×10-3cm2).

Step 2: Initialize the high-energy particle fluence rate F according to formula (1), where the number of correctable error bits m of the EDAC circuit in the EDAC reinforced microprocessor under test is specifically 1, and C ₀ is selected as 0.8, and the result is

Step 3, continuously injecting high-energy particles according to the high-energy particle injection rate F to irradiate the EDAC reinforced microprocessor under test, and starting the test program of the EDAC reinforced microprocessor under test, and counting the number of soft errors in which the test program is not completed within the time T and the number of soft errors in which the running results are erroneous, until the total injection amount reaches a preset value.

Step 3.1. Initialize the soft error count variable K=0.

Step 3.2. Use high energy particles at a fluence rate Irradiate the EDAC hardened microprocessor under test and start counting the total fluence Q.

Step 3.3. Determine whether the total high-energy particle injection Q reaches the preset value. If so, go to step 4; otherwise, go to step S3.4.

Step 3.4. The EDAC reinforced microprocessor under test starts running the above test program. If the above test program completes one run within T time and outputs the run result, go to step 3.5; otherwise, the K value increases by 1 and go to step 3.3.

Step 3.5. If the running result output by the above test program is correct, go to step 3.3; otherwise, increase the K value by 1 and go to step 3.3.

Step 4, stop high-energy particle irradiation, and calculate the single event upset cross section C=K/Q of the EDAC-hardened microprocessor under test according to formula (2).

The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims (7)

1. A method for testing the single event upset cross section of an EDAC-reinforced microprocessor, characterized in that the steps include: S1. A test program configured to test the EDAC reinforced microprocessor under test, and to test the time T taken to complete a run of the test program, and the area S of the SRAM component of the EDAC reinforced microprocessor under test used by the test program to run; S2. The time T taken to complete a run of the test program obtained from the test, the area S of the tested EDAC reinforced microprocessor SRAM component used to initialize the high-energy particle fluence rate F; S3. Continuously injecting high-energy particles according to the high-energy particle injection rate F to irradiate the EDAC reinforced microprocessor under test, and starting the test program of the EDAC reinforced microprocessor under test, and counting the number of soft errors of the test program not being completed within the time T and the number of soft errors of the running results being wrong, until the total injection amount reaches a preset value; S4. Calculate the single event upset cross section of the EDAC reinforced microprocessor under test according to the number of soft errors counted in step S3 and the total injection amount. 2. The method for testing the single-particle upset cross section of an EDAC-hardened microprocessor according to claim 1 is characterized in that, in the step S2, the high-energy particle fluence rate F is initialized according to the number of error bits m that can be corrected by the EDAC circuit in the EDAC-hardened microprocessor under test, the time T taken by the test program to complete one run, and the area S of the SRAM component of the EDAC-hardened microprocessor under test used in the test program run. 3. The method for testing the single event upset cross section of an EDAC-reinforced microprocessor according to claim 2, characterized in that in the step S2, the high-energy particle fluence rate F is initialized specifically according to the following formula: F＝(C ₀ ·m)/(T·S) Wherein, m is the number of error bits that can be corrected by the EDAC circuit in the EDAC-hardened microprocessor under test, C ₀ is a preset coefficient, T is the time taken by the test program to complete one run, and S is the area of the SRAM component of the EDAC-hardened microprocessor under test used by the test program to run. 4 . The method for testing the single event upset cross section of an EDAC-reinforced microprocessor according to claim 3 , wherein the preset coefficient C ₀ is a real number between 0.1 and 1. 5. The method for testing the single event upset cross section of a DAC-reinforced microprocessor according to claim 1, wherein the step S3 comprises: S301. Initialize the soft error count variable K=0; S302. Irradiate the EDAC reinforced microprocessor under test according to the high-energy particles at a fluence rate F and start counting the total fluence Q; S303. Determine whether the current total injection volume Q reaches the preset value, if yes, proceed to step S306, otherwise proceed to step S304; S304. Control the EDAC reinforced microprocessor under test to start running the test program. If the test program completes one run within the time T and outputs the run result, go to S305. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303. S305. Determine whether the running result currently output by the test program is correct. If it is correct, go to step S303. Otherwise, increase the value of the soft error count variable K by 1 and go to step S303. S306. Stop high-energy particle irradiation and output the current value of the soft error count variable K and the current total injection amount. 6. The method for testing the single event upset cross section of an EDAC-reinforced microprocessor according to any one of claims 1 to 5, characterized in that in the step S4, the single event upset cross section C of the EDAC-reinforced microprocessor under test is calculated according to the following formula: C = K/Q; Wherein, K is the soft error count value, and Q is the total injection amount. 7. The method for testing the single event upset cross section of an EDAC-reinforced microprocessor according to any one of claims 1 to 5, characterized in that the EDAC circuit in the EDAC-reinforced microprocessor under test has a correction-one-check-two function.