CN114968576A - a processor - Google Patents

Abstract

The present invention provides a processor, which can run in a host machine state or a virtual guest state according to application requirements, the host machine state and the virtual guest state respectively correspond to different instruction systems, and the processor includes: a host machine The first-level instruction cache is used to cache the instructions of the host state corresponding to the instruction system that can be executed by the processor running in the host state; the client level one instruction cache is used to cache the virtual guest state corresponding to the instruction system. instructions to be executed by a processor operating in a virtual guest state; and a selection circuit for selecting the host L1 instruction cache or the guest L1 instruction cache with the processing according to the processor operating state The corresponding components of the processor are in communication such that instructions are fetched from the host L1 instruction cache when the processor is operating in the host state, and instructions are fetched from the guest L1 instruction cache when the processor is operating in the virtual guest state.

Description

a processor

technical field

The present invention relates to the field of processor design, in particular, to the related field of processor instruction systems, and more particularly, to a processor that supports cross-instruction systems, that is, a processor applied to dual instruction caches.

Background technique

As the computing and control core of the computer system, the processor is the final execution unit for information processing and program operation. As shown in Figure 1, all existing processors have only one level one instruction cache (L1 IC) and one level one data cache (L1 DC). The execution unit executes, and the execution unit reads/writes the data cache as needed while executing instructions. Processors are designed to efficiently implement a specific instruction system, such as X86 instruction system, ARM instruction system, MIPS instruction system, RISCV instruction system, and so on. The existing processor design method can efficiently execute the code of the specific instruction system specified by the design, but if the code of other instruction systems needs to be executed at the same time, only the software binary translation technology can be used. The simple translation from one instruction system code to another instruction system code itself is not too expensive, which is equivalent to replacing hardware decoding with software decoding. For example, the Java virtual machine uses binary translation technology, and the performance impact is not significant. big. However, compared with the Java virtual machine, the binary translation of code between different instruction systems has a series of extra costs that are difficult for software to solve. The main reason is that in software translation, the translation module and the execution module share the same address space and operating environment, which will cause indirect transfer. The dynamic relocation of target addresses, the context switching saving in and out of the translation module, the connection of the translated basic block code traces, the overlapping of the address space of the translation module and the translated code, etc., make the code binary translation performance between different instruction systems relatively poor.

SUMMARY OF THE INVENTION

Therefore, the object of the present invention is to overcome the defects of the above-mentioned prior art, provide a kind of can support software translation and avoid indirect transfer target address dynamic relocation, the context environment switching preservation of entering and leaving translation module, the basic block code trace connection after translation, A handler for issues such as address space overlap between translation modules and translated code.

According to a first aspect of the present invention, a processor is provided, which can run in a host state or a virtual guest state according to application requirements, wherein the host state and the virtual guest state respectively correspond to different instruction systems, and the processing The device includes: a host-level instruction cache, which is used to cache instructions of the host state corresponding to the instruction system that can be executed by a processor running in the host state; a client-level instruction cache, which is used to cache the virtual guest The state corresponds to the instruction of the instruction system that can be executed by the processor running in the virtual guest state; and, the selection circuit is used for selecting the host machine level instruction cache or the client level instruction according to the processor operating state. The cache is in communication with corresponding components of the processor such that instructions are fetched from the host level one instruction cache when the processor is operating in the host state and from the guest level when the processor is operating in the virtual guest state Instruction cache fetches.

Preferably, run in the host state: a binary translation program, the binary translation program can be executed by the processor running in the host state for translating the source program of the instruction system corresponding to the virtual guest state into Code executable by the processor running in the virtual guest state and stored in the guest L1 instruction cache. Wherein, the client L1 instruction cache is configured to support read and write of processor execution components when the processor is running in a host state, and to support access read and write outside the processor.

In some embodiments of the present invention, the client L1 instruction cache is configured as a multi-way set-associative cache structure, wherein each cache line includes: a tag field, used to indicate the corresponding cache line in which it is located. The source program counter value before the virtual client source program is translated; the continuation line field, which is used to indicate whether there is a continuation line in the translated virtual client code; the code length field, which is used to store the code length of the cache line where it is located; and the translation The following instruction code field.

Preferably, when the processor is running in the virtual guest state, it is configured to fetch instructions from the client-level instruction high-level cache in the following manner: using the source program counter value of the virtual guest state to store the instruction in the client-level instruction cache Find the cache line in , and return the instruction of the cache line whose source program counter value matches the corresponding tag field, and calculate the next instruction fetch according to the source program counter value and code length field indicated by the tag field in the cache line that finally completes the instruction fetch the source program counter value. In some embodiments of the present invention, the processor is further configured to determine whether to continue searching for a continuation line in an adjacent next group of cache lines according to the indication of the continuation line field.

Preferably, the source program counter value of the next instruction fetch is the sum of the source program counter value and the code length field value indicated by the cache line tag field of the current instruction fetch.

In some embodiments of the present invention, the processor is configured to: run the host state to respond to the interrupt when an interrupt is generated by the invalidation of the client L1 instruction cache, and call a binary translation program to complete the virtual guest state correspondence Subsequent outstanding translation of the source program of the instruction set and writing the translated code into the client L1 instruction cache.

According to a second aspect of the present invention, a method for running a dual-instruction system based on the processor according to the first aspect of the present invention is provided, wherein the method includes: in response to an application requirement, running the processor in a state corresponding to the application requirement. state, wherein the processor can run the host machine state or the virtual guest state, the host machine state and the virtual guest state respectively correspond to different instruction systems; Level 1 instruction cache or guest level 1 instruction cache is in communication with corresponding components of the processor, such that instructions are fetched from the host level 1 instruction cache when the processor is running in the host state, and Fetches instructions from the guest L1 instruction cache while in virtual guest state.

Compared with the prior art, the advantages of the present invention are: the present invention proposes a dual instruction cache processor design method for the problem of insufficient performance when the existing processors are compatible with other instruction system programs through binary translation technology. Significantly improve the binary translation performance compatible with other instruction systems. It can be seen from the above embodiments that the present invention enables the processor to efficiently execute codes of other instruction systems by adding a small amount of hardware support, and solves the problem of efficient software compatibility across instruction systems.

Description of drawings

The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

1 is a schematic structural diagram of a processor in the prior art according to an embodiment of the present invention;

2 is a schematic structural diagram of a dual instruction cache processor according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a cache line data structure in a client L1 instruction high-level cache in a dual instruction cache processor according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

In the process of processor design research, the inventor found that a processor with a complex instruction system (such as an X86 processor) is actually a binary translation system with a different instruction system, but this binary translation system is implemented in hardware, which translates the complex instruction system into a binary translation system. The X86 instruction hardware is translated into microcode instructions similar to the reduced instruction system internally, while the performance of the X86 processor itself is not affected at all. The biggest difference between hardware translation and software translation is that translation components and execution components have independent operating environments and address spaces. Therefore, the problems such as indirect transfer target address dynamic relocation that cannot be overcome by software translation, hardware translation does not exist, but hardware translation is used. Translation costs far more than software translation. It can be seen that if the processor design can be improved so that the software binary translation can have an independent operating environment and address space like the hardware translation at runtime, the software binary translation will have the same performance as the hardware translation, which can greatly improve the performance of the software binary translation. to reduce hardware costs and improve the performance of software translation.

The technical idea of the present invention is briefly introduced below.

Modern high-performance processors all support CPU virtualization technology, that is, the processor adds a client running state to the original running state to run virtual client programs, and the original running state is used to run local The program, that is, the host program, based on this, the inventor proposes a processor design scheme: the original operating state of the processor is called the host state, and the binary translation program is run in the host state, and the translated code Running in the client state, the binary translator and the translated code can have independent running environment and address space. Among them, in terms of practical application, the hardware instruction system actually executed in the virtual guest state is the same as the host state. Through binary translation technology, the virtual guest state appears to be running an instruction system different from the host state. However, because the size of the translated code has changed from the pre-translation source code, usually larger, this is called code bloat. In order to keep the running address space of the translated code consistent with the source code before translation, the organization and storage of the translated code in the address space should be different from other programs on the host. Existing processors have only one L1 instruction cache, which is shared by the host program and the guest's translated code. This causes the client's translated code to break the independence of its own address space in order to use this shared L1 instruction cache. Therefore, the inventor proposes to add a dedicated client-level instruction cache in the processor supporting the CPU virtualization technology, which is specially used by the processor when running the virtual client program, which can completely solve the above-mentioned problem of sharing the first-level instruction cache. Problems caused by the instruction cache, so that software binary translation and hardware translation have similar performance.

According to an embodiment of the present invention, as shown in FIG. 2 , the present invention provides a design solution for a processor with dual instruction caches. The processor includes two first-level instruction caches, one of which is a traditional one for the sink. A Level 1 Instruction Cache (L1 IC) for the host state and a Level 1 Instruction Cache (L1 GIC) for the virtual guest state, the two instruction caches are connected to the processor through a one-of-two circuit The instruction fetch component, and a strobe signal sel selects which instruction cache the processor fetches instructions from. When the processor is running in the virtual guest state, the sel strobe signal will control the two-to-one circuit to select the instruction fetch component to L1 GIC, so that the instruction fetch unit fetches instructions from the client's first-level instruction cache. When the processor is running in the host state, the sel strobe signal will control the two-to-one circuit to select the instruction fetch unit to the L1 IC, so that the instruction fetch is made. The component fetches instructions from the host L1 instruction cache. According to an embodiment of the present invention, the L1 GIC can be read/written by the execution unit of the processor, or read/written by accesses from outside the processor. Usually, the execution unit only allows to read and write L1 when the processor is working in the host state. GIC, because the binary translation program runs in the host state, and the translated code runs in the client state, allowing the execution unit to read and write the L1 GIC to store the translated code in it, so that the processor allows the virtual guest. state can be fetched from the LI GIC.

According to an embodiment of the present invention, the organization of the L1 GIC is the same as that of the traditional L1 IC, and a multi-way set-associative cache structure is adopted, so this structure will not be repeated here. However, the specific cache line structure in L1 GIC is different from the traditional L1 IC in two points. Its structure is shown in Figure 3, where PC is the source instruction code program counter value (tag field), and C is the continuation line flag field. , CLEN is the source instruction code length field, Inst is the translated instruction code. Specifically, the difference between L1 GIC and L1 IC is:

The first difference is that the tag field in the cache line in the L1 GIC is the source program counter value (PC) before client translation, and the tag field in the traditional L1 IC is the physical memory address of the line of code.

The second difference is that the cache line of the L1 GIC adds two new fields: the continuation line field (C) and the source code length field (CLEN). Among them, the continuation line field indicates whether there is a continuation line in the translated code. If the continuation line field is 1, it means that there is a continuation line. If the continuation line field is 0, it means that there is no continuation line. If there is a continuation line, it needs to be in the next cache line. Continue to fetch; the source code length field (CLEN) is used to calculate the pre-translation source program counter value of the subsequent code (next fetch code).

In addition, the present invention also designs the processor as follows: if the client's first-level instruction cache L1 GIC fails, an interrupt/exception for the client's high-speed instruction cache invalidation will be generated, and the interrupt/exception can be sent to the processor for processing, It can also be sent to an external processor for processing. If issued to this processor, the processor returns from the virtual guest state to the host state in response to this interrupt/exception, for example, by calling a translator in the host state to complete the translation of subsequent guest instruction codes and write to the guest Machine Instruction Cache L1 GIC to respond to this interrupt/exception.

In order to better understand the working principle of the processor of the present invention, a single processor that supports CPU virtualization technology is used as an example to illustrate:

The processor initially runs in the host state, and when it needs to execute the client program across the instruction system, it enters the virtual client state by responding to the instruction to enter the client state.

When the processor enters the client state, the instruction fetching unit of the processor is switched to the client level one instruction cache for instruction fetching by setting the selection signal sel of the one-of-two circuit. For example, the sel signal entering the client state is 1, returning to the host state sel signal 0, and selecting different instruction caches for instruction fetching by setting the difference of 0/1.

The processor uses the source program counter value of the client program to look up the cache line in the client-specific instruction cache, and the value of the PC field of the cache line matches the source program counter value of the client program to be looked up. Returns the instruction that hits the cache line, and at the same time, if the continuation line field of the cache line is 1, the continuation line is searched according to the preset continuation line search strategy (for example, the continuation line is searched in the next adjacent group of cache lines, but the continuation line is searched for The row search strategy is not limited to this strategy, and can be set to any other convenient search strategy according to requirements). Among them, it should be noted that when the processor is running in the client state, it executes the instructions of the code line hit by the instruction fetch in the L1 GIC in sequence. After executing a line of instructions, it needs to calculate and read the code line and then continue to execute. The line of code is the source program counter value that needs to be calculated for the next instruction fetch. If the continuation line field is 0, the source program counter value of the next instruction fetch is calculated according to the program counter value and code length field of this cache line, that is, the source program counter value of the next instruction fetch = the PC value of this cache line + this The CLEN value of the cache line; if the continuation line field is 1, the source program counter value of the next instruction fetch is calculated in the same way after the continuation line fetch is completed, that is, the source program counter value of the next instruction fetch = the completed instruction fetch The PC value of the cache line + the CLEN value of the cache line that completed the fetch.

If the client L1 instruction cache lookup is invalid, an exception of client instruction cache invalidation is generated, the processor returns to the host state, executes the binary translation program, and updates the client L1 instruction cache through the processor execution unit. , enter the virtual client state again and continue to execute the client program across the instruction system.

Aiming at the problem of insufficient performance when the existing processor is compatible with other instruction system programs through binary translation technology, the present invention proposes a dual instruction cache processor design method, which can greatly improve the binary translation performance compatible with other instruction systems. It can be seen from the above embodiments that the present invention enables the processor to efficiently execute codes of other instruction systems by adding a small amount of hardware support, and solves the problem of efficient software compatibility across instruction systems.

It should be noted that although the steps are described above in a specific order, it does not mean that the steps must be executed in the above-mentioned specific order. In fact, some of these steps can be executed concurrently, or even change the order, as long as it can be achieved The required function can be.

The present invention may be a system, method and/or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the present invention.

A computer-readable storage medium may be a tangible device that retains and stores instructions for use by the instruction execution device. Computer-readable storage media may include, but are not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing, for example. More specific examples (non-exhaustive list) of computer readable storage media include: portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM) or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically coded devices, such as printers with instructions stored thereon Hole cards or raised structures in grooves, and any suitable combination of the above.

Various embodiments of the present invention have been described above, and the foregoing descriptions are exemplary, not exhaustive, and not limiting of the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. a kind of processor, it can run in host machine state or virtual guest state according to application requirement, described host machine state and virtual guest state correspond to different instruction systems respectively, it is characterized in that, described processor comprises: The host's first-level instruction cache is used to cache the instructions of the instruction system corresponding to the host state that can be executed by the processor running in the host state; a guest level one instruction cache for caching instructions of a virtual guest state corresponding to an instruction system that can be executed by a processor running in the virtual guest state; and A selection circuit, configured to select, according to the operating state of the processor, to connect the host-level instruction cache or the client-level instruction cache with the corresponding components of the processor, so that, when the processor operates in the host state The instruction is fetched from the host's first-level instruction cache when the processor is running in the virtual guest state, and the instruction is fetched from the guest's first-level instruction cache when the processor is running in the virtual guest state. 2. The processor according to claim 1, characterized in that, in the host state, running: A binary translation program, the binary translation program can be executed by the processor running in the host state and used for translating the source program of the instruction system corresponding to the virtual guest state into a executable program executable by the processor running in the virtual guest state code and stored in the client L1 instruction cache. 3. The processor of claim 2, wherein the client L1 instruction cache is configured to support read and write of processor execution components when the processor is running in a host state and to support external read and write operations of the processor. Access to read and write. 4. The processor of claim 3, wherein the client L1 instruction cache is configured as a multiple-way set-associative cache structure, wherein each cache line comprises: The tag field is used to indicate the source program counter value of the virtual client source program corresponding to its cache line before translation; The continuation line field is used to indicate whether there is a continuation line in the translated virtual client code; The code length field is used to store the code length of the cache line where it is located; and the translated instruction code field. 5 . The processor according to claim 4 , wherein, when the processor is running in a virtual guest state, it is configured to fetch instructions from the client-level instruction high-level cache in the following manner: 6 . The source program counter value of the virtual client state is used to find the cache line in the client-level instruction cache, and the instruction of the cache line whose source program counter value matches the corresponding tag field is returned. The label field indicates the source program counter value and the code length field calculates the source program counter value for the next instruction fetch. 6 . The processor of claim 5 , wherein the processor is further configured to determine whether to continue searching for a continuation line in an adjacent next group of cache lines according to the indication of the continuation line field. 7 . 7. The processor according to claim 5, wherein the source program counter value of the next instruction fetch is the difference between the source program counter value and the code length field value indicated by the cache line tag field of the instruction fetch this time. and. 8. The processor of claim 2, wherein the processor is configured to: run the host state to respond to the interrupt and invoke the binary translation program when an interrupt is generated by a client-level instruction cache invalidation to complete the subsequent unfinished translation of the source program of the virtual guest state corresponding to the instruction system and write the translated code into the client level one instruction cache. 9. A method for running a dual-instruction system based on any one of the processors of claims 1-8, wherein the method comprises: In response to application requirements, the processor is run in a state corresponding to the application requirements, wherein the processor can run a host state or a virtual guest state, and the host state and the virtual guest state respectively correspond to different instruction systems ; Based on the state corresponding to the application requirement, the host machine level I instruction cache or the client machine level I instruction cache is selected to communicate with the corresponding components of the processor, so that when the processor is running in the host machine state, the host machine is in the host machine state. The host L1 instruction cache fetches instructions, and fetches instructions from the guest L1 instruction cache when the processor is running in the virtual guest state. 10. An electronic device, characterized in that the device comprises: storage device; One or more processors as claimed in any of claims 1-9.

Images